Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation
Tanfer Alan1,a, Andreas Gerstlauer2 and Jörg Henkel1,b
1Karlsruhe Institute of Technology
aalan@kit.edu
bhenkel@kit.edu
2University of Texas at Austin
gerstl@ece.utexas.edu
ABSTRACT
Approximate computing trades off computation accuracy against energy efficiency. Algorithms from several modern application domains such as decision making and computer vision are tolerant to approximations while still meeting their requirements. The extent of approximation tolerance, however, significantly varies with a change in input characteristics and applications.
We propose a novel hybrid approach for the synthesis of runtime accuracy configurable hardware that minimizes energy consumption at area expense. To that end, first we explore instantiating multiple hardware blocks with different fixed approximation levels. These blocks can be selected dynamically and thus allow to configure the accuracy during runtime. They benefit from having fewer transistors and also synthesis relaxations in contrast to state-of-the-art gating mechanisms which only switch off a group of logic. Our hybrid approach combines instantiating such blocks with area-efficient gating mechanisms that reduce toggling activity, creating a fine-grained design-time knob on energy vs. area. Examining total energy savings for a Sobel Filter under different workloads and accuracy tolerances show that our method finds Pareto-optimal solutions providing up to 16% and 44% energy savings compared to state-of-the-art accuracyconfigurable gating mechanism and an exact hardware block, respectively, at 2x area cost.
