A RRAM-Based FPGA for Energy-Efficient Edge Computing
Xifan Tang*, Edouard Giacomin, Patsy Cadareanu, Ganesh Gore and Pierre-Emmanuel Gaillardon
Electrical and Computer Engineering, University of Utah, Salt Lake City, Utah, U.S.A.
*xifan.tang@utah.edu
ABSTRACT
The shift from centralized cloud to edge computing demands hardware systems with data processing capability at ultra-low power. Reconfigurable solutions such as Field- Programmable Gate Arrays (FPGAs) offer a high flexibility in terms of hardware implementation and are thus popular for use in many edge computing systems. However, breaking through the energy wall of FPGAs is a challenge, as low-power operation often requires compromising performances. In this paper, we study a low-power high-performance FPGA architecture exploiting Resistive Random Access Memory (RRAM) technology. To perform a comprehensive analysis, we introduce a novel design flow which can rapidly prototype FPGA fabrics from which accurate area, delay, and power results can be obtained. Based on full-chip layouts and SPICE simulations, we show that RRAM-based FPGAs can improve up to 8%/22%/16% in area/delay/power compared to SRAM-based counterparts at nominal voltage. Even when operated at a near-Vt supply, the proposed RRAM-based FPGA can improve the Energy-Delay Product by about 2 without any delay overhead, when compared to an SRAM-based FPGA. In addition, Monte Carlo simulations showed that the proposed RRAM-based FPGA architecture stays robust under different CMOS process corners as well as under a 30% RRAM resistance standard deviation.
