Sweeping for Leakage in Masked Circuit Layouts
Danilo Šijačića, Josep Balaschb and Ingrid Verbauwhedec
imec-COSIC, KU Leuven, Leuven, Belgium
adanilo.sijacic@esat.kuleuven.be
bjosep.balasch@esat.kuleuven.be
cingrid.verbauwhede@esat.kuleuven.be
ABSTRACT
Masking schemes are the most popular countermeasure against side-channel analysis. They theoretically decorrelate information leaked through inherent physical channels from the key-dependent intermediate values that occur during computation. Their provable security is devised under models that abstract complex physical phenomena of the underlying hardware. In this work, we investigate the impact of the physical layout to the side-channel security of masking schemes. For this we propose a model for co-simulation of the analog power distribution network with the digital logic core. Our study considers the drive of the power supply buffers, as well as parasitic resistors, inductors and capacitors. We quantify our findings using Test Vector Leakage Assessment by relative comparison to the parasitic-free model. Thus we provide a deeper insight into the potential layout sources of leakage and their magnitude.
Keywords: Masking, Coupling, Layout Parasitics, SPICE.
