Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle
Victor N. Kravets1, Jie-Hong R. Jiang2 and Heinz Riener3
1 IBM T. J. Watson Research Center New York, NY
kravets@us.ibm.com
2 National Taiwan University Taipei, Taiwan
jhjiang@ntu.edu.tw
3 EPFL Lausanne, Switzerland
heinz.riener@epfl.ch
ABSTRACT
The behavioral revisions to the design are frequent in the late stage of the semiconductor chip development. Quite often, their realization emphasizes incrementality that seeks minimum perturbation of the existing implementation. This tutorial paper poses the engineering change order (ECO) problem as the functional decomposition and proposes its solution in the form of the Boolean equations. We hope that the sufficient generality of the statement will be useful in extending the existing stateof- the-art design revision techniques. To assist in this process, we present an observed variety of design revisions encountered in the chip development cycle. The knowledge of such frequent and realistic ECOs is essential in advancing a tool's ability to yield compact implementation updates. We believe that sharing our experience of practical ECOs would benefit the research community in developing an open-source tool.
