BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory
Meng Zhang1,a, Fei Wu1,2,b, Qin Yu1, Weihua Liu1,c, Lanlan Cui1,d, Yahui Zhao1,e and Changsheng Xie1,f
1Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System, Engineering Research Center of data storage systems and Technology, Ministry of Education of China School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan China
2Shenzhen Research Institute of Huazhong University of Science and Technology, Shenzhen, China
azgmeng@hust.edu.cn
bwufei@hust.edu.cn
cliuweihua@hust.edu.cn
dcuilanlan@hust.edu.cn
eyahuiz@hust.edu.cn
fcs xie@hust.edu.cn
ABSTRACT
Three-dimensional (3D) NAND flash memory has high capacity and cell storage density by using the multi-bit technology and vertical stack architecture, but degrading data reliability due to high raw bit error rates (RBER) caused by program/erase (P/E) cycles and retention periods. Low-density parity-check (LDPC) codes become more popular error-correcting technologies to improve data reliability due to strong error correction capability, but introducing more decoding iterations at higher RBER. To reduce decoding iterations, this paper proposes BeLDPC: bit errors aware adaptive rate LDPC codes for 3D triple-level cell (TLC) NAND flash memory. Firstly, bit error characteristics in 3D charge trap TLC NAND flash memory are studied on a real FPGA testing platform, including asymmetric bit flipping and temporal locality of bit errors. Then, based on these characteristics, a high-efficiency LDPC code is designed. Experimental results show BeLDPC can reduce decoding iterations under different P/E cycles and retention periods.
