DATE'99 Author Index

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Abraham, J.
An Efficient Filter-based Approach for Combinational Verification [p. 132]

Abramovici, M.
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy [p. 747]

Adham, S.
Design for Testability Method for CML Digital Circuits [p. 360]

Agaësse, J.
Virtual Components Application and Customization [p. 726]

Al-Hashimi, B.
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths [p. 289]

Alippi, C.
A DAG-Based Design Approach for Reconfigurable VLIW Processors [p. 778]

Alzazeri, Y.
A Method of Distributed Controller Design for RTL Circuits [p. 774]

Antaki, B.
Design for Testability Method for CML Digital Circuits [p. 360]

Antreich, K.
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints [p. 323]

Arbetman, Y.
Functional Verification Methodology for Microprocessors using the Genesys Test-Program Generator -- Application to the X86 Microprocessors Family [p. 434]

Arnout, G.
C for System Level Design [p. 384]

Avedillo, M.
An Algorithm for Face-Constrained Encoding of Symbols using Minimum Code Length [p. 521]

B

Bagherzadeh, N.
Kernel Scheduling in Reconfigurable Computing [p. 90]

Baitinger, U.
Efficient Switching Activity Simulation under a Real Delay Model using a Bitparallel Approach [p. 459]

Bampi, S.
OTA Amplifiers Designed on Digital Sea-of-Transistors Array [p. 776]

Barna, C.
Object-Oriented Reuse Methodology for VHDL [p. 689]

Beckmann, F.
Time Constrained Modulo Scheduling with Global Resource Sharing [p. 210]

Beerel, P.
Symbolic Reachability Analysis of Large Finite State Machines using Don't Cares [p. 13]

Benini, L.
Dynamic Power Management for Non-Stationary Service Requests [p. 77]
Glitch Power Minimization by Gate Freezing [p. 163]
Specification and Validation of Distributed IP-based Designs with JavaCAD [p. 684]

Bernard, D.
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts [p. 576]

Bertrand, Y.
Design, Characterization and Modeling of a CMOS Magnetic Field Sensor [p. 239]

Bhattacharya, M.
A Physical Design Tool for Built-In Self-Repairable Static RAMS [p. 714]

Bogliolo, A.
Dynamic Power Management for Non-Stationary Service Requests [p. 77]
Specification and Validation of Distributed IP-based Designs with JavaCAD [p. 684]

Bolsens, I.
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement [p. 271]
A Single-Package Solution for Wireless Transceivers [p. 425]
Single Chip or Hybrid System Integration ? [p. 616]

Bowen, J.
Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]

Brayton, R.
Using Combinational Verification for Sequential Circuits [p. 138]

Breuer, P.
Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]

Buchenrieder, K.
Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components [p. 768]

Bühler, M.
Efficient Switching Activity Simulation under a Real Delay Model using a Bitparallel Approach [p. 459]

C

Cabodi, G.
Computing Timed Transition Relations for Sequential Cycle-Based Simulation [p. 8]

Calvez, J.
An Object-Based Executable Model for Simulation of Real-Time HW/SW Systems [p. 782]

Camurati, P.
Computing Timed Transition Relations for Sequential Cycle-Based Simulation [p. 8]

Cano, F.
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]

Carletta, J.
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs [p. 278]

Carrabina, J.
Digital MOS Circuit Partitioning with Symbolic Modeling [p. 503]

Carro, L.
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester [p. 184]

Chadha, R.
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]

Chakraborty, K.
A Physical Design Tool for Built-In Self-Repairable Static RAMS [p. 714]

Chang, F.
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]

Chang, J.
Codex-dp: Co-Design of Communicating Systems using Dynamic Programming [p. 568]

Chatterjee, A.
Minimal Length Diagnostic Tests for Analog Circuits using Test History [p. 189]
Parametric Fault Diagnosis for Analog Systems using Functional Mapping [p. 195]

Chaudhary, K.
Post-Placement Residual-Overlap Removal with Minimal Movement [p. 581]

Cherubal, S.
Parametric Fault Diagnosis for Analog Systems using Functional Mapping [p. 195]

Chiusano, S.
Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization [p. 516]

Choi, J.
OTA Amplifiers Designed on Digital Sea-of-Transistors Array [p. 776]

Chou, M.
Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's [p. 396]

Chung, E.
Dynamic Power Management for Non-Stationary Service Requests [p. 77]

Ciesielski, M.
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence [p. 638]

Claesen, L.
Formally Verified Redundancy Removal [p. 150]

Cmar, R.
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement [p. 271]

Corlette, D.
Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI [p. 788]

Corno, F.
Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization [p. 516]
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms [p. 754]

Costa, J.
Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's [p. 396]

Cota, E.
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester [p. 184]

D

Dabrowksi, J.
Experiences with Modeling of Analog and Mixed A/D Systems based on PWL Technique [p. 790]

Dalpasso, M.
Specification and Validation of Distributed IP-based Designs with JavaCAD [p. 684]

Dave, B.
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems [p. 97]

Dawson, C.
Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI [p. 788]

de Armas, V.
High Speed GaAs Subsystem Design using Feed through Logic [p. 509]

De Man, H.
A Single-Package Solution for Wireless Transceivers [p. 425]

De Micheli, G.
Dynamic Power Management for Non-Stationary Service Requests [p. 77]
Glitch Power Minimization by Gate Freezing [p. 163]
Polynomial Methods for Allocating Complex Components [p. 217]
Hardware Synthesis from C/C++ Models [p. 382]

de Neef, J.
Industrial Evaluation of DRAM Tests [p. 623]

Dhanwada, N.
Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis [p. 328]

Dick, R.
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis [p. 263]

Doboli, A.
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems [p. 338]

Donnay, S.
A Single-Package Solution for Wireless Transceivers [p. 425]

dos Santos, L.
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation [p. 609]

Drechsler, N.
Variable Reordering for Shared Binary Decision Diagrams using Output Probabilities [p. 758]

Drechsler, R.
Formal Verification of Word-Level Specifications [p. 52]
Variable Reordering for Shared Binary Decision Diagrams using Output Probabilities [p. 758]

Dutt, N.
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]

E

Eckl, K.
Retiming Sequential Circuits with Multiple Register Classes [p. 650]

Eckmueller, J.
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints [p. 323]

Endo, M.
High-Speed Software-based Platform for Embedded Software of a Single-Chip MPEG-2 Video Encoder LSI with HDTV Scalability [p. 303]

Engels, M.
A Single-Package Solution for Wireless Transceivers [p. 425]

Entrena, L.
Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization [p. 516]

Ernst, R.
Multi-language System Design [p. 696]

Espejo, J.
Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization [p. 516]

Eveking, H.
Automatic Verification of Scheduling Results in High-Level Synthesis [p. 59]

F

Favalli, M.
On the Design of Self-Checking Functional Units based on Shannon Circuits [p. 368]

Feldman, P.
Efficient Techniques for Modeling Chip-level Interconnect, Substrate and Package Parasitics [p. 418]

Feldmann, P.
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]

Ferguson, J.
A Digital Partial Built-In-Self-Test Structure for a High Performance Automatic Gain Control Circuit [p. 232]

Fernández, F.
An Accurate Error Control Mechanism for Simplification before Generation Algorithms [p. 412]

Fernandez, M.
Kernel Scheduling in Reconfigurable Computing [p. 90]

Ferrandi, F.
Symbolic Functional Vector Generation for VHDL Specifications [p. 442]

Figueras, J.
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing [p. 543]
Testing the Configurable Interconnect/Logic Interface of SRAM-based FPGA's [p. 618]

Filippi, E.
Fast Hardware-Software Co-Simulation using VHDL Models [p. 309]

Fleischmann, J.
Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components [p. 768]

Floyd, M.
Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI [p. 788]

Fornaciari, W.
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems [p. 762]
A DAG-Based Design Approach for Reconfigurable VLIW Processors [p. 778]

Fournier, L.
Functional Verification Methodology for Microprocessors using the Genesys Test-Program Generator -- Application to the X86 Microprocessors Family [p. 434]

France, R.
Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]

Friedman, E.
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits [p. 643]

Fujita, M.
On Reducing Transitions through Data Modifications [p. 82]
An Efficient Filter-based Approach for Combinational Verification [p. 132]

Fummi, F.
Symbolic Functional Vector Generation for VHDL Specifications [p. 442]

Fussell, D.
An Efficient Filter-based Approach for Combinational Verification [p. 132]

G

Gajski, D.
A Retargetable, Ultra-Fast Instruction Set Simulator [p. 298]
OpenJ: An Extensible System Level Design Language [p. 480]

Ganesh, V.
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]

Gerli, L.
Symbolic Functional Vector Generation for VHDL Specifications [p. 442]

Ghosh, A.
Hardware Synthesis from C/C++ [p. 387]

Gielen, G.
A Power Estimation Model for High-Speed CMOS A/D Converters [p. 401]

Gizopoulos, D.
An Effective BIST Architecture for Fast Multiplier Cores [p. 117]

Glass, T.
Combinational Equivalence Checking using Satisfiability and Recursive Learning [p. 145]

Gomes, A.
Minimal Length Diagnostic Tests for Analog Circuits using Test History [p. 189]

Graeb, H.
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints [p. 323]

Greenstein, G.
A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis [p. 780]

Grun, P.
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]

Guerra e Silva, L.
Algorithms for Solving Boolean Satisfiability in Combinational Circuits [p. 526]

Guerra, O.
An Accurate Error Control Mechanism for Simplification before Generation Algorithms [p. 412]

Gupta, A.
A Physical Design Tool for Built-In Self-Repairable Static RAMS [p. 714]

H

Haase, J.
Design Methodology for IP Providers [p. 728]

Halambi, A.
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]

Hamilton, S.
Self Recovering Controller and Datapath Codesign [p. 596]

Haniotakis, T.
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks [p. 112]

Hazard, P.
Design, Characterization and Modeling of a CMOS Magnetic Field Sensor [p. 239]

Hellebrand, S.
Symmetric Transparent BIST for RAMs [p. 702]

Hemani, A.
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems [p. 256]

Hendricx, S.
Formally Verified Redundancy Removal [p. 150]

Hermes, B
A Digital Partial Built-In-Self-Test Structure for a High Performance Automatic Gain Control Circuit [p. 232]

Hermida, R.
Kernel Scheduling in Reconfigurable Computing [p. 90]
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach [p. 766]

Hertwig, A.
Self Recovering Controller and Datapath Codesign [p. 596]

Hinrichsen, H.
Automatic Verification of Scheduling Results in High-Level Synthesis [p. 59]

Holzheuer, H.
How to use Knowledge in an Analysis Process [p. 498]

Hong, Y.
Symbolic Reachability Analysis of Large Finite State Machines using Don't Cares [p. 13]

Höreth, S.
Formal Verification of Word-Level Specifications [p. 52]

Hsiao, M.
Peak Power Estimation using Genetic Spot Optimization for Large VLSI Circuits [p. 175]

Hsu, Y.
FSMD Functional Partitioning for Low Power [p. 22]

Huertas, J.
An Algorithm for Face-Constrained Encoding of Symbols using Minimum Code Length [p. 521]

Huhn, M.
Verifying Imprecisely Working Arithmetic Circuits [p. 65]

Hvala, B.
On Analog Signature Analysis [p. 249]

Hwang, E.
FSMD Functional Partitioning for Low Power [p. 22]

Hwang, T.
Logic Transformation for Low Power Synthesis [p. 158]

I

Ikeda, M.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]

Iwasaki, H.
High-Speed Software-based Platform for Embedded Software of a Single-Chip MPEG-2 Video Encoder LSI with HDTV Scalability [p. 303]

Iyer, M.
Wavefront Technology Mapping [p. 531]

J

Jacobs, E.
Identification and Exploitation of Symmetries in DSP Algorithms [p. 602]

Jacome, M.
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs [p. 676]

Jain, J.
An Efficient Filter-based Approach for Combinational Verification [p. 132]

Jantsch, A.
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems [p. 256]
Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification [p. 562]

Jäschke, C.
Time Constrained Modulo Scheduling with Global Resource Sharing [p. 210]

Jerraya, A.
Multi-language System Design [p. 696]

Jess, J.
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation [p. 609]

Jha, N.
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis [p. 263]

Jochens, G.
A New Parameterizable Power Macro-Model for Datapath Components [p. 29]

Junkkari, J.
Higher Product Complexity and Shorter Development Time - Continuous Challenge to Design and Test Environment [p. 2]

K

Kalla, P.
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence [p. 638]

Kang, S.
Logic Transformation for Low Power Synthesis [p. 158]
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks [p. 473]

Kapp, K.
Efficient Switching Activity Simulation under a Real Delay Model using a Bitparallel Approach [p. 459]

Kapur, S.
Efficient Techniques for Modeling Chip-level Interconnect, Substrate and Package Parasitics [p. 418]

Kaul, M.
Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs [p. 202]

Khare, A.
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]

Kim, H.
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks [p. 473]

Kim, K.
Logic Transformation for Low Power Synthesis [p. 158]

Klavzar, S.
On Analog Signature Analysis [p. 249]

Kloos, C.
Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]

Kolla, R.
Spanning Tree Based State Encoding for Low Power Dissipation [p. 168]

Kondo, T.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]

Konijnenburg, M.
Illegal State Space Identification for Sequential Circuit Test Generation [p. 741]

Kranitis, N.
An Effective BIST Architecture for Fast Multiplier Cores [p. 117]

Kress, R.
Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components [p. 768]

Kropf, T.
Verifying Imprecisely Working Arithmetic Circuits [p. 65]

Krupnova, H.
Iterative Improvement based Multi-Way Netlist Partitioning for FPGAs [p. 587]

Kruse, L.
A New Parameterizable Power Macro-Model for Datapath Components [p. 29]

Kuchcinski, K.
Integrated Resource Assignment and Scheduling of Task Graphs using Finite Domain Constraints [p. 772]

Kuh, E.
Coupled Noise Estimation for Distributed RC Interconnect Model [p. 664]

Kulkarni, S.
A Physical Design Tool for Built-In Self-Repairable Static RAMS [p. 714]

Kumar, S.
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems [p. 256]

Kunkel, J.
Hardware Synthesis from C/C++ [p. 387]

Kurdahi, F.
Kernel Scheduling in Reconfigurable Computing [p. 90]

L

Landrault, C.
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts [p. 576]

Latorre, L.
Design, Characterization and Modeling of a CMOS Magnetic Field Sensor [p. 239]

Laur, R.
Time Constrained Modulo Scheduling with Global Resource Sharing [p. 210]

Laurent, B.
Virtual Components Application and Customization [p. 726]

Lauwers, E.
A Power Estimation Model for High-Speed CMOS A/D Converters [p. 401]

Lavagno, L.
Fast Hardware-Software Co-Simulation using VHDL Models [p. 309]

Lechner, A.
A Digital Partial Built-In-Self-Test Structure for a High Performance Automatic Gain Control Circuit [p. 232]

Legl, C.
Retiming Sequential Circuits with Multiple Register Classes [p. 650]

Leupers, R.
Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors [p. 105]

Levinger, M.
Functional Verification Methodology for Microprocessors using the Genesys Test-Program Generator -- Application to the X86 Microprocessors Family [p. 434]

Liao, S.
Hardware Synthesis from C/C++ [p. 387]

Lin, X.
Full Scan Fault Coverage with Partial Scan [p. 468]

Liu, C.
Logic Transformation for Low Power Synthesis [p. 158]

Liu, X.
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits [p. 643]

Logothetis, G.
Verifying Imprecisely Working Arithmetic Circuits [p. 65]

Long, D.
Efficient Techniques for Modeling Chip-level Interconnect, Substrate and Package Parasitics [p. 418]

Lopez, J.
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs [p. 676]

Lubaszewski, M.
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester [p. 184]

M

Maamar, A.
ADOLT -- An ADaptable On-Line Testing Scheme for VLSI Circuits [p. 770]

Macii, A.
Glitch Power Minimization by Gate Freezing [p. 163]

Macii, E.
Glitch Power Minimization by Gate Freezing [p. 163]

Madrid, N.
Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]

Maestre, R.
Kernel Scheduling in Reconfigurable Computing [p. 90]

Maestro, J.
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach [p. 766]

Makris, Y.
Channel-Based Behavioral Test Synthesis for Improved Module Reachability [p. 283]

Manhaeve, H.
On-Chip Transient Current Monitor for Testing of Low-Voltage CMOS IC [p. 538]

Mansouri, N.
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs [p. 223]

Marques-Silva, J.
Combinational Equivalence Checking using Satisfiability and Recursive Learning [p. 145]
Algorithms for Solving Boolean Satisfiability in Combinational Circuits [p. 526]

Martínez, M.
An Algorithm for Face-Constrained Encoding of Symbols using Minimum Code Length [p. 521]

Martinolle, F.
Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI [p. 788]

Maurer, P.
Software Bit-Slicing: A Technique for Improving Simulation Performance [p. 786]

Mazumder, P.
A Physical Design Tool for Built-In Self-Repairable Static RAMS [p. 714]

Meinel, C.
Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering [p. 760]

Merten, M.
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy [p. 747]

Mesman, B.
Identification and Exploitation of Symmetries in DSP Algorithms [p. 602]

Metra, C.
On the Design of Self-Checking Functional Units based on Shannon Circuits [p. 368]

Michael, M.
ATPG Tools for Delay Faults at the Functional Level [p. 631]

Minami, T.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]

Montiel-Nelson, J.
High Speed GaAs Subsystem Design using Feed through Logic [p. 509]

Morawiec, A.
Cycle-based Simulation with Decision Diagrams [p. 454]

Moser, E.
Case Study: System Model of Crane and Embedded Control [p. 721]

Mozos, D.
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach [p. 766]

Mukherjee, R.
An Efficient Filter-based Approach for Combinational Verification [p. 132]

Müller-Schloer, C.
An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems [p. 784]

Murgai, R.
On Reducing Transitions through Data Modifications [p. 82]

N

Nag, S.
Post-Placement Residual-Overlap Removal with Minimal Movement [p. 581]

Naganuma, J.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]
High-Speed Software-based Platform for Embedded Software of a Single-Chip MPEG-2 Video Encoder LSI with HDTV Scalability [p. 303]

Nagaraj, N.
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]

Nebel, W.
A New Parameterizable Power Macro-Model for Datapath Components [p. 29]
Data Type Analysis for Hardware Synthesis from Object-Oriented Models [p. 491]
Java, VHDL-AMS, Ada or C for System Level Specifications? [p. 720]
Case Study: System Model of Crane and Embedded Control [p. 721]

Nicolaidis, M.
A CAD Framework for Generating Self-Checking Multipliers based On Residue Codes [p. 122]
Scaling Deeper to Submicron: On-Line Testing to the Rescue [p. 432]
A One-Bit Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection [p. 792]

Nicolau, A.
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]

Nicolici, N.
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths [p. 289]

Niggemeyer, D.
Parametric Built-In Self-Test of VLSI Systems [p. 376]

Nikolos, D.
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks [p. 112]

Nitta, K.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]

Nooshabadi, S.
High Speed GaAs Subsystem Design using Feed through Logic [p. 509]

Nöth, W.
Spanning Tree Based State Encoding for Low Power Dissipation [p. 168]

Nouet, P.
Design, Characterization and Modeling of a CMOS Magnetic Field Sensor [p. 239]
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts [p. 576]

Noufal, I.
A CAD Framework for Generating Self-Checking Multipliers based On Residue Codes [p. 122]

Nourani, M.
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs [p. 278]

Novak, F.
On Analog Signature Analysis [p. 249]

Núñez, A.
High Speed GaAs Subsystem Design using Feed through Logic [p. 509]

Nunez-Aldana, A.
Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis [p. 328]
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis [p. 406]

O'Nils, M.
Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification [p. 562]

O

Ochiai, K.
High-Speed Software-based Platform for Embedded Software of a Single-Chip MPEG-2 Video Encoder LSI with HDTV Scalability [p. 303]

Ogura, T.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]
High-Speed Software-based Platform for Embedded Software of a Single-Chip MPEG-2 Video Encoder LSI with HDTV Scalability [p. 303]

Orailoglu, A.
Channel-Based Behavioral Test Synthesis for Improved Module Reachability [p. 283]
Self Recovering Controller and Datapath Codesign [p. 596]

P

Papachristou, C.
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs [p. 278]
A Method of Distributed Controller Design for RTL Circuits [p. 774]

Papaefthymiou, M.
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits [p. 643]

Papesch, M.
Efficient Switching Activity Simulation under a Real Delay Model using a Bitparallel Approach [p. 459]

Paschalis, A.
An Effective BIST Architecture for Fast Multiplier Cores [p. 117]

Pasquier, O.
An Object-Based Executable Model for Simulation of Real-Time HW/SW Systems [p. 782]

Passerone, C.
Computing Timed Transition Relations for Sequential Cycle-Based Simulation [p. 8]

Pedram, M.
Battery-Powered Digital CMOS Design [p. 72]
Codex-dp: Co-Design of Communicating Systems using Dynamic Programming [p. 568]

Peixoto, H.
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs [p. 676]

Petrie, M.
Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]

Pomeranz, I.
Full Scan Fault Coverage with Partial Scan [p. 468]

Poncino, M.
Glitch Power Minimization by Gate Freezing [p. 163]

Portal, J.
Testing the Configurable Interconnect/Logic Interface of SRAM-based FPGA's [p. 618]

Pozzi, L.
A DAG-Based Design Approach for Reconfigurable VLIW Processors [p. 778]

Pressecq, F.
Design, Characterization and Modeling of a CMOS Magnetic Field Sensor [p. 239]

Psarakis, M.
An Effective BIST Architecture for Fast Multiplier Cores [p. 117]

Pulka, A.
Experiences with Modeling of Analog and Mixed A/D Systems based on PWL Technique [p. 790]

Putzke-Röming, W.
Data Type Analysis for Hardware Synthesis from Object-Oriented Models [p. 491]

Q

Quer, S.
Computing Timed Transition Relations for Sequential Cycle-Based Simulation [p. 8]

Quintana, J.
An Algorithm for Face-Constrained Encoding of Symbols using Minimum Code Length [p. 521]

R

Radetzki, M.
Data Type Analysis for Hardware Synthesis from Object-Oriented Models [p. 491]

Raik, J.
Cycle-based Simulation with Decision Diagrams [p. 454]

Sequential Circuit Test Generation using Decision Diagram Models [p. 736]

Ranjan, R,
Using Combinational Verification for Sequential Circuits [p. 138]

Rayane, I.
A One-Bit Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection [p. 792]

Reddy, S.
Full Scan Fault Coverage with Partial Scan [p. 468]

Renovell, M.
Testing the Configurable Interconnect/Logic Interface of SRAM-based FPGA's [p. 618]

Reutter, A.
An Efficient Reuse System for Digital Circuit Design [p. 38]

Ribas, L.
Digital MOS Circuit Partitioning with Symbolic Modeling [p. 503]

Richardson, A.
A Digital Partial Built-In-Self-Test Structure for a High Performance Automatic Gain Control Circuit [p. 232]

Rijnders, L.
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement [p. 271]

Ritter, G.
Automatic Verification of Scheduling Results in High-Level Synthesis [p. 59]

Rius, J.
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing [p. 543]

Roca, E.
An Accurate Error Control Mechanism for Simplification before Generation Algorithms [p. 412]

Rodríguez-García, J.
An Accurate Error Control Mechanism for Simplification before Generation Algorithms [p. 412]

Rodríguez-Vázquez, A.
An Accurate Error Control Mechanism for Simplification before Generation Algorithms [p. 412]

Rosenstiel, W.
An Efficient Reuse System for Digital Circuit Design [p. 38]

Object-Oriented Reuse Methodology for VHDL [p. 689]

Emulation of a Fast Reactive Embedded System using a Real Time Operating System [p. 764]

Royo, A.
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs [p. 676]

Rudnick, E.
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy [p. 747]

A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis [p. 780]

Rüffer, M.
Parametric Built-In Self-Test of VLSI Systems [p. 376]

Russell, G.
ADOLT -- An ADaptable On-Line Testing Scheme for VLSI Circuits [p. 770]

S

Sami, M.
A DAG-Based Design Approach for Reconfigurable VLIW Processors [p. 778]

San Millán, E.
Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization [p. 516]

Sangiovanni-Vincentelli, A.
Fast Hardware-Software Co-Simulation using VHDL Models [p. 309]

Santos, M.
Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip using HDL [p. 549]

Santoso, Y.
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy [p. 747]

Sarmiento, R.
High Speed GaAs Subsystem Design using Feed through Logic [p. 509]

Sasaki, H.
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstract State Machine [p. 353]

Saucier, G.
Iterative Improvement based Multi-Way Netlist Partitioning for FPGAs [p. 587]

Savaria, Y.
Design for Testability Method for CML Digital Circuits [p. 360]

Scarsi, R.
Glitch Power Minimization by Gate Freezing [p. 163]

Schaumont, P.
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement [p. 271]

Scherber, S.
An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems [p. 784]

Schilp, W.
Software Bit-Slicing: A Technique for Improving Simulation Performance [p. 786]

Schmidt, E.
A New Parameterizable Power Macro-Model for Datapath Components [p. 29]

Schneider, K.
Verifying Imprecisely Working Arithmetic Circuits [p. 65]

Schwencker, R.
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints [p. 323]

Sciuto, D.
Symbolic Functional Vector Generation for VHDL Specifications [p. 442]
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems [p. 762]

Seepold, R.
Virtual Socket Interface Alliance [p. 182]

Sgroi, M.
Fast Hardware-Software Co-Simulation using VHDL Models [p. 309]

Sheehan, B.
Projective Convolution: RLC Model-Order Reduction using the Impulse Response [p. 669]

Shi, C.
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams [p. 448]

Shin, J.
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks [p. 473]

Sidiropulos, M.
On-Chip Transient Current Monitor for Testing of Low-Voltage CMOS IC [p. 538]

Silvano, C.
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems [p. 762]

Silveira, L.
Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's [p. 396]
Algorithms for Solving Boolean Satisfiability in Combinational Circuits [p. 526]

Singh, H.
Kernel Scheduling in Reconfigurable Computing [p. 90]

Singhal, V.
Using Combinational Verification for Sequential Circuits [p. 138]

Smith, J.
Polynomial Methods for Allocating Complex Components [p. 217]

Somenzi, F.
Using Combinational Verification for Sequential Circuits [p. 138]

Sonza Reorda, M.
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms [p. 754]

Squillero, G.
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms [p. 754]

Stammermann, A.
Data Type Analysis for Hardware Synthesis from Object-Oriented Models [p. 491]

Stangier, C.
Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering [p. 760]

Steckstor, T.
Emulation of a Fast Reactive Embedded System using a Real Time Operating System [p. 764]

Stok, L.
Wavefront Technology Mapping [p. 531]

Stopjaková, V.
On-Chip Transient Current Monitor for Testing of Low-Voltage CMOS IC [p. 538]

Strehl, K.
Interval Diagram Techniques for Symbolic Model Checking of Petri Nets [p. 756]

Suguri, K.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]

Sullivan, A.
Wavefront Technology Mapping [p. 531]

T

Tabbara, B.
Fast Hardware-Software Co-Simulation using VHDL Models [p. 309]

Takayama, K.
An Efficient Filter-based Approach for Combinational Verification [p. 132]

Tan, X.
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams [p. 448]

Teixeira, J.
Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip using HDL [p. 549]

Thiele, L.
Interval Diagram Techniques for Symbolic Model Checking of Petri Nets [p. 756]

Thoma, P.
Automotive Electronics -- A Challenge for Systems Engineering [p. 4]

Thornton, M.
Variable Reordering for Shared Binary Decision Diagrams using Output Probabilities [p. 758]

Timmer, A.
Identification and Exploitation of Symmetries in DSP Algorithms [p. 602]

Toulouse, A.
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts [p. 576]

Tragoudas, S.
ATPG Tools for Delay Faults at the Functional Level [p. 631]

Tröster, G.
Potentials of Chip-Package Co-Design for High-Speed Digital Applications [p. 423]

Tsiatouhas, Y.
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks [p. 112]

U

Ubar, R.
Cycle-based Simulation with Decision Diagrams [p. 454]
Sequential Circuit Test Generation using Decision Diagram Models [p. 736]

Upadhyaya, S.
On Programmable Memory Built-in Self Test Architectures [p. 708]

V

Vahid, F.
FSMD Functional Partitioning for Low Power [p. 22]

van de Goor, A.
Industrial Evaluation of DRAM Tests [p. 623]
Illegal State Space Identification for Sequential Circuit Test Generation [p. 741]

van der Linden, J.
Illegal State Space Identification for Sequential Circuit Test Generation [p. 741]

Van Der Steen, J.
Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints [p. 556]

van Eijk, C.
Identification and Exploitation of Symmetries in DSP Algorithms [p. 602]

van Staveren, A.
Systematic Biasing of Negative Feedback Amplifiers [p. 318]

Velasco-Medina, J.
A One-Bit Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection [p. 792]

Vemuri, R.
Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs [p. 202]
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs [p. 223]
Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis [p. 328]
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems [p. 338]
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis [p. 406]

Vercauteren, S.
Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints [p. 556]

Vergos, H.
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks [p. 112]

Verhoeven, C.
Systematic Biasing of Negative Feedback Amplifiers [p. 318]

Verkest, D.
Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints [p. 556]

Vernalde, S.
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement [p. 271]

W

Wakabayashi, K.
C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber" [p. 390]

Wambacq, P.
A Single-Package Solution for Wireless Transceivers [p. 425]

Wang, J.
Coupled Noise Estimation for Distributed RC Interconnect Model [p. 664]

Weiß,K.
Emulation of a Fast Reactive Embedded System using a Real Time Operating System [p. 764]

Williams, J.
Variable Reordering for Shared Binary Decision Diagrams using Output Probabilities [p. 758]

Williams, T.
Testing in Nanometer Technologies [p. 5]

Wu, J.
A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis [p. 780]

Wu, Q.
Battery-Powered Digital CMOS Design [p. 72]

Wunderlich, H.
Symmetric Transparent BIST for RAMs [p. 702]

X

Xiong, N.
Design for Testability Method for CML Digital Circuits [p. 360]

Y

Yang, Z.
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analogue Circuits [p. 244]

Yarmolik, V.
Symmetric Transparent BIST for RAMs [p. 702]

Ye, L.
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]

Yoshitome, T.
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]

Yu, Q.
Coupled Noise Estimation for Distributed RC Interconnect Model [p. 664]

Z

Zarrineh, K.
On Programmable Memory Built-in Self Test Architectures [p. 708]

Zhu, J.
A Retargetable, Ultra-Fast Instruction Set Simulator [p. 298]
OpenJ: An Extensible System Level Design Language [p. 480]

Ziad, H.
A Single-Package Solution for Wireless Transceivers [p. 425]

Zorian, Y.
An Effective BIST Architecture for Fast Multiplier Cores [p. 117]
Scaling Deeper to Submicron: On-Line Testing to the Rescue [p. 432]
Testing the Configurable Interconnect/Logic Interface of SRAM-based FPGA's [p. 618]

Zwolinski, M.
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analogue Circuits [p. 244]