DATE 2009 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]


A

Abadir, M.
PDF icon TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
Abate, F.
PDF icon A Study of the Single Event Effects Impact on Functional Mapping within Flash-Based FPGAs [p. 1226]
Abbaspour, S.
PDF icon Efficient Compression and Handling of Current Source Model Library Waveforms [p. 1178]
Abel, N.
PDF icon DPR in High Energy Physics [p. 39]
Abid, M.
PDF icon High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation [p. 940]
Abouelella, F.
PDF icon Automatically Mapping Applications to a Self-Reconfiguring Platform [p. 964]
Aboulhamid, E.M.
PDF icon Co-Simulation Based Platform for Wireless Protocols Design Explorations [p. 874]
Acquaviva, A.
PDF icon Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip [p. 906]
PDF icon Flexible Energy-Aware Simulation of Heterogeneous Wireless Sensor Networks [p. 1638]
Afratis, P.
PDF icon Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
Afzali-Kusha, A.
PDF icon An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
Aggarwal, A.
PDF icon Architectural Support for Low Overhead Detection of Memory Violations [p. 652]
Ahmed, S.Z.
PDF icon Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor [p. 184]
Aho, E.
PDF icon A Case for Multi-Channel Memories in Video Recording [p. 934]
Ain, A.
PDF icon A Formal Approach for Specification-Driven AMS Behavioral Model Generation [p. 1512]
Aitken, R.
PDF icon Impact of Voltage Scaling on Nanoscale SRAM Reliability [p. 387]
Akella, V.
PDF icon Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing [p. 1530]
Akin, A.
PDF icon A High Performance Reconfigurable Motion Estimation Hardware Architecture [p. 882]
Al Faruque, M.A.
PDF icon Configurable Links for Runtime Adaptive On-Chip Communication [p. 256]
Albers, K.
PDF icon Improved Worst-Case Response-Time Calculations by Upper-Bound Conditions [p. 105]
Al-Hashimi, B.M.
PDF icon Variation Resilient Adaptive Controller for Subthreshold Circuits [p. 142]
PDF icon Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing [p. 1349]
PDF icon An Automated Design Flow for Vibration-Based Energy Harvester Systems [p. 1391]
PDF icon Selective State Retention Design Using Symbolic Simulation [p. 1644]
Ali, S.
PDF icon Improved Performance and Variation Modelling for Hierarchical-Based Optimisation of Analogue Integrated Circuits [p. 712]
Alimohammad, A.
PDF icon A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development and Verification [p. 45]
Alles, M.
PDF icon A Novel LDPC Decoder for DVB-S2 IP [p. 1308]
Alves, N.
PDF icon Detecting Errors Using Multi-Cycle Invariance Information [p. 791]
Ammari, A.C.
PDF icon High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation [p. 940]
Angiolini, F.
PDF icon Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces [p. 262]
Ansaloni, G.
PDF icon Heterogeneous Coarse-Grained Processing Elements: A Template Architecture for Embedded Processing Acceleration [p. 542]
Arakida, H.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Ardestani, E.K.
PDF icon Using Randomization to Cope with Circuit Uncertainty [p. 815]
Ares, F.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Aridhi, S.
PDF icon Scalable Compile-Time Scheduler for Multi-Core Architectures [p. 1552]
Arjomand, M.
PDF icon A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM [p. 566]
Armengaud, E.
PDF icon Remote Measurement of Local Oscillator Drifts in FlexRay Networks [p. 1082]
Arnold, O.
PDF icon Dimensioning Heterogeneous MPSoCs via Parallelism Analysis [p. 554]
Arpinen, T.
PDF icon Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA [p. 244]
Arslan, T.
PDF icon An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures [p. 33]
Ashby, T.J.
PDF icon Exploring Parallelizations of Applications for MPSoC Platforms Using MPA [p. 1148]
Atienza, D.
PDF icon Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis [p. 616]
PDF icon Dynamic Thermal Management in 3D Multicore Architectures [p. 1410]
Avnit, K.
PDF icon A Formal Approach to Design Space Exploration of Protocol Converters [p. 129]
Ayala, J.
PDF icon Dynamic Thermal Management in 3D Multicore Architectures [p. 1410]

B

Bachmann, C.
PDF icon A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing [p. 1614]
Bae, S.
PDF icon Exploiting Clock Skew Scheduling for FPGA [p. 1524]
Baert, R.
PDF icon Exploring Parallelizations of Applications for MPSoC Platforms Using MPA [p. 1148]
Baghdadi, A.
PDF icon ASIP-Based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications [p. 1620]
Bahar, R.I.
PDF icon Detecting Errors Using Multi-Cycle Invariance Information [p. 791]
Bakir, M.
PDF icon Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
Balakrishnan, M.
PDF icon Cache Aware Compression for Processor Debug Support [p. 208]
PDF icon A Generic Platform for Estimation of Multi-Threaded Program Performance on Heterogeneous Multiprocessor [p. 1018]
Balasa, F.
PDF icon Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
Baneres, D.
PDF icon Variable-Latency Design by Function Speculation [p. 1704]
Bannow, N.
PDF icon Analogue Mixed Signal Simulation Using Spice and SystemC [p. 284]
Baojun, Q.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Bardine, A.
PDF icon A Power-Efficient Migration Mechanism for D-NUCA Caches [p. 598]
Barke, E.
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Baronti, F.
PDF icon Distributed Sensor For Steering Wheel Grip Force Measurement In Driver Fatigue Detection [p. 894]
Bartolini, A.
PDF icon Visual Quality Analysis for Dynamic Backlight Scaling in LCD Systems [p. 1428]
Bastian, M.
PDF icon A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
Basu, S.
PDF icon Multi-Clock SOC Design Using Protocol Conversion [p. 123]
Bauer, L.
PDF icon Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors [p. 958]
PDF icon A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC Video Codec [p. 1434]
Baumgartner, J.
PDF icon Speculative Reduction-Based Scalable Redundancy Identification [p. 1674]
PDF icon Scalable Liveness Checking via Property-Preserving Transformations [p. 1680]
Bazargan, K.
PDF icon Using Randomization to Cope with Circuit Uncertainty [p. 815]
Becker, J.
PDF icon Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems [p. 178]
Bedani, M.
PDF icon A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard [p. 364]
Beeby, S.P.
PDF icon An Automated Design Flow for Vibration-Based Energy Harvester Systems [p. 1391]
Behrend, J.
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Beivide, R.
PDF icon Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap [p. 530]
Bekooij, M.
PDF icon Programming MPSoC Platforms: Road Works Ahead! [p. 1584]
Bellasi, P.
PDF icon Predictive Models for Multimedia Applications Power Consumption Based on Use-Case and OS Level Analysis [p. 1446]
Beltrame, G.
PDF icon A Real-Time Application Design Methodology for MPSoCs [p. 767]
Ben Jamaa, M.H.
PDF icon Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis [p. 622]
Benini, L.
PDF icon SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips [p. 9]
PDF icon Physically Clustered Forward Body Biasing for Variability Compensation in Nano-Meter CMOS Design [p. 154]
PDF icon Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces [p. 262]
PDF icon Robust Non-Preemptive Hard Real-Time Scheduling for Clustered Multicore Platforms [p. 803]
PDF icon Efficient OpenMP Support and Extensions for MPSoCs with Explicitly Managed Memory Hierarchy [p. 809]
PDF icon Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip [p. 906]
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
PDF icon Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation Techniques for Full-Swing and Low-Swing On-Chip Communication Channels [p. 1404]
PDF icon Visual Quality Analysis for Dynamic Backlight Scaling in LCD Systems [p. 1428]
Benoit, P.
PDF icon Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC [p. 1564]
Berekovic, M.
PDF icon A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing [p. 1614]
Bernasconi, A.
PDF icon On Decomposing Boolean Functions via Extended Cofactoring [p. 1464]
Berning, M.
PDF icon Error Correction in Single-Hop Wireless Sensor Networks - A Case Study [p. 1296]
Bertacco, V.
PDF icon A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs [p. 21]
PDF icon Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't Cares [p. 582]
PDF icon CASPAR: Hardware Patching for Multi-Core Processors [p. 658]
PDF icon GCS: High-Performance Gate-Level Simulation with GP-GPUs [p. 1332]
Bertels, K.
PDF icon Algorithms for the Automatic Extension of an Instruction-Set [p. 548]
PDF icon Toward a Runtime System for Reconfigurable Computers: A Virtualization Approach [p. 1576]
Bertozzi, D.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
PDF icon Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation Techniques for Full-Swing and Low-Swing On-Chip Communication Channels [p. 1404]
Bhagawat, P.
PDF icon Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO System [p. 870]
Bhattacharyya, S.S.
PDF icon A Generalized Scheduling Approach for Dynamic Dataflow Applications [p. 111]
Biggs, J.
PDF icon Selective State Retention Design Using Symbolic Simulation [p. 1644]
Bild, D.R
PDF icon Minimization of NBTI Performance Degradation Using Internal Node Control [p. 148]
Blaauw, D.
PDF icon A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs [p. 21]
Bobba, S.
PDF icon Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis [p. 616]
Boers, D.
PDF icon Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems [p. 519]
Bok, G.E.
PDF icon Minimization of NBTI Performance Degradation Using Internal Node Control [p. 148]
Bolzani, L.
PDF icon Enabling Concurrent Clock and Power Gating in an Industrial Design Flow [p. 334]
Bombieri, N.
PDF icon Functional Qualification of TLM Verification [p. 190]
PDF icon Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches [p. 1500]
Bonhomme, Y.
PDF icon System-Level Hardware-Based Protection of Memories against Soft-Errors [p. 1222]
Bonnaud, P.-H.
PDF icon Cross-Coupling in 65nm Fully Integrated EDGE System on Chip - Design and Cross-Coupling Prevention of Complex 65nm SoC [p. 1045]
Bononi, L.
PDF icon aEqualized: A Novel Routing Algorithm for the Spidergon Network on Chip [p. 749]
Bonzini, P.
PDF icon Heterogeneous Coarse-Grained Processing Elements: A Template Architecture for Embedded Processing Acceleration [p. 542]
Boonen, M.
PDF icon Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0 [p. 316]
Borde, E.
PDF icon Mode-Based Reconfiguration of Critical Software Component Architectures [p. 1160]
Bouchhima, A.
PDF icon Extending IP-XACT to Support an MDE Based Approach For SoC Design [p. 586]
Bougard, B.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
PDF icon Finite Precision Processing in Wireless Applications [p. 1230]
PDF icon Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors [p. 1608]
Boutillon, E.
PDF icon Optimizing Data Flow Graphs to Minimize Hardware Implementation [p. 117]
Bouzaida, L.
PDF icon Efficient and Accurate Method for Intra-gate Defect Diagnoses in Nanometer Technology and Volume Data [p. 988]
Bozorgzadeh, E.
PDF icon SEU-Aware Resource Binding for Modular Redundancy Based Designs on FPGAs [p. 1124]
Brama, R.
PDF icon A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard [p. 364]
Braunes, J.
PDF icon Generating the Trace Qualification Configuration for MCDS from a High Level Language [p. 1560]
Braunsteine, C.
PDF icon Increasing the Accuracy of SAT-Based Debugging [p. 1326]
Brayton, R.
PDF icon Speculative Reduction-Based Scalable Redundancy Identification [p. 1674]
Brayton, R.K.
PDF icon Sequential Logic Rectifications with Approximate SPFDs [p. 1698]
Bringmann, O.
PDF icon White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling [p. 513]
Brockmeyer, E.
PDF icon Exploring Parallelizations of Applications for MPSoC Platforms Using MPA [p. 1148]
Brooks, D.
PDF icon An Event-Guided Approach to Reducing Voltage Noise in Processors [p. 160]
Bruce, A.
PDF icon Flow Regulation for On-Chip Communication [p. 578]
Bruneel, K.
PDF icon Automatically Mapping Applications to a Self-Reconfiguring Platform [p. 964]
Burdett, A.
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
Burleson, W.
PDF icon A Monitor Interconnect and Support Subsystem for Multicore Processors [p. 761]

C

Cabodi, G.
PDF icon Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints [p. 1686]
Cai, Y.
PDF icon An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models [p. 1190]
Calazans, N.
PDF icon Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA [p. 634]
Calimera, A.
PDF icon Enabling Concurrent Clock and Power Gating in an Industrial Design Flow [p. 334]
Calvez, A.
PDF icon Statistical Fault Injection: Quantified Error and Confidence [p. 502]
Campagnolo, R.
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
Camurati, P.
PDF icon Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints [p. 1686]
Cao, Y.
PDF icon Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization [p. 328]
Carbognani, F.
PDF icon Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT [p. 646]
Carloni, L.P.
PDF icon A Case Study in Distributed Deployment of Embedded Software for Camera Networks [p. 1006]
Carlson, T.
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
Cartron, M.
PDF icon System-Level Hardware-Based Protection of Memories against Soft-Errors [p. 1222]
Casteres, J.
PDF icon Aircraft Integration Real-Time Simulator Modeling with AADL for Architecture Tradeoffs [p. 346]
Castro-Lopez, R.
PDF icon Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
Catthoor, F.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
PDF icon Finite Precision Processing in Wireless Applications [p. 1230]
PDF icon Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors [p. 1608]
Cervin, A.
PDF icon Integrated Scheduling and Synthesis of Control Applications on Distributed Embedded Systems [p. 57]
Chakrabarty, K.
PDF icon Generation of Compact Test Sets with High Defect Coverage [p. 1130]
PDF icon Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips [p. 1290]
PDF icon Seed Selection in LFSR-Reseeding-Based Test Compression for the Detection of Small-Delay Defects [p. 1488]
Chakraborty, A.
PDF icon Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees [p. 296]
Chambers, B.
PDF icon Faster SAT Solving with Better CNF Generation [p. 1590]
Chandra, A.
PDF icon Scalable Adaptive Scan (SAS) [p. 1476]
Chandra, V.
PDF icon Impact of Voltage Scaling on Nanoscale SRAM Reliability [p. 387]
Chang, K.-H.
PDF icon Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't Cares [p. 582]
Chang, S.-W.
PDF icon pTest: An Adaptive Testing Tool for Concurrent Software on Embedded Multicore Processors [p. 1012]
Chang, Y.-H.
PDF icon A File-System-Aware FTL Design for Flash-Memory Storage Systems [p. 393]
PDF icon A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement [p. 405]
Chang, Y.-W.
PDF icon Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
Charot, F.
PDF icon A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications [p. 1242]
Chatha, K.
PDF icon Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints [p. 1548]
Chatterjee, A.
PDF icon A Novel Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles [p. 1656]
Chatterjee, D.
PDF icon GCS: High-Performance Gate-Level Simulation with GP-GPUs [p. 1332]
Che, J.-J.
PDF icon An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous Multiprocessor Systems [p. 694]
Chen, D.
PDF icon Reconfigurable Circuit Design with Nanomaterials [p. 442]
Chen, F.-W.
PDF icon Performance-Driven Dual-Rail Insertion for Chip-Level Pre-Fabricated Design [p. 308]
Chen, G.
PDF icon A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs [p. 21]
Chen, H.-M.
PDF icon Package Routability-and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design [p. 845]
Chen, N.
PDF icon On Hierarchical Statistical Static Timing Analysis [p. 1320]
Chen, Q.
PDF icon New Simulation Methodology of 3D Surface Roughness Loss for Interconnects Modeling [p. 1184]
Chen, X.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
PDF icon Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization [p. 328]
PDF icon Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing [p. 1530]
Chen, Y.
PDF icon An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures [p. 731]
Cheng, C.-K.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
PDF icon Parallel Transistor Level Full-Chip Circuit Simulation [p. 304]
Cheng, W.-T.
PDF icon Improving Compressed Test Pattern Generation for Multiple Scan Chain Failure Diagnosis [p. 1000]
Cheung, P.
PDF icon Partition-Based Exploration for Reconfigurable JPEG Designs [p. 886]
Chiang, M.-F.
PDF icon Register Placement for High-Performance Circuits [p. 1470]
Chilstedt, S.
PDF icon Reconfigurable Circuit Design with Nanomaterials [p. 442]
Cho, H.
PDF icon KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems [p. 507]
Choi, G.
PDF icon Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO System [p. 870]
Chou, C.-L.
PDF icon User-Centric Design Space Exploration for Heterogeneous Network-on-Chip Platforms [p. 15]
Choudhuri, S.
PDF icon FSAF: File System Aware Flash Translation Layer for NAND Flash Memories [p. 399]
Choudhury, M.R.
PDF icon Masking Timing Errors on Speed-Paths In Logic Circuits [p. 87]
Chrysos, G.
PDF icon Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
Chu, Y.-S.
PDF icon A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement [p. 405]
Chung, S. W.
PDF icon Exploiting Narrow-Width Values for Thermal-Aware Register File Designs [p. 1422]
Ciesielski, M.
PDF icon Optimizing Data Flow Graphs to Minimize Hardware Implementation [p. 117]
Cilardo, A.
PDF icon A New Speculative Addition Architecture Suitable for Two's Complement Operations [p. 664]
Ciriani, V.
PDF icon On Decomposing Boolean Functions via Extended Cofactoring [p. 1464]
Ciuprina, G.
PDF icon On the Efficient Reduction of Complete EM Based Parametric Models [p. 1172]
Clermidy, F.
PDF icon Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC [p. 1564]
Cockburn, B.F.
PDF icon A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development and Verification [p. 45]
Comparetti, M.
PDF icon A Power-Efficient Migration Mechanism for D-NUCA Caches [p. 598]
Concer, N.
PDF icon aEqualized: A Novel Routing Algorithm for the Spidergon Network on Chip [p. 749]
Cong, J.
PDF icon Energy Efficient Multiprocessor Task Scheduling under Input-Dependent Variation [p. 411]
Corporaal, H.
PDF icon Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0 [p. 316]
Cortadella, J.
PDF icon Variable-Latency Design by Function Speculation [p. 1704]
Cosemans, S.
PDF icon A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context [p. 929]
Coskun, A.K.
PDF icon Dynamic Thermal Management in 3D Multicore Architectures [p. 1410]
Costa, J.C.
PDF icon A MILP-Based Approach to Path Sensitization of Embedded Software [p. 1568]
Courcambec, S.
PDF icon SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection [p. 570]
Craninkx, J.
PDF icon A Design Methodology for Fully Reconfigurable Delta-Sigma Data Converters [p. 1379]
Cuelle, J.-P.
PDF icon Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor [p. 184]

D

Dabiri, F.
PDF icon Hardware Aging-Based Software Metering [p. 460]
Dabiri, F.
PDF icon Energy Minimization for Real-Time Systems with Non-Convex and Discrete Operation Modes [p. 1416]
Daneshtalab, M.
PDF icon An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
Danger, J.-L.
PDF icon Successful Attack of an FPGA-Based WDDL DES Cryptoprocessor without Place and Route Constraints [p. 640]
Darbari, A.
PDF icon Selective State Retention Design Using Symbolic Simulation [p. 1644]
Das, A.
PDF icon A Graph Grammar Based Approach to Automated Multi-Objective Analog Circuit Design [p. 700]
Dasgupta, P.
PDF icon A Formal Approach for Specification-Driven AMS Behavioral Model Generation [p. 1512]
Dash, R.
PDF icon Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO System [p. 870]
Davare, A.
PDF icon UMTS MPSoC Design Evaluation Using a System Level Design Framework [p. 478]
de Lamotte, F.
PDF icon A Co-Design Approach for Embedded System Modeling and Code Generation with UML and MARTE [p. 226]
de Langen, P.
PDF icon Limiting the Number of Dirty Cache Lines [p. 670]
De Marinis, M.
PDF icon Shock Immunity Enhancement via Resonance Damping in Gyroscopes for Automotive Applications [p. 1094]
De Micheli, G
PDF icon SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips [p. 9]
PDF icon Physically Clustered Forward Body Biasing for Variability Compensation in Nano-Meter CMOS Design [p. 154]
PDF icon Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis [p. 616]
PDF icon Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis [p. 622]
Declerck, J.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
Dehaene, W.
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
PDF icon A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context [p. 929]
Dejonghe, A.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
Demangel, F.
PDF icon A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications [p. 1242]
Densmore, D.
PDF icon UMTS MPSoC Design Evaluation Using a System Level Design Framework [p. 478]
DeOrio, A.
PDF icon A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs [p. 21]
PDF icon GCS: High-Performance Gate-Level Simulation with GP-GPUs [p. 1332]
Desoli, G.
PDF icon Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip [p. 906]
Di Carlo, S.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
Di Natale, M.
PDF icon Time and Memory Tradeoffs in the Implementation of AUTOSAR Components [p. 864]
PDF icon Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay [p. 1076]
Díaz-Madrid, J.A.
PDF icon Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing [p. 369]
Dick, R.P.
PDF icon Minimization of NBTI Performance Degradation Using Internal Node Control [p. 148]
PDF icon Latency Criticality Aware On-Chip Communication [p. 1052]
PDF icon Energy-Efficient Spatially-Adaptive Clustering and Routing in Wireless Sensor Networks [p. 1267]
Diemer, J.
PDF icon A Link Arbitration Scheme for Quality of Service in a Latency-Optimized Network-on-Chip [p. 574]
Dietrich, M.
PDF icon Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
Diguet, J.-P.
PDF icon A Co-Design Approach for Embedded System Modeling and Code Generation with UML and MARTE [p. 226]
Dilillo, L.
PDF icon A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
Doboli, A.
PDF icon Online Adaptation Policy Design for Grid Sensor Networks with Reconfigurable Embedded Nodes [p. 1273]
Doemer, R.
PDF icon Programming MPSoC Platforms: Road Works Ahead! [p. 1584]
Doménech-Asensi, G.
PDF icon Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing [p. 369]
Dong, C.
PDF icon Reconfigurable Circuit Design with Nanomaterials [p. 442]
Doriol, P.J.
PDF icon EMC-Aware Design on a Microcontroller for Automotive Applications [p. 1208]
Dotto, F.
PDF icon High Data Rate Fully Flexible SDR Modem [p. 1040]
Drabik, N.
PDF icon A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications [p. 1242]
Drechsler, R.
PDF icon Overcoming Limitations of the SystemC Data Introspection [p. 590]
PDF icon Property Analysis and Design Understanding [p. 1246]
PDF icon Debugging of Toffoli Networks [p. 1284]
PDF icon Increasing the Accuracy of SAT-Based Debugging [p. 1326]
Drissi, M.
PDF icon Enhancing Correlation Electro-Magnetic Attack Using Planar Near-Field Cartography [p. 628]
D'Silva, V.
PDF icon Fixed Points for Multi-Cycle Path Detection [p. 1710]
Dubrova, E.
PDF icon How To Speed-Up Your NLFSR-Based Stream Cipher [p. 878]
Dudnik, P.
PDF icon Architectural Support for Low Overhead Detection of Memory Violations [p. 652]
Dueck, G.W.
PDF icon Debugging of Toffoli Networks [p. 1284]
Dutt, N.
PDF icon TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
Dutta, H.
PDF icon Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms [p. 135]
Dworak, J.
PDF icon Detecting Errors Using Multi-Cycle Invariance Information [p. 791]

E

Eberle, W.
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
Ebi, T.
PDF icon Configurable Links for Runtime Adaptive On-Chip Communication [p. 256]
Ebrahimi, M.
PDF icon An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
Eichler, U.
PDF icon Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
El Mrabti, A.
PDF icon Extending IP-XACT to Support an MDE Based Approach For SoC Design [p. 586]
Eles, P.
PDF icon Integrated Scheduling and Synthesis of Control Applications on Distributed Embedded Systems [p. 57]
PDF icon Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors [p. 682]
Eltawil, A.
PDF icon TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
PDF icon Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling [p. 911]
Endoh, T.
PDF icon MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
Eom, Y.I.
PDF icon KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems [p. 507]
Erdogan, A.T.
PDF icon An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures [p. 33]
Ernst, R.
PDF icon Mapping of a Film Grain Removal Algorithm to a Heterogeneous Reconfigurable Architecture [p. 27]
PDF icon Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources [p. 524]
PDF icon A Link Arbitration Scheme for Quality of Service in a Latency-Optimized Network-on-Chip [p. 574]
PDF icon Learning Early-Stage Platform Dimensioning from Late-Stage Timing Verification [p. 851]
Evain, S.
PDF icon System-Level Hardware-Based Protection of Memories against Soft-Errors [p. 1222]
Eydoux, J.
PDF icon Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor [p. 184]

F

Facchini, M.
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
PDF icon A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context [p. 929]
Fahmy, S.F.
PDF icon On Bounding Response Times under Software Transactional Memory in Distributed Multiprocessor Real-Time Systems [p. 688]
Fan, X.
PDF icon Energy-Efficient Spatially-Adaptive Clustering and Routing in Wireless Sensor Networks [p. 1267]
Fanucci, L.
PDF icon Shock Immunity Enhancement via Resonance Damping in Gyroscopes for Automotive Applications [p. 1094]
Fard, S. F.
PDF icon A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development and Verification [p. 45]
Fasthuber, R.
PDF icon Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors [p. 1608]
Fau, N.
PDF icon A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications [p. 1242]
Fedorov, A.
PDF icon Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
Fei, Y.
PDF icon Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT [p. 1302]
Felber, N.
PDF icon Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT [p. 646]
Feldmann, P.
PDF icon Efficient Compression and Handling of Current Source Model Library Waveforms [p. 1178]
Feng, S.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Fernandez Villena, J.
PDF icon On the Efficient Reduction of Complete EM Based Parametric Models [p. 1172]
Fernandez, F.V.
PDF icon Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
Ferrari, A.
PDF icon Time and Memory Tradeoffs in the Implementation of AUTOSAR Components [p. 864]
Fettweis, G.
PDF icon Dimensioning Heterogeneous MPSoCs via Parallelism Analysis [p. 554]
Fey, G.
PDF icon Increasing the Accuracy of SAT-Based Debugging [p. 1326]
Fichtner, W.
PDF icon Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT [p. 646]
Fick, D.
PDF icon A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs [p. 21]
Fiorin, L.
PDF icon MPSoCs Run-Time Monitoring through Networks-on-Chip [p. 558]
Flamand, E.
PDF icon Strategic Directions towards Multicore Application Specific Computing [p. 1266]
Flynn, A.
PDF icon Bitstream Relocation with Local Clock Domains for Partially Reconfigurable FPGAs [p. 300]
Foglia, P.
PDF icon A Power-Efficient Migration Mechanism for D-NUCA Caches [p. 598]
Fornaciari, W.
PDF icon Predictive Models for Multimedia Applications Power Consumption Based on Use-Case and OS Level Analysis [p. 1446]
Forzan, C.
PDF icon EMC-Aware Design on a Microcontroller for Automotive Applications [p. 1208]
Fossati, L.
PDF icon A Real-Time Application Design Methodology for MPSoCs [p. 767]
Fourmique, A.
PDF icon Co-Simulation Based Platform for Wireless Protocols Design Explorations [p. 874]
Frehse, S.
PDF icon Debugging of Toffoli Networks [p. 1284]
Fujita, S.
PDF icon Nano-electronics Challenge - Chip Designers Meet Real Nano-Electronics in 2010s? [p. 431]
Fummi, F.
PDF icon Functional Qualification of TLM Verification [p. 190]
PDF icon Networked Embedded System Applications Design Driven by an Middleware Environment [p. 1024]
PDF icon Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches [p. 1500]
PDF icon Flexible Energy-Aware Simulation of Heterogeneous Wireless Sensor Networks [p. 1638]
Fytraki, S.
PDF icon ReSiM, A Trace-Driven, Reconfigurable ILP Processor Simulator [p. 536]

G

Gabrielli, G.
PDF icon A Power-Efficient Migration Mechanism for D-NUCA Caches [p. 598]
Gai, P.
PDF icon Time and Memory Tradeoffs in the Implementation of AUTOSAR Components [p. 864]
Galanakis, C.
PDF icon Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
Galuzzi, C.
PDF icon Algorithms for the Automatic Extension of an Instruction-Set [p. 548]
Ganesan, G.
PDF icon Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees [p. 296]
Ganzerli, M.
PDF icon A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard [p. 364]
Gao, W.
PDF icon DPR in High Energy Physics [p. 39]
Garcia, L.
PDF icon Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints [p. 1686]
Garcia, S.
PDF icon Making DNA Self-Assembly Error-Proof: Attaining Small Growth Error Rates through Embedded Information Redundancy [p. 898]
Garg, S.
PDF icon System-Level Process Variability Analysis and Mitigation for 3D MPSoCs [p. 604]
Garnier, P.
PDF icon Trends and Challenges in Wireless Application Processors [p. 603]
Gaydadjiev, G.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
Genser, A.
PDF icon A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing [p. 1614]
Gentile, G.
PDF icon Time and Memory Tradeoffs in the Implementation of AUTOSAR Components [p. 864]
Genz, C.
PDF icon Overcoming Limitations of the SystemC Data Introspection [p. 590]
George, A.D.
PDF icon Bitstream Relocation with Local Clock Domains for Partially Reconfigurable FPGAs [p. 300]
Gerlach, J.
PDF icon An Automated Flow For Integrating Hardware IP into the Automotive Systems Engineering Process [p. 1196]
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Ghasemzadeh, H.
PDF icon Communication Minimization for In-Network Processing in Body Sensor Networks: A Buffer Assignment Technique [p. 358]
Gherman, V.
PDF icon System-Level Hardware-Based Protection of Memories against Soft-Errors [p. 1222]
Ghose, S.
PDF icon Architectural Support for Low Overhead Detection of Memory Violations [p. 652]
Gielen, G.
PDF icon Massively Multi-Topology Sizing of Analog Integrated Circuits [p. 706]
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
PDF icon Efficient Reliability Simulation of Analog ICs Including Variability and Time-Varying Stress [p. 1238]
PDF icon A Design Methodology for Fully Reconfigurable Delta-Sigma Data Converters [p. 1379]
Gilabert, F.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
Gilberti, M.
PDF icon Online Adaptation Policy Design for Grid Sensor Networks with Reconfigurable Embedded Nodes [p. 1273]
Gilgeous, L.
PDF icon Architectural Support for Low Overhead Detection of Memory Violations [p. 652]
Girard, P.
PDF icon A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
Girodias, B.
PDF icon Co-Simulation Based Platform for Wireless Protocols Design Explorations [p. 874]
Giusto, P.
PDF icon Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay [p. 1076]
Givargis, A.
PDF icon FSAF: File System Aware Flash Translation Layer for NAND Flash Memories [p. 399]
Glas, B.
PDF icon Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems [p. 178]
Glaser, D.
PDF icon A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow [p. 797]
Glass, M.
PDF icon Incorporating Graceful Degradation into Embedded System Design [p. 320]
PDF icon Combined System Synthesis and Communication Architecture Exploration for MPSoCs [p. 472]
Glesner, M.
PDF icon A Flexible Floating-Point Wavelet Transform and Wavelet Packet Processor [p. 1314]
Glöckel, V.
PDF icon Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
Gnudi, A.
PDF icon A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard [p. 364]
Goergen, R.
PDF icon An Automated Flow For Integrating Hardware IP into the Automotive Systems Engineering Process [p. 1196]
Gogniat, G.
PDF icon A Co-Design Approach for Embedded System Modeling and Code Generation with UML and MARTE [p. 226]
Golshan, S.
PDF icon SEU-Aware Resource Binding for Modular Redundancy Based Designs on FPGAs [p. 1124]
Gomez, C.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
Gomez, M.E.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
Gomez-Prado, D.
PDF icon Optimizing Data Flow Graphs to Minimize Hardware Implementation [p. 117]
Goossens, K.
PDF icon A High-Level Debug Environment for Communication-Centric Debug [p. 202]
PDF icon aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services [p. 250]
Gopalakrishnan, S.
PDF icon Algebraic Techniques to Enhance Common Sub-Expression Elimination for Polynomial Synthesis [p. 1452]
Gordon-Ross, A.
PDF icon SCORES: A Scalable and Parametric Streams-Based Communication Architecture for Modular Reconfigurable Systems [p. 268]
PDF icon Bitstream Relocation with Local Clock Domains for Partially Reconfigurable FPGAs [p. 300]
Gouin, V.
PDF icon A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
Goyal, A.
PDF icon A Novel Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles [p. 1656]
Grabowski, D.
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Graeb, H.
PDF icon Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Graziosi, G.
PDF icon EMC-Aware Design on a Microcontroller for Automotive Applications [p. 1208]
Griessnig, G.
PDF icon Fault Insertion Testing of a Novel CPLD-Based Fail-Safe System [p. 214]
Grimm, C.
PDF icon Analogue Mixed Signal Simulation Using Spice and SystemC [p. 284]
Grosse, D.
PDF icon Property Analysis and Design Understanding [p. 1246]
PDF icon Debugging of Toffoli Networks [p. 1284]
Gu, H.
PDF icon A Low-Power Fat Tree-Based Optical Network-on-Chip for Multiprocessor System-on-Chip [p. 3]
Guan, X.
PDF icon Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT [p. 1302]
Guillemin, P.
PDF icon SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection [p. 570]
Guilley, S.
PDF icon Successful Attack of an FPGA-Based WDDL DES Cryptoprocessor without Place and Route Constraints [p. 640]
Guillot, J.
PDF icon Optimizing Data Flow Graphs to Minimize Hardware Implementation [p. 117]
Guntoro, A.
PDF icon A Flexible Floating-Point Wavelet Transform and Wavelet Packet Processor [p. 1314]
Guo, R.
PDF icon Improving Compressed Test Pattern Generation for Multiple Scan Chain Failure Diagnosis [p. 1000]
Guo, X.
PDF icon Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage [p. 454]
Gupta, A.
PDF icon TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
Gupta, M.S
PDF icon An Event-Guided Approach to Reducing Voltage Noise in Processors [p. 160]
Gururaj, K.
PDF icon Energy Efficient Multiprocessor Task Scheduling under Input-Dependent Variation [p. 411]

H

Ha, S.
PDF icon Pipelined Data Parallel Task Mapping/Scheduling Technique for MPSoC [p. 69]
PDF icon On-Chip Communication Architecture Exploration for Processor-Pool-Based MPSoC [p. 466]
PDF icon Programming MPSoC Platforms: Road Works Ahead! [p. 1584]
Haase, V.
PDF icon Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints [p. 1548]
Hagemeyer, J.
PDF icon Design Optimizations to Improve Placeability of Partial Reconfiguration Modules [p. 976]
Haik, G.
PDF icon Mode-Based Reconfiguration of Critical Software Component Architectures [p. 1160]
Hamalainen, T.D.
PDF icon Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA [p. 244]
Hampton, M.
PDF icon Functional Qualification of TLM Verification [p. 190]
Hamzaoglu, I.
PDF icon A High Performance Reconfigurable Motion Estimation Hardware Architecture [p. 882]
Han, W.
PDF icon An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures [p. 33]
Han, Y.
PDF icon A Unified Online Fault Detection Scheme Via Checking of Stability Violation [p. 496]
Hannig, F.
PDF icon Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms [p. 135]
Hannikainen, M.
PDF icon Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA [p. 244]
Hansson, A.
PDF icon aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services [p. 250]
Hanumaiah, V.
PDF icon Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints [p. 1548]
Hanyu, T.
PDF icon MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
Hao, K.
PDF icon Componentizing Hardware/Software Interface Design [p. 232]
Harrod, P.
PDF icon Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing [p. 1349]
Hartmann, P.A.
PDF icon OSSS+R: A Framework for Application Level Modelling and Synthesis of Reconfigurable Systems [p. 970]
Hatami, S.
PDF icon Efficient Compression and Handling of Current Source Model Library Waveforms [p. 1178]
Haubelt, C.
PDF icon Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms [p. 135]
PDF icon Incorporating Graceful Degradation into Embedded System Design [p. 320]
PDF icon Combined System Synthesis and Communication Architecture Exploration for MPSoCs [p. 472]
Hauer, H.
PDF icon Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing [p. 369]
Hayakawa, J.
PDF icon MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
Hayes, J.P.
PDF icon Contactless Testing: Possibility or Pipe-Dream? [p. 676]
He, N.
PDF icon An Efficient Path-Oriented Bitvector Encoding Width Computation Algorithm for Bit-Precise Verification [p. 1602]
Hedrich, L.
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Heinen, S.
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Held, S.
PDF icon Gate Sizing for Large Cell-Based Designs [p. 827]
Helmreich, K.
PDF icon A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow [p. 797]
Henkel, J.
PDF icon Configurable Links for Runtime Adaptive On-Chip Communication [p. 256]
PDF icon Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors [p. 958]
PDF icon A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC Video Codec [p. 1434]
PDF icon Efficient Constant-Time Entropy Decoding for H.264 [p. 1440]
Henriksson, T.
PDF icon Flow Regulation for On-Chip Communication [p. 578]
PDF icon Heterogeneous Multi-Core Platform for Consumer Multimedia Applications [p. 1254]
Henzen, L.
PDF icon Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT [p. 646]
Herrholz, A.
PDF icon OSSS+R: A Framework for Application Level Modelling and Synthesis of Reconfigurable Systems [p. 970]
Hoe, J.C.
PDF icon Automatic Generation of Streaming Datapaths for Arbitrary Fixed Permutations [p. 1118]
Holcomb, D.
PDF icon Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits [p. 785]
Hollis, S.
PDF icon Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems [p. 917]
Holloway, G.
PDF icon An Event-Guided Approach to Reducing Voltage Noise in Processors [p. 160]
Holst, S.
PDF icon A Diagnosis Algorithm for Extreme Space Compaction [p. 1355]
Homayoun, H.
PDF icon Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling [p. 911]
Hong, S.
PDF icon Process Variation Aware Thread Mapping for Chip Multiprocessors [p. 821]
Hong, X.
PDF icon An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models [p. 1190]
Hsiao, M.S.
PDF icon An Efficient Path-Oriented Bitvector Encoding Width Computation Algorithm for Bit-Precise Verification [p. 1602]
Hsieh, A.-C.
PDF icon Thermal-Aware Memory Mapping in 3D Designs [p. 1361]
Hsieh, B.-S.
PDF icon Enhanced Design of Filterless Class-D Audio Amplifier [p. 1397]
Hsieh, J.-W.
PDF icon A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement [p. 405]
Hsieh, K.-Y.
PDF icon pTest: An Adaptive Testing Tool for Concurrent Software on Embedded Multicore Processors [p. 1012]
Hsieh W.-W.
PDF icon A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test [p. 1234]
Hu, J.
PDF icon Exploiting Narrow-Width Values for Thermal-Aware Register File Designs [p. 1422]
Hu, K.
PDF icon Towards a Formal Semantics for the AADL Behavior Annex [p. 1166]
Hu, X.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
Huang, C.
PDF icon Defect-Aware Logic Mapping for Nanowire-Based Programmable Logic Arrays via Satisfiability [p. 1279]
Huang, G.
PDF icon Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
Huang, L.
PDF icon Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms [p. 51]
PDF icon Test Architecture Design and Optimization for Three-Dimensional SoCs [p. 220]
Huang, S.-Y.
PDF icon QC-Fill: An X-Fill Method for Quick-and-Cool Scan Test [p. 1142]
Hulzink, J.
PDF icon A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing [p. 1614]
Huss, S.A.
PDF icon SC-DEVS: An Efficient Systemc Extension for the DEVS Model of Computation [p. 1518]
Huynh, H.P.
PDF icon Runtime Reconfiguration of Custom Instructions for Real-Time Embedded Systems [p. 1536]
Hwang, T.
PDF icon A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test [p. 1234]
PDF icon Thermal-Aware Memory Mapping in 3D Designs [p. 1361]

I

Iamundo, S.
PDF icon aEqualized: A Novel Routing Algorithm for the Spidergon Network on Chip [p. 749]
Iannacci, J.
PDF icon A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard [p. 364]
Ikeda, S.
PDF icon MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
Imhof, M.E.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
Ioan, D.
PDF icon On the Efficient Reduction of Complete EM Based Parametric Models [p. 1172]
Iqbal, N.
PDF icon Efficient Constant-Time Entropy Decoding for H.264 [p. 1440]
Izosimov, V.
PDF icon Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors [p. 682]

J

Jacoby, R.
PDF icon Solver Technology for System-level to RTL Equivalence Checking [p. 196]
Jafari, R.
PDF icon Communication Minimization for In-Network Processing in Body Sensor Networks: A Buffer Assignment Technique [p. 358]
Jafri, A.R.
PDF icon ASIP-Based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications [p. 1620]
Jahanian, A.
PDF icon Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network [p. 833]
Jain, H.
PDF icon Solver Technology for System-level to RTL Equivalence Checking [p. 196]
Jain, N.
PDF icon Communication Minimization for In-Network Processing in Body Sensor Networks: A Buffer Assignment Technique [p. 358]
Jantsch, A.
PDF icon Flow Regulation for On-Chip Communication [p. 578]
PDF icon Priority Based Forced Requeue to Reduce Worst Case Latencies for Bursty Traffic [p. 1070]
PDF icon Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures [p. 1506]
Jara-Berrocal, A.
PDF icon SCORES: A Scalable and Parametric Streams-Based Communication Architecture for Modular Reconfigurable Systems [p. 268]
Jemai, A.
PDF icon High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation [p. 940]
Jensen, E.D.
PDF icon On Bounding Response Times under Software Transactional Memory in Distributed Multiprocessor Real-Time Systems [p. 688]
Jentschel, H.-J.
PDF icon An Approach to Linear Model-Based Testing and Diagnosis for Nonlinear Cascaded Mixed-Signal Systems [p. 1662]
Jeong, S.-W.
PDF icon In-Network Reorder Buffer to Improve Overall NoC Performance While Resolving the In-Order Requirement Problem [p. 1058]
Jersak, M.
PDF icon Learning Early-Stage Platform Dimensioning from Late-Stage Timing Verification [p. 851]
Jezequel, M.
PDF icon ASIP-Based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications [p. 1620]
Jha, N.K.
PDF icon An Architecture for Secure Software Defined Radio [p. 448]
Jiang, L.
PDF icon Test Architecture Design and Optimization for Three-Dimensional SoCs [p. 220]
Jiaxin, L.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Jone, W.-B.
PDF icon Selective Light Vth Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power Reduction [p. 594]
Joo, Y.-P.
PDF icon On-Chip Communication Architecture Exploration for Processor-Pool-Based MPSoC [p. 466]
Joshi, Y.
PDF icon Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
Juurlink, B.
PDF icon Limiting the Number of Dirty Cache Lines [p. 670]

K

Kabutz, M.
PDF icon A Novel LDPC Decoder for DVB-S2 IP [p. 1308]
Kahng, A.B.
PDF icon ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration [p. 423]
Kalla, P.
PDF icon Algebraic Techniques to Enhance Common Sub-Expression Elimination for Polynomial Synthesis [p. 1452]
Kalligeros, E.
PDF icon LFSR-Based Test-Data Compression with Self-Stoppable Seeds [p. 1482]
Kandemir, M.
PDF icon Adaptive Prefetching for Shared Cache Based Chip Multiprocessors [p. 773]
PDF icon Process Variation Aware Thread Mapping for Chip Multiprocessors [p. 821]
PDF icon Using Dynamic Compilation for Continuing Execution under Reduced Memory Availability [p. 1373]
Kang, J.
PDF icon Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing [p. 1530]
Kanzawa, Y.
PDF icon Scalable Adaptive Scan (SAS) [p. 1476]
Kapur, R.
PDF icon Scalable Adaptive Scan (SAS) [p. 1476]
Karakolah, D.
PDF icon ASIP-Based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications [p. 1620]
Kasperski, F.
PDF icon High Data Rate Fully Flexible SDR Modem [p. 1040]
Kavousianos, X.
PDF icon Generation of Compact Test Sets with High Defect Coverage [p. 1130]
PDF icon LFSR-Based Test-Data Compression with Self-Stoppable Seeds [p. 1482]
Kazmierski, T.J.
PDF icon An Automated Design Flow for Vibration-Based Energy Harvester Systems [p. 1391]
Ke, L.
PDF icon Improved Performance and Variation Modelling for Hierarchical-Based Optimisation of Analogue Integrated Circuits [p. 712]
Ke, Y.
PDF icon A Design Methodology for Fully Reconfigurable Delta-Sigma Data Converters [p. 1379]
Kebschull, U.
PDF icon DPR in High Energy Physics [p. 39]
Keinert, J.
PDF icon Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms [p. 135]
Kgil, T.
PDF icon Using Non-Volatile Memory to Save Energy in Servers [p. 743]
Khajeh, A.
PDF icon TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
Khan, O.
PDF icon A Self-Adaptive System Architecture to Address Transistor Aging [p. 81]
PDF icon Improving Yield and Reliability of Chip Multiprocessors [p. 490]
PDF icon Hardware/Software Co-design Architecture for Thermal Management of Chip Multiprocessors [p. 952]
Khazaka, R.
PDF icon Computation of IP3 Using Single-Tone Moments Analysis [p. 718]
Khouri, K.
PDF icon TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
Khursheed, S.
PDF icon Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing [p. 1349]
Kienhuis, B.
PDF icon Automated Synthesis of Streaming C Applications to Process Networks In Hardware [p. 890]
Kienle, F.
PDF icon A Novel LDPC Decoder for DVB-S2 IP [p. 1308]
Kim, E.J.
PDF icon Temperature-Aware Scheduler Based on Thermal Behavior Grouping in Multicore Systems [p. 946]
Kim, J.
PDF icon Program Phase and Runtime Distribution-Aware Online DVFS for Combined Vdd/Vbb Scaling [p. 417]
Kim, S.
PDF icon On-Chip Communication Architecture Exploration for Processor-Pool-Based MPSoC [p. 466]
Kim, Y.-J.
PDF icon Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
Kinsman, A.B.
PDF icon Finite Precision Bit-Width Allocation Using SAT-Modulo Theory [p. 1106]
Kinzelbach, H.
PDF icon Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
Kirchner, T.
PDF icon Analogue Mixed Signal Simulation Using Spice and SystemC [p. 284]
Kishinevsky, M.
PDF icon Variable-Latency Design by Function Speculation [p. 1704]
Kitayama, K.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Kizu, T.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Kochte, M.A.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
Kodaka, T.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Koelbl, A.
PDF icon Solver Technology for System-level to RTL Equivalence Checking [p. 196]
Koenig, F.
PDF icon Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems [p. 519]
Koester, M.
PDF icon Design Optimizations to Improve Placeability of Partial Reconfiguration Modules [p. 976]
Kollig, P.
PDF icon Heterogeneous Multi-Core Platform for Consumer Multimedia Applications [p. 1254]
Kollman, S.
PDF icon Improved Worst-Case Response-Time Calculations by Upper-Bound Conditions [p. 105]
Korhonen, E.
PDF icon A Loopback-Based INL Test Method for D/A and A/D Converters Employing a Stimulus Identification Technique [p. 1650]
Koskinen, T.
PDF icon Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA [p. 244]
Kostamovaara, J.
PDF icon A Loopback-Based INL Test Method for D/A and A/D Converters Employing a Stimulus Identification Technique [p. 1650]
Koutsoupia, M.
PDF icon LFSR-Based Test-Data Compression with Self-Stoppable Seeds [p. 1482]
Kravets, V.
PDF icon Sequential Logic Synthesis Using Symbolic Bi-Decompsition [p. 1458]
Kroening, D.
PDF icon Strengthening Properties Using on Refinement [p. 1692]
PDF icon Fixed Points for Multi-Cycle Path Detection [p. 1710]
Kropf, T.
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Kuehne, U.
PDF icon Property Analysis and Design Understanding [p. 1246]
PDF icon Increasing the Accuracy of SAT-Based Debugging [p. 1326]
Kugel, A.
PDF icon DPR in High Energy Physics [p. 39]
Kukner, H.
PDF icon A High Performance Reconfigurable Motion Estimation Hardware Architecture [p. 882]
Kumar, R.
PDF icon Distributed Peak Power Management for Many-Core Architectures [p. 1556]
Kundu, S.
PDF icon A Self-Adaptive System Architecture to Address Transistor Aging [p. 81]
PDF icon A Study on Placement of Post Silicon Clock Tuning Buffers for Mitigating Impact of Process Variation [p. 292]
PDF icon On Linewidth-Based Yield Analysis for Nanometer Lithography [p. 381]
PDF icon Improving Yield and Reliability of Chip Multiprocessors [p. 490]
PDF icon Hardware/Software Co-design Architecture for Thermal Management of Chip Multiprocessors [p. 952]
Kuo, T.-W.
PDF icon A File-System-Aware FTL Design for Flash-Memory Storage Systems [p. 393]
PDF icon A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement [p. 405]
PDF icon An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous Multiprocessor Systems [p. 694]
Kurdahi, F.
PDF icon TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
PDF icon Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling [p. 911]
Kuusilinna, K.
PDF icon A Case for Multi-Channel Memories in Video Recording [p. 934]
Kwon, W.-C.
PDF icon In-Network Reorder Buffer to Improve Overall NoC Performance While Resolving the In-Order Requirement Problem [p. 1058]
Kyung, C.-M.
PDF icon Program Phase and Runtime Distribution-Aware Online DVFS for Combined Vdd/Vbb Scaling [p. 417]

L

Ladhar, A.
PDF icon Efficient and Accurate Method for Intra-gate Defect Diagnoses in Nanometer Technology and Volume Data [p. 988]
Larcher, L.
PDF icon A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard [p. 364]
Larsson, E.
PDF icon Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips [p. 484]
Leblebici, J.
PDF icon Dynamic Thermal Management in 3D Multicore Architectures [p. 1410]
Lee, D.Y.
PDF icon Contactless Testing: Possibility or Pipe-Dream? [p. 676]
Lee, J.
PDF icon FSAF: File System Aware Flash Translation Layer for NAND Flash Memories [p. 399]
PDF icon Static Analysis to Mitigate Soft Errors in Register Files [p. 1367]
Lee, J.K.
PDF icon pTest: An Adaptive Testing Tool for Concurrent Software on Embedded Multicore Processors [p. 1012]
Lee, Y.-J.
PDF icon Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
Lenzi, F.
PDF icon Distributed Sensor For Steering Wheel Grip Force Measurement In Driver Fatigue Detection [p. 894]
Leonardi, F.
PDF icon A Case Study in Distributed Deployment of Embedded Software for Camera Networks [p. 1006]
Letombe, F.
PDF icon Functional Qualification of TLM Verification [p. 190]
Lettnin, D.
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Leupers, R.
PDF icon Programming MPSoC Platforms: Road Works Ahead! [p. 1584]
Leveugle, R.
PDF icon Statistical Fault Injection: Quantified Error and Confidence [p. 502]
Li, B.
PDF icon ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration [p. 423]
PDF icon On Hierarchical Statistical Static Timing Analysis [p. 1320]
Li, C.
PDF icon An Architecture for Secure Software Defined Radio [p. 448]
Li, H.
PDF icon An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures [p. 731]
Li, J.
PDF icon Power and Performance of Read-Write Aware Hybrid Caches with Non-volatile Memories [p. 737]
Li, M.
PDF icon Finite Precision Processing in Wireless Applications [p. 1230]
PDF icon Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors [p. 1608]
Li, W.
PDF icon Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits [p. 785]
PDF icon Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay [p. 1076]
Li, X.
PDF icon A Unified Online Fault Detection Scheme Via Checking of Stability Violation [p. 496]
Li, Z.
PDF icon Latency Criticality Aware On-Chip Communication [p. 1052]
Licheng, X.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Lillie, A.
PDF icon Implementation of a Reduced-Lattice MIMO Detector for OFDM Systems [p. 1626]
Lim, S.K.
PDF icon Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
PDF icon Decoupling Capacitor Planning with Analytical Delay Model on RLC Power Grid [p. 839]
Lima Kastensmidt, F.
PDF icon A Study of the Single Event Effects Impact on Functional Mapping within Flash-Based FPGAs [p. 1226]
Limberg, T.
PDF icon Dimensioning Heterogeneous MPSoCs via Parallelism Analysis [p. 554]
Lin, C.-C.
PDF icon Rewiring Using IRredundancy Removal and Addition [p. 324]
Lin, C.W.
PDF icon Enhanced Design of Filterless Class-D Audio Amplifier [p. 1397]
Lin, H.
PDF icon Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT [p. 1302]
Lin, I.-S.
PDF icon A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test [p. 1234]
Lin, P.-H.
PDF icon Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
Lin, S.
PDF icon Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing [p. 1530]
Lin, Y.C.
PDF icon Enhanced Design of Filterless Class-D Audio Amplifier [p. 1397]
Liu, C.-N. J.
PDF icon Package Routability-and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design [p. 845]
Liu, X.
PDF icon Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation [p. 1338]
PDF icon A Generic Framework for Scan Capture Power Reduction in Fixed-Length Symbol-Based Test Compression Environment [p. 1494]
Liu, Y.
PDF icon Energy-Efficient Spatially-Adaptive Clustering and Routing in Wireless Sensor Networks [p. 1267]
Liu, Y.-Y.
PDF icon Performance-Driven Dual-Rail Insertion for Chip-Level Pre-Fabricated Design [p. 308]
Loi, I.
PDF icon Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces [p. 262]
Lombardi, M.
PDF icon Robust Non-Preemptive Hard Real-Time Scheduling for Clustered Multicore Platforms [p. 803]
Lomne, V.
PDF icon Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA [p. 634]
Long, H.
PDF icon Energy-Efficient Spatially-Adaptive Clustering and Routing in Wireless Sensor Networks [p. 1267]
Lopez, P.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
Los Santos Aransay , A.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Lu, C.-H.
PDF icon Package Routability-and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design [p. 845]
Lu, P.
PDF icon A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow [p. 797]
Lu, Z.
PDF icon Flow Regulation for On-Chip Communication [p. 578]
Ludovici, D.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
Luk, W.
PDF icon Partition-Based Exploration for Reconfigurable JPEG Designs [p. 886]
PDF icon Design Optimizations to Improve Placeability of Partial Reconfiguration Modules [p. 976]
Lukasiewycz, M.
PDF icon Incorporating Graceful Degradation into Embedded System Design [p. 320]
PDF icon Combined System Synthesis and Communication Architecture Exploration for MPSoCs [p. 472]

M

Ma, D.
PDF icon Towards a Formal Semantics for the AADL Behavior Annex [p. 1166]
Macii, A.
PDF icon Enabling Concurrent Clock and Power Gating in an Industrial Design Flow [p. 334]
Macii, E.
PDF icon Physically Clustered Forward Body Biasing for Variability Compensation in Nano-Meter CMOS Design [p. 154]
PDF icon Enabling Concurrent Clock and Power Gating in an Industrial Design Flow [p. 334]
Madduri, S.
PDF icon A Monitor Interconnect and Support Subsystem for Multicore Processors [p. 761]
Mader, R.
PDF icon Fault Insertion Testing of a Novel CPLD-Based Fail-Safe System [p. 214]
Madlener, F.
PDF icon SC-DEVS: An Efficient Systemc Extension for the DEVS Model of Computation [p. 1518]
Maenner, R.
PDF icon DPR in High Energy Physics [p. 39]
Maistri, P.
PDF icon Statistical Fault Injection: Quantified Error and Confidence [p. 502]
Makhzan, M.A.
PDF icon Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling [p. 911]
Makris, Y.
PDF icon Enrichment of Limited Training Sets in Machine-Learning-Based Analog/RF Test [p. 1668]
Mamagkakis, S.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
Mangalagiri, P.
PDF icon Exploiting Clock Skew Scheduling for FPGA [p. 1524]
Manolios, P.
PDF icon Faster SAT Solving with Better CNF Generation [p. 1590]
Marchal, P.
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
PDF icon A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context [p. 929]
Marchetti, E.
PDF icon Shock Immunity Enhancement via Resonance Damping in Gyroscopes for Automotive Applications [p. 1094]
Marculescu, D.
PDF icon Joint Logic Restructuring and Pin Reordering against NBTI-Induced Performance Degradation [p. 75]
PDF icon System-Level Process Variability Analysis and Mitigation for 3D MPSoCs [p. 604]
Marculescu, R.
PDF icon User-Centric Design Space Exploration for Heterogeneous Network-on-Chip Platforms [p. 15]
Margull, U.
PDF icon Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems [p. 519]
Maricau, E.
PDF icon Efficient Reliability Simulation of Analog ICs Including Variability and Time-Varying Stress [p. 1238]
Marinissen, E.J.
PDF icon Contactless Testing: Possibility or Pipe-Dream? [p. 676]
Markov, I.L.
PDF icon Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't Cares [p. 582]
Marongiu, A.
PDF icon Efficient OpenMP Support and Extensions for MPSoCs with Explicitly Managed Memory Hierarchy [p. 809]
Martínez Madrid, N.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Masmoudi, M.
PDF icon Efficient and Accurate Method for Intra-gate Defect Diagnoses in Nanometer Technology and Volume Data [p. 988]
Mathew, J.
PDF icon Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems [p. 917]
Mathieu, Y.
PDF icon Successful Attack of an FPGA-Based WDDL DES Cryptoprocessor without Place and Route Constraints [p. 640]
Matsumoto, N.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Matsunaga, S.
PDF icon MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
Mattes, H.
PDF icon An Approach to Linear Model-Based Testing and Diagnosis for Nonlinear Cascaded Mixed-Signal Systems [p. 1662]
Maurine, P.
PDF icon Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA [p. 634]
Mazumder, P.
PDF icon An Accurate Interconnect Thermal Model Using Equivalent Transmission Line Circuit [p. 280]
Mazzini, S.
PDF icon An MDE Methodology for the Development of High-Integrity Real-Time Systems [p. 1154]
McConnaghy, T.
PDF icon Massively Multi-Topology Sizing of Analog Integrated Circuits [p. 706]
Mecheri, A.S.
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
Medardoni, S.
PDF icon Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
Meeuws, R.
PDF icon Algorithms for the Automatic Extension of an Instruction-Set [p. 548]
Meier, N.
PDF icon DPR in High Energy Physics [p. 39]
Meinhardt, C.
PDF icon A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable Chips [p. 352]
Mendler, M.
PDF icon WCRT Algebra and Interfaces for Esterel-Style Synchronous Processing [p. 93]
Menuet, P.
PDF icon Scalable Compile-Time Scheduler for Multi-Core Architectures [p. 1552]
Milano, M.
PDF icon Robust Non-Preemptive Hard Real-Time Scheduling for Clustered Multicore Platforms [p. 803]
Milder, P.A.
PDF icon Automatic Generation of Streaming Datapaths for Arbitrary Fixed Permutations [p. 1118]
Milford, D.
PDF icon Implementation of a Reduced-Lattice MIMO Detector for OFDM Systems [p. 1626]
Millberg, M.
PDF icon Flow Regulation for On-Chip Communication [p. 578]
PDF icon Priority Based Forced Requeue to Reduce Worst Case Latencies for Bursty Traffic [p. 1070]
Mir, S.
PDF icon Enrichment of Limited Training Sets in Machine-Learning-Based Analog/RF Test [p. 1668]
Mirsaeedi, M.
PDF icon Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network [p. 833]
Mishchenko, A.
PDF icon Sequential Logic Synthesis Using Symbolic Bi-Decompsition [p. 1458]
PDF icon Speculative Reduction-Based Scalable Redundancy Identification [p. 1674]
Mishra, B.
PDF icon Variation Resilient Adaptive Controller for Subthreshold Circuits [p. 142]
Mitra, S.
PDF icon Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect Ttransistors [p. 436]
Mitra, T.
PDF icon Runtime Reconfiguration of Custom Instructions for Real-Time Embedded Systems [p. 1536]
Miura, K.
PDF icon MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
Modarressi, M.
PDF icon A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM [p. 566]
Mohammadi, S.
PDF icon An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
MohammadZadeh, N.M.
PDF icon Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network [p. 833]
Mohanram, K.
PDF icon Masking Timing Errors on Speed-Paths In Logic Circuits [p. 87]
PDF icon Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis [p. 622]
Mohanty, S.P.
PDF icon Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems [p. 917]
Molter, H.G.
PDF icon SC-DEVS: An Efficient Systemc Extension for the DEVS Model of Computation [p. 1518]
Monreal, T.
PDF icon Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap [p. 530]
Monteiro, J.C.
PDF icon A MILP-Based Approach to Path Sensitization of Embedded Software [p. 1568]
Mony, H.
PDF icon Speculative Reduction-Based Scalable Redundancy Identification [p. 1674]
PDF icon Scalable Liveness Checking via Property-Preserving Transformations [p. 1680]
Moore, B.
PDF icon Contactless Testing: Possibility or Pipe-Dream? [p. 676]
Mori, T.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Mplemenos, G.-G.
PDF icon Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
Mudge, T.
PDF icon Using Non-Volatile Memory to Save Energy in Servers [p. 743]
Mueller, R.
PDF icon An Approach to Linear Model-Based Testing and Diagnosis for Nonlinear Cascaded Mixed-Signal Systems [p. 1662]
Mueller, S.
PDF icon A Novel LDPC Decoder for DVB-S2 IP [p. 1308]
Mueller, W.
PDF icon A UML Frontend for IP-XACT-Based IP Management [p. 238]
PDF icon Increased Accuracy through Noise Injection in RTOS Simulation [p. 1632]
Mueller-Glaser, K.D.
PDF icon Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems [p. 178]
Mukherjee, S.
PDF icon A Formal Approach for Specification-Driven AMS Behavioral Model Generation [p. 1512]
Mukhopadhyay, R.
PDF icon A Formal Approach for Specification-Driven AMS Behavioral Model Generation [p. 1512]
Muller, M.
PDF icon Has Anything Changed in Electronic Design Since 1983? [p. 1]
Murali, S.
PDF icon SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips [p. 9]
Murciano, M.
PDF icon Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints [p. 1686]
Mylavarapu, S.K.
PDF icon FSAF: File System Aware Flash Translation Layer for NAND Flash Memories [p. 399]

N

Nagaraj, K.
PDF icon A Study on Placement of Post Silicon Clock Tuning Buffers for Mitigating Impact of Process Variation [p. 292]
Nalla, P.K.
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Narayanan, S.H.K.
PDF icon Process Variation Aware Thread Mapping for Chip Multiprocessors [p. 821]
Nassar, M.
PDF icon Successful Attack of an FPGA-Based WDDL DES Cryptoprocessor without Place and Route Constraints [p. 640]
Nassif, S.
PDF icon Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications [p. 375]
Nebel, W.
PDF icon OSSS+R: A Framework for Application Level Modelling and Synthesis of Reconfigurable Systems [p. 970]
PDF icon An Automated Flow For Integrating Hardware IP into the Automotive Systems Engineering Process [p. 1196]
Negrean, M.
PDF icon Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources [p. 524]
Neishaburi, M.H.
PDF icon An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
Nejad, A.B.
PDF icon A High-Level Debug Environment for Communication-Centric Debug [p. 202]
Nepal, K.
PDF icon Detecting Errors Using Multi-Cycle Invariance Information [p. 791]
Neubauer, H.
PDF icon Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing [p. 369]
Ney, A.
PDF icon A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
Nezan, J.-F.
PDF icon Scalable Compile-Time Scheduler for Multi-Core Architectures [p. 1552]
Nguyen, T.K. T.
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
Nicolescu, G.
PDF icon Co-Simulation Based Platform for Wireless Protocols Design Explorations [p. 874]
Nicolici, N.
PDF icon Automated Data Analysis Solutions to Silicon Debug [p. 982]
PDF icon Finite Precision Bit-Width Allocation Using SAT-Modulo Theory [p. 1106]
Niemetz, M.
PDF icon Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems [p. 519]
Nikara, J.
PDF icon A Case for Multi-Channel Memories in Video Recording [p. 934]
Nikolos, D.
PDF icon LFSR-Based Test-Data Compression with Self-Stoppable Seeds [p. 1482]
Ning, D.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Nocco, S.
PDF icon Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints [p. 1686]
Nohl, A.
PDF icon Programming MPSoC Platforms: Road Works Ahead! [p. 1584]
Nonogaki, N.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Novo, D.
PDF icon Finite Precision Processing in Wireless Applications [p. 1230]
Nyborg Gregertsen, K.
PDF icon An Efficient and Deterministic Multi-Tasking Run-Time Environment for Ada and the Ravenscar Profile on Atmel AVR ®32 UC3 Microcontroller [p. 1572]

O

Oetjens, J.
PDF icon An Automated Flow For Integrating Hardware IP into the Automotive Systems Engineering Process [p. 1196]
Ohno, H.
PDF icon MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
Ohyama, R.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Okamoto, T.
PDF icon Register Placement for High-Performance Circuits [p. 1470]
Okuda, Y.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Olivieri, M.
PDF icon Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip [p. 906]
Oppenheimer, F.
PDF icon OSSS+R: A Framework for Application Level Modelling and Synthesis of Reconfigurable Systems [p. 970]
Orailoglu, A.
PDF icon Towards No-Cost Adaptive MPSoC Static Schedules through Exploitation of Logical-to-Physical Core Mapping Latitude [p. 63]
PDF icon Making DNA Self-Assembly Error-Proof: Attaining Small Growth Error Rates through Embedded Information Redundancy [p. 898]
Osborne, C.
PDF icon Heterogeneous Multi-Core Platform for Consumer Multimedia Applications [p. 1254]
Ozturk, O.
PDF icon Adaptive Prefetching for Shared Cache Based Chip Multiprocessors [p. 773]
PDF icon Process Variation Aware Thread Mapping for Chip Multiprocessors [p. 821]
PDF icon Using Dynamic Compilation for Continuing Execution under Reduced Memory Availability [p. 1373]

P

Pacalet, R.
PDF icon SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection [p. 570]
Paci, G.
PDF icon Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation Techniques for Full-Swing and Low-Swing On-Chip Communication Channels [p. 1404]
Paik, S.
PDF icon HLS-L: High-Level Synthesis of High Performance Latch-Based Circuits [p. 1112]
Palcovic, M.
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
Palermo, G.
PDF icon MPSoCs Run-Time Monitoring through Networks-on-Chip [p. 558]
Palmers, P.
PDF icon Massively Multi-Topology Sizing of Analog Integrated Circuits [p. 706]
Pan, A.
PDF icon Improving Yield and Reliability of Chip Multiprocessors [p. 490]
Pan, D.Z.
PDF icon Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees [p. 296]
Panda, P.R.
PDF icon Cache Aware Compression for Processor Debug Support [p. 208]
PDF icon A Generic Platform for Estimation of Multi-Threaded Program Performance on Heterogeneous Multiprocessor [p. 1018]
Panda, S.K.
PDF icon A Formal Approach for Specification-Driven AMS Behavioral Model Generation [p. 1512]
Pandini, D.
PDF icon EMC-Aware Design on a Microcontroller for Automotive Applications [p. 1208]
Papaefstathiou, I.
PDF icon Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
Papariello, F.
PDF icon Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip [p. 906]
Parameswaran, S.
PDF icon CUFFS: An Instruction Count Based Architectural Framework for Security of MPSoCs [p. 779]
Passerone, R.
PDF icon UMTS MPSoC Design Evaluation Using a System Level Design Framework [p. 478]
Patel, K.
PDF icon CUFFS: An Instruction Count Based Architectural Framework for Security of MPSoCs [p. 779]
Paterna, F.
PDF icon Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip [p. 906]
Patil, N.
PDF icon Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect Ttransistors [p. 436]
Pautet, L.
PDF icon Mode-Based Reconfiguration of Critical Software Component Architectures [p. 1160]
Pavlidis, V.F.
PDF icon A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs [p. 172]
Pedram, M.
PDF icon Efficient Compression and Handling of Current Source Model Library Waveforms [p. 1178]
Peh, L.-S.
PDF icon ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration [p. 423]
Pelcat, M.
PDF icon Scalable Compile-Time Scheduler for Multi-Core Architectures [p. 1552]
Peng, H.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
PDF icon Parallel Transistor Level Full-Chip Circuit Simulation [p. 304]
Peng, Z.
PDF icon Integrated Scheduling and Synthesis of Control Applications on Distributed Embedded Systems [p. 57]
PDF icon Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors [p. 682]
Perathoner, S.
PDF icon Reliable Mode Changes in Real-Time Systems with Fixed Priority or EDF Scheduling [p. 99]
Perbellini, G.
PDF icon Networked Embedded System Applications Design Driven by an Middleware Environment [p. 1024]
PDF icon Flexible Energy-Aware Simulation of Heterogeneous Wireless Sensor Networks [p. 1638]
Perry, S.
PDF icon Model Based Design Needs High Level Synthesis [p. 1202]
Petrot, F.
PDF icon Extending IP-XACT to Support an MDE Based Approach For SoC Design [p. 586]
Pi, L.
PDF icon Towards a Formal Semantics for the AADL Behavior Annex [p. 1166]
Pierrelee, O.
PDF icon High Data Rate Fully Flexible SDR Modem [p. 1040]
Pigorsch, F.
PDF icon Exploiting Structure in an AIG Based QBF Solver [p. 1596]
Pinto, A.
PDF icon A Case Study in Distributed Deployment of Embedded Software for Camera Networks [p. 1006]
Pixley, C.
PDF icon Solver Technology for System-level to RTL Equivalence Checking [p. 196]
Plishker, W.
PDF icon A Generalized Scheduling Approach for Dynamic Dataflow Applications [p. 111]
Plosila, J.
PDF icon An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
Pnevmatikatos, D.
PDF icon Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
PDF icon ReSiM, A Trace-Driven, Reconfigurable ILP Processor Simulator [p. 536]
Polian, I.
PDF icon Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors [p. 682]
Pollex, V.
PDF icon Improved Worst-Case Response-Time Calculations by Upper-Bound Conditions [p. 105]
Pomeranz, I.
PDF icon Selection of a Fault Model for Fault Diagnosis Based on Unique Responses [p. 994]
PDF icon A Scalable Method for the Generation of Small Test Sets [p. 1136]
Poncino, M.
PDF icon Enabling Concurrent Clock and Power Gating in an Industrial Design Flow [p. 334]
Pop, P.
PDF icon Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors [p. 682]
Popovich, M.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
Popp, R.
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Porrmann, M.
PDF icon Design Optimizations to Improve Placeability of Partial Reconfiguration Modules [p. 976]
Potkonjak, M.
PDF icon Hardware Aging-Based Software Metering [p. 460]
PDF icon Energy Minimization for Real-Time Systems with Non-Convex and Discrete Operation Modes [p. 1416]
Potter, P.G
PDF icon Partition-Based Exploration for Reconfigurable JPEG Designs [p. 886]
Pozzi, L.
PDF icon Heterogeneous Coarse-Grained Processing Elements: A Template Architecture for Embedded Processing Acceleration [p. 542]
Pradhan, D.K.
PDF icon Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems [p. 917]
Pravadelli, G.
PDF icon Functional Qualification of TLM Verification [p. 190]
PDF icon Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches [p. 1500]
Pravossoudovitch, S.
PDF icon A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
Pressler, M.
PDF icon White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling [p. 513]
Prete, C.A.
PDF icon A Power-Efficient Migration Mechanism for D-NUCA Caches [p. 598]
Prinetto, P.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
Pronath, M.
PDF icon Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
Pueschel, M.
PDF icon Automatic Generation of Streaming Datapaths for Arbitrary Fixed Permutations [p. 1118]
Pujol, L.
PDF icon Contactless Testing: Possibility or Pipe-Dream? [p. 676]
Pullini, A.
PDF icon Physically Clustered Forward Body Biasing for Variability Compensation in Nano-Meter CMOS Design [p. 154]
PDF icon Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis [p. 616]
Purandare, M.
PDF icon Strengthening Properties Using on Refinement [p. 1692]
Puri, S.
PDF icon An MDE Methodology for the Development of High-Integrity Real-Time Systems [p. 1154]
Puschini, D.
PDF icon Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC [p. 1564]
Putzke-Roeming, W.
PDF icon Mapping of a Film Grain Removal Algorithm to a Heterogeneous Reconfigurable Architecture [p. 27]

Q

Qi, Z.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Quaglia, D.
PDF icon Flexible Energy-Aware Simulation of Heterogeneous Wireless Sensor Networks [p. 1638]
Quer, S.
PDF icon Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints [p. 1686]

R

Radetzki, M.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
Ragel, R.
PDF icon CUFFS: An Instruction Count Based Architectural Framework for Security of MPSoCs [p. 779]
Raghunathan, A.
PDF icon An Architecture for Secure Software Defined Radio [p. 448]
Rajaram, A.
PDF icon Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees [p. 296]
Rajski, J.
PDF icon A Scalable Method for the Generation of Small Test Sets [p. 1136]
Ramaherirariny, T.
PDF icon Aircraft Integration Real-Time Simulator Modeling with AADL for Architecture Tradeoffs [p. 346]
Ravindran, B.
PDF icon On Bounding Response Times under Software Transactional Memory in Distributed Multiprocessor Real-Time Systems [p. 688]
Real, D.
PDF icon Enhancing Correlation Electro-Magnetic Attack Using Planar Near-Field Cartography [p. 628]
Reda, S.
PDF icon Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications [p. 375]
Reddi, V.J
PDF icon An Event-Guided Approach to Reducing Voltage Noise in Processors [p. 160]
Reddy, S.M.
PDF icon Selection of a Fault Model for Fault Diagnosis Based on Unique Responses [p. 994]
PDF icon Improving Compressed Test Pattern Generation for Multiple Scan Chain Failure Diagnosis [p. 1000]
PDF icon A Scalable Method for the Generation of Small Test Sets [p. 1136]
Reichelt, S.
PDF icon The Influence of Real-time Constraints on the Design of FlexRay-based Systems [p. 858]
Reina Nieves, A.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Reis, R.
PDF icon A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable Chips [p. 352]
Reitemeyer, S.
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Relles, J.
PDF icon An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models [p. 1190]
Remersaro, S.
PDF icon A Scalable Method for the Generation of Small Test Sets [p. 1136]
Ren, Q.
PDF icon Optimizing Data Flow Graphs to Minimize Hardware Implementation [p. 117]
Reyes, V.
PDF icon Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0 [p. 316]
Richter, K.
PDF icon Learning Early-Stage Platform Dimensioning from Late-Stage Timing Verification [p. 851]
Ristau, B.
PDF icon Dimensioning Heterogeneous MPSoCs via Parallelism Analysis [p. 554]
Robert, M.
PDF icon Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA [p. 634]
Roberts, D.
PDF icon Using Non-Volatile Memory to Save Energy in Servers [p. 743]
Rocchi, A.
PDF icon Shock Immunity Enhancement via Resonance Damping in Gyroscopes for Automotive Applications [p. 1094]
Roncella, R.
PDF icon Distributed Sensor For Steering Wheel Grip Force Measurement In Driver Fatigue Detection [p. 894]
Roncolato, N.
PDF icon Networked Embedded System Applications Design Driven by an Middleware Environment [p. 1024]
Roop, P.S.
PDF icon Multi-Clock SOC Design Using Protocol Conversion [p. 123]
Rosenstiel, W.
PDF icon White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling [p. 513]
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Roth, C.
PDF icon Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems [p. 178]
Rotigni, M.
PDF icon EMC-Aware Design on a Microcontroller for Automotive Applications [p. 1208]
Rouge, L.
PDF icon Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor [p. 184]
Rueda Morales, C.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Ruf, J.
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Ruggiero, M.
PDF icon Visual Quality Analysis for Dynamic Backlight Scaling in LCD Systems [p. 1428]
Ruiz-Merino, R.
PDF icon Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing [p. 369]

S

Sabeghi, M.
PDF icon Toward a Runtime System for Reconfigurable Computers: A Virtualization Approach [p. 1576]
Saez Gomez, J.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Safizadeh, H.
PDF icon Using Randomization to Cope with Circuit Uncertainty [p. 815]
Sahlbach, H.
PDF icon Mapping of a Film Grain Removal Algorithm to a Heterogeneous Reconfigurable Architecture [p. 27]
Sahu, A.
PDF icon A Generic Platform for Estimation of Multi-Threaded Program Performance on Heterogeneous Multiprocessor [p. 1018]
Salcic, Z
PDF icon Multi-Clock SOC Design Using Protocol Conversion [p. 123]
Saletti, R.
PDF icon Distributed Sensor For Steering Wheel Grip Force Measurement In Driver Fatigue Detection [p. 894]
Salimi Khaligh, R.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
Salminen, E.
PDF icon Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA [p. 244]
Samadi, K.
PDF icon ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration [p. 423]
Samii, S.
PDF icon Integrated Scheduling and Synthesis of Control Applications on Distributed Embedded Systems [p. 57]
Sandell, M.
PDF icon Implementation of a Reduced-Lattice MIMO Detector for OFDM Systems [p. 1626]
Sander, I.
PDF icon Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures [p. 1506]
Sander, O.
PDF icon Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems [p. 178]
Sane, N.
PDF icon A Generalized Scheduling Approach for Dynamic Dataflow Applications [p. 111]
Sangiovanni-Vincentelli, A.
PDF icon UMTS MPSoC Design Evaluation Using a System Level Design Framework [p. 478]
PDF icon Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay [p. 1076]
Sanz Velasco, P.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Sarbazi-Azad, H.
PDF icon A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM [p. 566]
Sarlotte, M.
PDF icon High Data Rate Fully Flexible SDR Modem [p. 1040]
Sarrafzadeh, M.
PDF icon Energy Minimization for Real-Time Systems with Non-Convex and Discrete Operation Modes [p. 1416]
Sartori, J.
PDF icon Distributed Peak Power Management for Many-Core Architectures [p. 1556]
Sasaki, S.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Sasan, A.
PDF icon Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling [p. 911]
Sassatelli, G.
PDF icon Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor [p. 184]
PDF icon Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC [p. 1564]
Sathanur, A.
PDF icon Physically Clustered Forward Body Biasing for Variability Compensation in Nano-Meter CMOS Design [p. 154]
Sattler, S.
PDF icon An Approach to Linear Model-Based Testing and Diagnosis for Nonlinear Cascaded Mixed-Signal Systems [p. 1662]
Sauvage, L.
PDF icon Successful Attack of an FPGA-Based WDDL DES Cryptoprocessor without Place and Route Constraints [p. 640]
Schallenberg, A.
PDF icon OSSS+R: A Framework for Application Level Modelling and Synthesis of Reconfigurable Systems [p. 970]
Schat, J.
PDF icon On the Relationship between Stuck-At Fault Coverage and Transition Fault Coverage [p. 1218]
Schattkowsky, T.
PDF icon A UML Frontend for IP-XACT-Based IP Management [p. 238]
Schaumont, P.
PDF icon Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage [p. 454]
Scheickl, O.
PDF icon The Influence of Real-time Constraints on the Design of FlexRay-based Systems [p. 858]
Schlichtmann, U.
PDF icon On Hierarchical Statistical Static Timing Analysis [p. 1320]
PDF icon Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
Schliecker, S.
PDF icon Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources [p. 524]
Schmidt, D.
PDF icon Error Correction in Single-Hop Wireless Sensor Networks - A Case Study [p. 1296]
Schmidt, M.
PDF icon On Hierarchical Statistical Static Timing Analysis [p. 1320]
PDF icon Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
Schneider, K.
PDF icon Separate Compilation and Execution of Imperative Synchronous Modules [p. 1580]
Schneider, W.
PDF icon On Hierarchical Statistical Static Timing Analysis [p. 1320]
Schoenknecht, V.
PDF icon Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
Scholl, C.
PDF icon Exploiting Structure in an AIG Based QBF Solver [p. 1596]
Schreger, M.
PDF icon A Novel LDPC Decoder for DVB-S2 IP [p. 1308]
Schwarz, C.
PDF icon SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection [p. 570]
Sciuto, D.
PDF icon A Real-Time Application Design Methodology for MPSoCs [p. 767]
Seepold, R.
PDF icon Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
Seiculescu, C.
PDF icon SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips [p. 9]
Sellathamby, C.
PDF icon Contactless Testing: Possibility or Pipe-Dream? [p. 676]
Seshia, S.A.
PDF icon Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits [p. 785]
PDF icon Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay [p. 1076]
Seymour, N.
PDF icon System-Level Hardware-Based Protection of Memories against Soft-Errors [p. 1222]
Sgroi, M.
PDF icon Communication Minimization for In-Network Processing in Body Sensor Networks: A Buffer Assignment Technique [p. 358]
Shafique, M.
PDF icon Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors [p. 958]
PDF icon A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC Video Codec [p. 1434]
Shang, L.
PDF icon Latency Criticality Aware On-Chip Communication [p. 1052]
Shayan, A.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
Shih, W.-Y.
PDF icon Package Routability-and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design [p. 845]
Shin, D.
PDF icon KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems [p. 507]
Shin, I.
PDF icon HLS-L: High-Level Synthesis of High Performance Latch-Based Circuits [p. 1112]
Shin, Y.
PDF icon HLS-L: High-Level Synthesis of High Performance Latch-Based Circuits [p. 1112]
Shrivastava, A.
PDF icon FSAF: File System Aware Flash Translation Layer for NAND Flash Memories [p. 399]
PDF icon Static Analysis to Mitigate Soft Errors in Register Files [p. 1367]
Sifakis, J.
PDF icon Embedded Systems Design - Scientific Challenges and Work Directions [p. 2]
Silvano, C.
PDF icon MPSoCs Run-Time Monitoring through Networks-on-Chip [p. 558]
Silveira, L.M.
PDF icon On the Efficient Reduction of Complete EM Based Parametric Models [p. 1172]
Simalatsar, A.
PDF icon UMTS MPSoC Design Evaluation Using a System Level Design Framework [p. 478]
Simunic-Rosing, T.
PDF icon Dynamic Thermal Management in 3D Multicore Architectures [p. 1410]
Singh, J.
PDF icon Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems [p. 917]
Singh, V.
PDF icon Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips [p. 484]
Sinha, R.
PDF icon Multi-Clock SOC Design Using Protocol Conversion [p. 123]
Sinha, S.
PDF icon Sequential Logic Rectifications with Approximate SPFDs [p. 1698]
Siorpaes, D.
PDF icon Predictive Models for Multimedia Applications Power Consumption Based on Use-Case and OS Level Analysis [p. 1446]
Siozios, K.
PDF icon A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs [p. 172]
Skavhaug, A.
PDF icon An Efficient and Deterministic Multi-Tasking Run-Time Environment for Ada and the Ravenscar Profile on Atmel AVR ®32 UC3 Microcontroller [p. 1572]
Slomka, F.
PDF icon Improved Worst-Case Response-Time Calculations by Upper-Bound Conditions [p. 105]
PDF icon Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems [p. 519]
Slupsky, S.
PDF icon Contactless Testing: Possibility or Pipe-Dream? [p. 676]
Smith, D.
PDF icon Sequential Logic Rectifications with Approximate SPFDs [p. 1698]
Soares, R.
PDF icon Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA [p. 634]
Soler-Garrido, J.
PDF icon Implementation of a Reduced-Lattice MIMO Detector for OFDM Systems [p. 1626]
Sommer, G.
PDF icon Cross-Coupling in 65nm Fully Integrated EDGE System on Chip - Design and Cross-Coupling Prevention of Complex 65nm SoC [p. 1045]
Sonza Reorda, M.
PDF icon A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable Chips [p. 352]
Sotiriades, E.
PDF icon Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
Soudris, D.
PDF icon A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs [p. 172]
Soulard, P.
PDF icon A Co-Design Approach for Embedded System Modeling and Code Generation with UML and MARTE [p. 226]
Sowmya, A.
PDF icon A Formal Approach to Design Space Exploration of Protocol Converters [p. 129]
Spallek, R.G.
PDF icon Generating the Trace Qualification Configuration for MCDS from a High Level Language [p. 1560]
Speight, E.
PDF icon Power and Performance of Read-Write Aware Hybrid Caches with Non-volatile Memories [p. 737]
Sreedhar, A.
PDF icon On Linewidth-Based Yield Analysis for Nanometer Lithography [p. 381]
Steger, C.
PDF icon Fault Insertion Testing of a Novel CPLD-Based Fail-Safe System [p. 214]
Steger, C.
PDF icon A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing [p. 1614]
Steinhorst, S.
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Steininger, A.
PDF icon Remote Measurement of Local Oscillator Drifts in FlexRay Networks [p. 1082]
Sterpone, L.
PDF icon A Study of the Single Event Effects Impact on Functional Mapping within Flash-Based FPGAs [p. 1226]
Steyaert, M.
PDF icon Massively Multi-Topology Sizing of Analog Integrated Circuits [p. 706]
Stoimenov, N.
PDF icon Reliable Mode Changes in Real-Time Systems with Fixed Priority or EDF Scheduling [p. 99]
Strasser, M.
PDF icon Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
Stratigopoulos, H.-G.
PDF icon Enrichment of Limited Training Sets in Machine-Learning-Based Analog/RF Test [p. 1668]
Streubuehr, M.
PDF icon Combined System Synthesis and Communication Architecture Exploration for MPSoCs [p. 472]
Stroobandt, D.
PDF icon Automatically Mapping Applications to a Self-Reconfiguring Platform [p. 964]
Su, L.
PDF icon SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection [p. 570]
Suarez, D.
PDF icon Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap [p. 530]
Subburaman, M.
PDF icon aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services [p. 250]
Subramanian, V.
PDF icon Online Adaptation Policy Design for Grid Sensor Networks with Reconfigurable Embedded Nodes [p. 1273]
Suelflow, A.
PDF icon Increasing the Accuracy of SAT-Based Debugging [p. 1326]
Sun, Y.
PDF icon Latency Criticality Aware On-Chip Communication [p. 1052]
Swaminathan, M.
PDF icon A Novel Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles [p. 1656]
Sylvester, D.
PDF icon A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs [p. 21]

T

Tabanoglu, G.
PDF icon The Influence of Real-time Constraints on the Design of FlexRay-based Systems [p. 858]
Tahghighi, M.
PDF icon Using Randomization to Cope with Circuit Uncertainty [p. 815]
Talpin, J.-P.
PDF icon Separate Compilation and Execution of Imperative Synchronous Modules [p. 1580]
Tan, S. X.-D.
PDF icon An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models [p. 1190]
Tang, X.
PDF icon Improving Compressed Test Pattern Generation for Multiple Scan Chain Failure Diagnosis [p. 1000]
Tannir, D.
PDF icon Computation of IP3 Using Single-Tone Moments Analysis [p. 718]
Tao, Y.
PDF icon Decoupling Capacitor Planning with Analytical Delay Model on RLC Power Grid [p. 839]
Tasdizen, O.
PDF icon A High Performance Reconfigurable Motion Estimation Hardware Architecture [p. 882]
Tavasoli, G.
PDF icon Using Randomization to Cope with Circuit Uncertainty [p. 815]
Teich, J.
PDF icon Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms [p. 135]
PDF icon Incorporating Graceful Degradation into Embedded System Design [p. 320]
PDF icon Combined System Synthesis and Communication Architecture Exploration for MPSoCs [p. 472]
PDF icon CAN+: A New Backward-Compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates [p. 1088]
Tenhunen, H.
PDF icon An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
Tessier, R.
PDF icon A Monitor Interconnect and Support Subsystem for Multicore Processors [p. 761]
Theodoropoulos, D.
PDF icon Algorithms for the Automatic Extension of an Instruction-Set [p. 548]
Thiele, L.
PDF icon Reliable Mode Changes in Real-Time Systems with Fixed Priority or EDF Scheduling [p. 99]
PDF icon An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous Multiprocessor Systems [p. 694]
Tokuyoshi, T.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Toms, T.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
Torres, L.
PDF icon Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor [p. 184]
PDF icon Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA [p. 634]
PDF icon Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC [p. 1564]
Novo, D.
PDF icon Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors [p. 1608]
Flynn, D.
PDF icon Selective State Retention Design Using Symbolic Simulation [p. 1644]
Toumazou, C.
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
Traulsen, C.
PDF icon WCRT Algebra and Interfaces for Esterel-Style Synchronous Processing [p. 93]
Trautmann, M.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
Trucco, G.
PDF icon On Decomposing Boolean Functions via Extended Cofactoring [p. 1464]
Tsuboi, Y.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Tuominen, P.A.
PDF icon A Case for Multi-Channel Memories in Video Recording [p. 934]
Tzeng, C.-W.
PDF icon QC-Fill: An X-Fill Method for Quick-and-Cool Scan Test [p. 1142]

U

Ueda, Y.
PDF icon Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
Um, J.
PDF icon In-Network Reorder Buffer to Improve Overall NoC Performance While Resolving the In-Order Requirement Problem [p. 1058]
Umans, E.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
Uygur, G.
PDF icon A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow [p. 797]

V

Vadlamani, R.
PDF icon A Monitor Interconnect and Support Subsystem for Multicore Processors [p. 761]
Vahdatpour, A.
PDF icon Energy Minimization for Real-Time Systems with Non-Convex and Discrete Operation Modes [p. 1416]
Vajda, A.
PDF icon Programming MPSoC Platforms: Road Works Ahead! [p. 1584]
Valette, F.
PDF icon Enhancing Correlation Electro-Magnetic Attack Using Planar Near-Field Cartography [p. 628]
Vallejo, F.
PDF icon Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap [p. 530]
van Berkel, C.H. (K)
PDF icon Multi-Core for Mobile Phones [p. 1260]
Van der Perre, L.
PDF icon Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
PDF icon Finite Precision Processing in Wireless Applications [p. 1230]
PDF icon Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors [p. 1608]
van Der Wolf, P.
PDF icon Flow Regulation for On-Chip Communication [p. 578]
van Haastregt, S. u
PDF icon Automated Synthesis of Streaming C Applications to Process Networks In Hardware [p. 890]
van Moll, B.
PDF icon Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0 [p. 316]
Vanhauwaert, P.
PDF icon Statistical Fault Injection: Quantified Error and Confidence [p. 502]
Vardanega, T.
PDF icon An MDE Methodology for the Development of High-Integrity Real-Time Systems [p. 1154]
Vayrynen, M.
PDF icon Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips [p. 484]
Vecchie, E.
PDF icon Separate Compilation and Execution of Imperative Synchronous Modules [p. 1580]
Vemuri, R.
PDF icon Selective Light Vth Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power Reduction [p. 594]
PDF icon A Graph Grammar Based Approach to Automated Multi-Objective Analog Circuit Design [p. 700]
Veneris, A.
PDF icon Automated Data Analysis Solutions to Silicon Debug [p. 982]
PDF icon Sequential Logic Rectifications with Approximate SPFDs [p. 1698]
Vermeulen, B.
PDF icon A High-Level Debug Environment for Communication-Centric Debug [p. 202]
Vetter, H.
PDF icon Implementation of a Reduced-Lattice MIMO Detector for OFDM Systems [p. 1626]
Vidal, J.
PDF icon A Co-Design Approach for Embedded System Modeling and Code Generation with UML and MARTE [p. 226]
Viehl, A.
PDF icon White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling [p. 513]
Vignon, A.
PDF icon System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
PDF icon A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context [p. 929]
Vijaykrishnan, N.
PDF icon Exploiting Clock Skew Scheduling for FPGA [p. 1524]
Villa, T.
PDF icon On Decomposing Boolean Functions via Extended Cofactoring [p. 1464]
Villavicencio, Y.
PDF icon EMC-Aware Design on a Microcontroller for Automotive Applications [p. 1208]
Vinals, V.
PDF icon Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap [p. 530]
Vinco, S.
PDF icon Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches [p. 1500]
Violante, M.
PDF icon A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable Chips [p. 352]
PDF icon A Study of the Single Event Effects Impact on Functional Mapping within Flash-Based FPGAs [p. 1226]
Virazel, A.
PDF icon A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
Vishnoi, A.
PDF icon Cache Aware Compression for Processor Debug Support [p. 208]
Volckaerts, B.
PDF icon Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
von Hanxleden, R.
PDF icon WCRT Algebra and Interfaces for Esterel-Style Synchronous Processing [p. 93]
Vroon, D.
PDF icon Faster SAT Solving with Better CNF Generation [p. 1590]
Vrudhula, S.
PDF icon Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints [p. 1548]

W

Wagner, I.
PDF icon CASPAR: Hardware Patching for Multi-Core Processors [p. 658]
Wahl, T.
PDF icon Strengthening Properties Using on Refinement [p. 1692]
Wang, B.
PDF icon An Accurate Interconnect Thermal Model Using Equivalent Transmission Line Circuit [p. 280]
Wang, C.-Y.
PDF icon Rewiring Using IRredundancy Removal and Addition [p. 324]
Wang, L.
PDF icon An Automated Design Flow for Vibration-Based Energy Harvester Systems [p. 1391]
Wang, S.
PDF icon Machine Learning-Based Volume Diagnosis [p. 902]
PDF icon Exploiting Narrow-Width Values for Thermal-Aware Register File Designs [p. 1422]
Wang, W.
PDF icon Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization [p. 328]
Wang, X.
PDF icon An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models [p. 1190]
Wang, Y.
PDF icon Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization [p. 328]
PDF icon Formal Approaches to Analog Circuit Verification [p. 724]
Waxman, C.
PDF icon Architectural Support for Low Overhead Detection of Memory Violations [p. 652]
Wegener, C.
PDF icon An Approach to Linear Model-Based Testing and Diagnosis for Nonlinear Cascaded Mixed-Signal Systems [p. 1662]
Wehn, N.
PDF icon Error Correction in Single-Hop Wireless Sensor Networks - A Case Study [p. 1296]
PDF icon A Novel LDPC Decoder for DVB-S2 IP [p. 1308]
Wei, G.-Y.
PDF icon An Event-Guided Approach to Reducing Voltage Noise in Processors [p. 160]
Wei, H.
PDF icon Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect Ttransistors [p. 436]
Wei, W.
PDF icon Machine Learning-Based Volume Diagnosis [p. 902]
Weiss, R.
PDF icon Fault Insertion Testing of a Novel CPLD-Based Fail-Safe System [p. 214]
Weixing, J.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Whitty, S.
PDF icon Mapping of a Film Grain Removal Algorithm to a Heterogeneous Reconfigurable Architecture [p. 27]
Wilcock, R.
PDF icon Improved Performance and Variation Modelling for Hierarchical-Based Optimisation of Analogue Integrated Circuits [p. 712]
PDF icon Optimal Sizing of Configurable Devices to Reduce Variability in Integrated Circuits [p. 1385]
Wildermann, S.
PDF icon CAN+: A New Backward-Compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates [p. 1088]
Wille, R.
PDF icon Debugging of Toffoli Networks [p. 1284]
Wilson, P.
PDF icon Improved Performance and Variation Modelling for Hierarchical-Based Optimisation of Analogue Integrated Circuits [p. 712]
PDF icon Optimal Sizing of Configurable Devices to Reduce Variability in Integrated Circuits [p. 1385]
Wirrer, G.
PDF icon Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems [p. 519]
Wolinski, C.
PDF icon A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications [p. 1242]
Wong, N.
PDF icon New Simulation Methodology of 3D Surface Roughness Loss for Interconnects Modeling [p. 1184]
Wu, J.
PDF icon Latency Criticality Aware On-Chip Communication [p. 1052]
Wu, K.-C.
PDF icon Joint Logic Restructuring and Pin Reordering against NBTI-Induced Performance Degradation [p. 75]
Wu, P.-L.
PDF icon A File-System-Aware FTL Design for Flash-Memory Storage Systems [p. 393]
Wu, X.
PDF icon Power and Performance of Read-Write Aware Hybrid Caches with Non-volatile Memories [p. 737]
Wunderlich, H.-J.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
PDF icon A Diagnosis Algorithm for Extreme Space Compaction [p. 1355]
Wuytack, S.
PDF icon Exploring Parallelizations of Applications for MPSoC Platforms Using MPA [p. 1148]

X

Xie, F.
PDF icon Componentizing Hardware/Software Interface Design [p. 232]
Xie, T.
PDF icon A UML Frontend for IP-XACT-Based IP Management [p. 238]
Xie, Y.
PDF icon Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization [p. 328]
PDF icon Power and Performance of Read-Write Aware Hybrid Caches with Non-volatile Memories [p. 737]
Xu, H.
PDF icon Selective Light Vth Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power Reduction [p. 594]
Xu, J.
PDF icon A Low-Power Fat Tree-Based Optical Network-on-Chip for Multiprocessor System-on-Chip [p. 3]
Xu, Q.
PDF icon Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms [p. 51]
PDF icon Test Architecture Design and Optimization for Three-Dimensional SoCs [p. 220]
PDF icon Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation [p. 1338]
PDF icon A Generic Framework for Scan Capture Power Reduction in Fixed-Length Symbol-Based Test Compression Environment [p. 1494]

Y

Yan, G.
PDF icon A Unified Online Fault Detection Scheme Via Checking of Stability Violation [p. 496]
Yang, C.
PDF icon Towards No-Cost Adaptive MPSoC Static Schedules through Exploitation of Logical-to-Physical Core Mapping Latitude [p. 63]
Yang, C.-Y.
PDF icon An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous Multiprocessor Systems [p. 694]
Yang, H.
PDF icon Pipelined Data Parallel Task Mapping/Scheduling Technique for MPSoC [p. 69]
PDF icon Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization [p. 328]
PDF icon Energy-Efficient Spatially-Adaptive Clustering and Routing in Wireless Sensor Networks [p. 1267]
Yang, Y.-S.
PDF icon Automated Data Analysis Solutions to Silicon Debug [p. 982]
PDF icon Sequential Logic Rectifications with Approximate SPFDs [p. 1698]
Yang, Z.
PDF icon Towards a Formal Semantics for the AADL Behavior Annex [p. 1166]
Yeo, I.
PDF icon Temperature-Aware Scheduler Based on Thermal Behavior Grouping in Multicore Systems [p. 946]
Yi, Y.
PDF icon An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures [p. 33]
Yilmaz, M.
PDF icon Seed Selection in LFSR-Reseeding-Based Test Compression for the Detection of Small-Delay Defects [p. 1488]
Yoo, S.
PDF icon Program Phase and Runtime Distribution-Aware Online DVFS for Combined Vdd/Vbb Scaling [p. 417]
PDF icon In-Network Reorder Buffer to Improve Overall NoC Performance While Resolving the In-Order Requirement Problem [p. 1058]
Yoshimura, T.
PDF icon Register Placement for High-Performance Circuits [p. 1470]
Yu, W.
PDF icon Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
Yuan, F.
PDF icon Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms [p. 51]
Yuan, T.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]

Z

Zabel, H.
PDF icon Increased Accuracy through Noise Injection in RTOS Simulation [p. 1632]
Zamani, M.S.
PDF icon Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network [p. 833]
Zhang, J.
PDF icon Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect Ttransistors [p. 436]
PDF icon Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis [p. 616]
Zhang, L.
PDF icon Power and Performance of Read-Write Aware Hybrid Caches with Non-volatile Memories [p. 737]
Zhang, W.
PDF icon A Low-Power Fat Tree-Based Optical Network-on-Chip for Multiprocessor System-on-Chip [p. 3]
Zhang, Y.
PDF icon Adaptive Prefetching for Shared Cache Based Chip Multiprocessors [p. 773]
Zhao, X.
PDF icon An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures [p. 33]
Zhao, Y.
PDF icon Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips [p. 1290]
Zheng, W.
PDF icon Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay [p. 1076]
Zheng, Y.
PDF icon Defect-Aware Logic Mapping for Nanowire-Based Programmable Logic Arrays via Satisfiability [p. 1279]
Zhu, D.
PDF icon An Automated Design Flow for Vibration-Based Energy Harvester Systems [p. 1391]
Zhu, J.
PDF icon Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures [p. 1506]
Ziavras, S.G.
PDF icon Exploiting Narrow-Width Values for Thermal-Aware Register File Designs [p. 1422]
Ziermann, T.
PDF icon CAN+: A New Backward-Compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates [p. 1088]
Zoellin, C.G.
PDF icon Test Exploration and Validation Using Transaction Level Models [p. 1250]
Zrida, H.K.
PDF icon High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation [p. 940]
Zuo, W.
PDF icon Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
Zwolinski, M.
PDF icon Variation Resilient Adaptive Controller for Subthreshold Circuits [p. 142]