DATE 2009 AUTHOR INDEX
[A]
[B]
[C]
[D]
[E]
[F]
[G]
[H]
[I]
[J]
[K]
[L]
[M]
[N]
[O]
[P]
[Q]
[R]
[S]
[T]
[U]
[V]
[W]
[X]
[Y]
[Z]
- Abadir,
M.
-
TRAM: A Tool for Temperature and Reliability Aware Memory Design
[p. 340]
- Abate,
F.
-
A Study of the Single Event Effects Impact on Functional Mapping within Flash-Based FPGAs
[p. 1226]
- Abbaspour,
S.
-
Efficient Compression and Handling of Current Source Model Library Waveforms
[p. 1178]
- Abel,
N.
-
DPR in High Energy Physics
[p. 39]
- Abid,
M.
-
High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation
[p. 940]
- Abouelella,
F.
-
Automatically Mapping Applications to a Self-Reconfiguring Platform
[p. 964]
- Aboulhamid,
E.M.
-
Co-Simulation Based Platform for Wireless Protocols Design Explorations
[p. 874]
- Acquaviva,
A.
-
Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip
[p. 906]
-
Flexible Energy-Aware Simulation of Heterogeneous Wireless Sensor Networks
[p. 1638]
- Afratis,
P.
-
Design and Implementation of a Database Filter for BLAST Acceleration
[p. 166]
- Afzali-Kusha,
A.
-
An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs
[p. 1064]
- Aggarwal,
A.
-
Architectural Support for Low Overhead Detection of Memory Violations
[p. 652]
- Ahmed,
S.Z.
-
Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL
Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor
[p. 184]
- Aho,
E.
-
A Case for Multi-Channel Memories in Video Recording
[p. 934]
- Ain,
A.
-
A Formal Approach for Specification-Driven AMS Behavioral Model Generation
[p. 1512]
- Aitken,
R.
-
Impact of Voltage Scaling on Nanoscale SRAM Reliability
[p. 387]
- Akella,
V.
-
Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing
[p. 1530]
- Akin,
A.
-
A High Performance Reconfigurable Motion Estimation Hardware Architecture
[p. 882]
- Al Faruque,
M.A.
-
Configurable Links for Runtime Adaptive On-Chip Communication
[p. 256]
- Albers,
K.
-
Improved Worst-Case Response-Time Calculations by Upper-Bound Conditions
[p. 105]
- Al-Hashimi,
B.M.
-
Variation Resilient Adaptive Controller for Subthreshold Circuits
[p. 142]
-
Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing
[p. 1349]
-
An Automated Design Flow for Vibration-Based Energy Harvester Systems
[p. 1391]
-
Selective State Retention Design Using Symbolic Simulation
[p. 1644]
- Ali,
S.
-
Improved Performance and Variation Modelling for Hierarchical-Based Optimisation of Analogue
Integrated Circuits
[p. 712]
- Alimohammad,
A.
-
A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development
and Verification
[p. 45]
- Alles,
M.
-
A Novel LDPC Decoder for DVB-S2 IP
[p. 1308]
- Alves,
N.
-
Detecting Errors Using Multi-Cycle Invariance Information
[p. 791]
- Ammari,
A.C.
-
High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation
[p. 940]
- Angiolini,
F.
-
Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces
[p. 262]
- Ansaloni,
G.
-
Heterogeneous Coarse-Grained Processing Elements: A Template Architecture for Embedded
Processing Acceleration
[p. 542]
- Arakida,
H.
-
Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor
[p. 1035]
- Ardestani,
E.K.
-
Using Randomization to Cope with Circuit Uncertainty
[p. 815]
- Ares,
F.
-
Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform
[p. 1100]
- Aridhi,
S.
-
Scalable Compile-Time Scheduler for Multi-Core Architectures
[p. 1552]
- Arjomand,
M.
-
A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM
[p. 566]
- Armengaud,
E.
-
Remote Measurement of Local Oscillator Drifts in FlexRay Networks
[p. 1082]
- Arnold,
O.
-
Dimensioning Heterogeneous MPSoCs via Parallelism Analysis
[p. 554]
- Arpinen,
T.
-
Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA
[p. 244]
- Arslan,
T.
-
An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures
[p. 33]
- Ashby,
T.J.
-
Exploring Parallelizations of Applications for MPSoC Platforms Using MPA
[p. 1148]
- Atienza,
D.
-
Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis
[p. 616]
-
Dynamic Thermal Management in 3D Multicore Architectures
[p. 1410]
- Avnit,
K.
-
A Formal Approach to Design Space Exploration of Protocol Converters
[p. 129]
- Ayala,
J.
-
Dynamic Thermal Management in 3D Multicore Architectures
[p. 1410]
- Bachmann,
C.
-
A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing
[p. 1614]
- Bae,
S.
-
Exploiting Clock Skew Scheduling for FPGA
[p. 1524]
- Baert,
R.
-
Exploring Parallelizations of Applications for MPSoC Platforms Using MPA
[p. 1148]
- Baghdadi,
A.
-
ASIP-Based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications
[p. 1620]
- Bahar,
R.I.
-
Detecting Errors Using Multi-Cycle Invariance Information
[p. 791]
- Bakir,
M.
-
Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs
[p. 610]
- Balakrishnan,
M.
-
Cache Aware Compression for Processor Debug Support
[p. 208]
-
A Generic Platform for Estimation of Multi-Threaded Program Performance on Heterogeneous
Multiprocessor
[p. 1018]
- Balasa,
F.
-
Analog Layout Synthesis - Recent Advances in Topological Approaches
[p. 274]
- Baneres,
D.
-
Variable-Latency Design by Function Speculation
[p. 1704]
- Bannow,
N.
-
Analogue Mixed Signal Simulation Using Spice and SystemC
[p. 284]
- Baojun,
Q.
-
Group-Caching for NoC Based Multicore Cache Coherent Systems
[p. 755]
- Bardine,
A.
-
A Power-Efficient Migration Mechanism for D-NUCA Caches
[p. 598]
- Barke,
E.
-
Formal Approaches to Analog Circuit Verification
[p. 724]
- Baronti,
F.
-
Distributed Sensor For Steering Wheel Grip Force Measurement In Driver Fatigue Detection
[p. 894]
- Bartolini,
A.
-
Visual Quality Analysis for Dynamic Backlight Scaling in LCD Systems
[p. 1428]
- Bastian,
M.
-
A New Design-for-Test Technique for SRAM Core-Cell Stability Faults
[p. 1344]
- Basu,
S.
-
Multi-Clock SOC Design Using Protocol Conversion
[p. 123]
- Bauer,
L.
-
Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors
[p. 958]
-
A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC
Video Codec
[p. 1434]
- Baumgartner,
J.
-
Speculative Reduction-Based Scalable Redundancy Identification
[p. 1674]
-
Scalable Liveness Checking via Property-Preserving Transformations
[p. 1680]
- Bazargan,
K.
-
Using Randomization to Cope with Circuit Uncertainty
[p. 815]
- Becker,
J.
-
Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems
[p. 178]
- Bedani,
M.
-
A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard
[p. 364]
- Beeby,
S.P.
-
An Automated Design Flow for Vibration-Based Energy Harvester Systems
[p. 1391]
- Behrend,
J.
-
Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software
[p. 1214]
- Beivide,
R.
-
Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap
[p. 530]
- Bekooij,
M.
-
Programming MPSoC Platforms: Road Works Ahead!
[p. 1584]
- Bellasi,
P.
-
Predictive Models for Multimedia Applications Power Consumption Based on Use-Case and OS Level
Analysis
[p. 1446]
- Beltrame,
G.
-
A Real-Time Application Design Methodology for MPSoCs
[p. 767]
- Ben Jamaa,
M.H.
-
Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis
[p. 622]
- Benini,
L.
-
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips
[p. 9]
-
Physically Clustered Forward Body Biasing for Variability Compensation in Nano-Meter CMOS Design
[p. 154]
-
Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces
[p. 262]
-
Robust Non-Preemptive Hard Real-Time Scheduling for Clustered Multicore Platforms
[p. 803]
-
Efficient OpenMP Support and Extensions for MPSoCs with Explicitly Managed Memory Hierarchy
[p. 809]
-
Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip
[p. 906]
-
System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications
[p. 923]
-
Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation
Techniques for Full-Swing and Low-Swing On-Chip Communication Channels
[p. 1404]
-
Visual Quality Analysis for Dynamic Backlight Scaling in LCD Systems
[p. 1428]
- Benoit,
P.
-
Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC
[p. 1564]
- Berekovic,
M.
-
A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing
[p. 1614]
- Bernasconi,
A.
-
On Decomposing Boolean Functions via Extended Cofactoring
[p. 1464]
- Berning,
M.
-
Error Correction in Single-Hop Wireless Sensor Networks - A Case Study
[p. 1296]
- Bertacco,
V.
-
A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs
[p. 21]
-
Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't Cares
[p. 582]
-
CASPAR: Hardware Patching for Multi-Core Processors
[p. 658]
-
GCS: High-Performance Gate-Level Simulation with GP-GPUs
[p. 1332]
- Bertels,
K.
-
Algorithms for the Automatic Extension of an Instruction-Set
[p. 548]
-
Toward a Runtime System for Reconfigurable Computers: A Virtualization Approach
[p. 1576]
- Bertozzi,
D.
-
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale
Technology Constraints
[p. 562]
-
Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation
Techniques for Full-Swing and Low-Swing On-Chip Communication Channels
[p. 1404]
- Bhagawat,
P.
-
Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO System
[p. 870]
- Bhattacharyya,
S.S.
-
A Generalized Scheduling Approach for Dynamic Dataflow Applications
[p. 111]
- Biggs,
J.
-
Selective State Retention Design Using Symbolic Simulation
[p. 1644]
- Bild,
D.R
-
Minimization of NBTI Performance Degradation Using Internal Node Control
[p. 148]
- Blaauw,
D.
-
A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs
[p. 21]
- Bobba,
S.
-
Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis
[p. 616]
- Boers,
D.
-
Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior
for Embedded Real-Time Systems
[p. 519]
- Bok,
G.E.
-
Minimization of NBTI Performance Degradation Using Internal Node Control
[p. 148]
- Bolzani,
L.
-
Enabling Concurrent Clock and Power Gating in an Industrial Design Flow
[p. 334]
- Bombieri,
N.
-
Functional Qualification of TLM Verification
[p. 190]
-
Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches
[p. 1500]
- Bonhomme,
Y.
-
System-Level Hardware-Based Protection of Memories against Soft-Errors
[p. 1222]
- Bonnaud,
P.-H.
-
Cross-Coupling in 65nm Fully Integrated EDGE System on Chip - Design and Cross-Coupling
Prevention of Complex 65nm SoC
[p. 1045]
- Bononi,
L.
-
aEqualized: A Novel Routing Algorithm for the Spidergon Network on Chip
[p. 749]
- Bonzini,
P.
-
Heterogeneous Coarse-Grained Processing Elements: A Template Architecture for Embedded
Processing Acceleration
[p. 542]
- Boonen,
M.
-
Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0
[p. 316]
- Borde,
E.
-
Mode-Based Reconfiguration of Critical Software Component Architectures
[p. 1160]
- Bouchhima,
A.
-
Extending IP-XACT to Support an MDE Based Approach For SoC Design
[p. 586]
- Bougard,
B.
-
Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform
Dimensioning
[p. 312]
-
Finite Precision Processing in Wireless Applications
[p. 1230]
-
Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application
Specific Instruction Set Processors
[p. 1608]
- Boutillon,
E.
-
Optimizing Data Flow Graphs to Minimize Hardware Implementation
[p. 117]
- Bouzaida,
L.
-
Efficient and Accurate Method for Intra-gate Defect Diagnoses in Nanometer Technology and
Volume Data
[p. 988]
- Bozorgzadeh,
E.
-
SEU-Aware Resource Binding for Modular Redundancy Based Designs on FPGAs
[p. 1124]
- Brama,
R.
-
A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard
[p. 364]
- Braunes,
J.
-
Generating the Trace Qualification Configuration for MCDS from a High Level Language
[p. 1560]
- Braunsteine,
C.
-
Increasing the Accuracy of SAT-Based Debugging
[p. 1326]
- Brayton,
R.
-
Speculative Reduction-Based Scalable Redundancy Identification
[p. 1674]
- Brayton,
R.K.
-
Sequential Logic Rectifications with Approximate SPFDs
[p. 1698]
- Bringmann,
O.
-
White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling
[p. 513]
- Brockmeyer,
E.
-
Exploring Parallelizations of Applications for MPSoC Platforms Using MPA
[p. 1148]
- Brooks,
D.
-
An Event-Guided Approach to Reducing Voltage Noise in Processors
[p. 160]
- Bruce,
A.
-
Flow Regulation for On-Chip Communication
[p. 578]
- Bruneel,
K.
-
Automatically Mapping Applications to a Self-Reconfiguring Platform
[p. 964]
- Burdett,
A.
-
Health-Care Electronics: The Market, the Challenges, the Progress
[p. 1030]
- Burleson,
W.
-
A Monitor Interconnect and Support Subsystem for Multicore Processors
[p. 761]
- Cabodi,
G.
-
Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints
[p. 1686]
- Cai,
Y.
-
An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models
[p. 1190]
- Calazans,
N.
-
Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA
[p. 634]
- Calimera,
A.
-
Enabling Concurrent Clock and Power Gating in an Industrial Design Flow
[p. 334]
- Calvez,
A.
-
Statistical Fault Injection: Quantified Error and Confidence
[p. 502]
- Campagnolo,
R.
-
Health-Care Electronics: The Market, the Challenges, the Progress
[p. 1030]
- Camurati,
P.
-
Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints
[p. 1686]
- Cao,
Y.
-
Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization
[p. 328]
- Carbognani,
F.
-
Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT
[p. 646]
- Carloni,
L.P.
-
A Case Study in Distributed Deployment of Embedded Software for Camera Networks
[p. 1006]
- Carlson,
T.
-
System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications
[p. 923]
- Cartron,
M.
-
System-Level Hardware-Based Protection of Memories against Soft-Errors
[p. 1222]
- Casteres,
J.
-
Aircraft Integration Real-Time Simulator Modeling with AADL for Architecture Tradeoffs
[p. 346]
- Castro-Lopez,
R.
-
Analog Layout Synthesis - Recent Advances in Topological Approaches
[p. 274]
- Catthoor,
F.
-
Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform
Dimensioning
[p. 312]
-
System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications
[p. 923]
-
Finite Precision Processing in Wireless Applications
[p. 1230]
-
Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application
Specific Instruction Set Processors
[p. 1608]
- Cervin,
A.
-
Integrated Scheduling and Synthesis of Control Applications on Distributed Embedded Systems
[p. 57]
- Chakrabarty,
K.
-
Generation of Compact Test Sets with High Defect Coverage
[p. 1130]
-
Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips
[p. 1290]
-
Seed Selection in LFSR-Reseeding-Based Test Compression for the Detection of Small-Delay Defects
[p. 1488]
- Chakraborty,
A.
-
Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees
[p. 296]
- Chambers,
B.
-
Faster SAT Solving with Better CNF Generation
[p. 1590]
- Chandra,
A.
-
Scalable Adaptive Scan (SAS)
[p. 1476]
- Chandra,
V.
-
Impact of Voltage Scaling on Nanoscale SRAM Reliability
[p. 387]
- Chang,
K.-H.
-
Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't Cares
[p. 582]
- Chang,
S.-W.
-
pTest: An Adaptive Testing Tool for Concurrent Software on Embedded Multicore Processors
[p. 1012]
- Chang,
Y.-H.
-
A File-System-Aware FTL Design for Flash-Memory Storage Systems
[p. 393]
-
A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement
[p. 405]
- Chang,
Y.-W.
-
Analog Layout Synthesis - Recent Advances in Topological Approaches
[p. 274]
- Charot,
F.
-
A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications
[p. 1242]
- Chatha,
K.
-
Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints
[p. 1548]
- Chatterjee,
A.
-
A Novel Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles
[p. 1656]
- Chatterjee,
D.
-
GCS: High-Performance Gate-Level Simulation with GP-GPUs
[p. 1332]
- Che,
J.-J.
-
An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous
Multiprocessor Systems
[p. 694]
- Chen,
D.
-
Reconfigurable Circuit Design with Nanomaterials
[p. 442]
- Chen,
F.-W.
-
Performance-Driven Dual-Rail Insertion for Chip-Level Pre-Fabricated Design
[p. 308]
- Chen,
G.
-
A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs
[p. 21]
- Chen,
H.-M.
-
Package Routability-and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design
[p. 845]
- Chen,
N.
-
On Hierarchical Statistical Static Timing Analysis
[p. 1320]
- Chen,
Q.
-
New Simulation Methodology of 3D Surface Roughness Loss for Interconnects Modeling
[p. 1184]
- Chen,
X.
-
Reliability Aware through Silicon Via Planning for 3D Stacked ICs
[p. 288]
-
Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization
[p. 328]
-
Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing
[p. 1530]
- Chen,
Y.
-
An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures
[p. 731]
- Cheng,
C.-K.
-
Reliability Aware through Silicon Via Planning for 3D Stacked ICs
[p. 288]
-
Parallel Transistor Level Full-Chip Circuit Simulation
[p. 304]
- Cheng,
W.-T.
-
Improving Compressed Test Pattern Generation for Multiple Scan Chain Failure Diagnosis
[p. 1000]
- Cheung,
P.
-
Partition-Based Exploration for Reconfigurable JPEG Designs
[p. 886]
- Chiang,
M.-F.
-
Register Placement for High-Performance Circuits
[p. 1470]
- Chilstedt,
S.
-
Reconfigurable Circuit Design with Nanomaterials
[p. 442]
- Cho,
H.
-
KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems
[p. 507]
- Choi,
G.
-
Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO System
[p. 870]
- Chou,
C.-L.
-
User-Centric Design Space Exploration for Heterogeneous Network-on-Chip Platforms
[p. 15]
- Choudhuri,
S.
-
FSAF: File System Aware Flash Translation Layer for NAND Flash Memories
[p. 399]
- Choudhury,
M.R.
-
Masking Timing Errors on Speed-Paths In Logic Circuits
[p. 87]
- Chrysos,
G.
-
Design and Implementation of a Database Filter for BLAST Acceleration
[p. 166]
- Chu,
Y.-S.
-
A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement
[p. 405]
- Chung,
S. W.
-
Exploiting Narrow-Width Values for Thermal-Aware Register File Designs
[p. 1422]
- Ciesielski,
M.
-
Optimizing Data Flow Graphs to Minimize Hardware Implementation
[p. 117]
- Cilardo,
A.
-
A New Speculative Addition Architecture Suitable for Two's Complement Operations
[p. 664]
- Ciriani,
V.
-
On Decomposing Boolean Functions via Extended Cofactoring
[p. 1464]
- Ciuprina,
G.
-
On the Efficient Reduction of Complete EM Based Parametric Models
[p. 1172]
- Clermidy,
F.
-
Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC
[p. 1564]
- Cockburn,
B.F.
-
A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development
and Verification
[p. 45]
- Comparetti,
M.
-
A Power-Efficient Migration Mechanism for D-NUCA Caches
[p. 598]
- Concer,
N.
-
aEqualized: A Novel Routing Algorithm for the Spidergon Network on Chip
[p. 749]
- Cong,
J.
-
Energy Efficient Multiprocessor Task Scheduling under Input-Dependent Variation
[p. 411]
- Corporaal,
H.
-
Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0
[p. 316]
- Cortadella,
J.
-
Variable-Latency Design by Function Speculation
[p. 1704]
- Cosemans,
S.
-
A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D
Interconnect Context
[p. 929]
- Coskun,
A.K.
-
Dynamic Thermal Management in 3D Multicore Architectures
[p. 1410]
- Costa,
J.C.
-
A MILP-Based Approach to Path Sensitization of Embedded Software
[p. 1568]
- Courcambec,
S.
-
SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection
[p. 570]
- Craninkx,
J.
-
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Optimizing Data Flow Graphs to Minimize Hardware Implementation
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Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints
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Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms
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Componentizing Hardware/Software Interface Design
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Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms
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Incorporating Graceful Degradation into Embedded System Design
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Combined System Synthesis and Communication Architecture Exploration for MPSoCs
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Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing
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Gate Sizing for Large Cell-Based Designs
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