DATE Executive Committee

DATE Sponsor Committee

Technical Program Chairs

Technical Program Committee

Reviewers

Foreword

Best Paper Awards

Tutorials

PH.D. Forum

Call for Papers: DATE 2010

- Has Anything Changed in Electronic Design Since 1983? [p. 1]
*M. Muller*- Embedded Systems Design - Scientific Challenges and Work Directions [p. 2]
*J. Sifakis*

- A Low-Power Fat Tree-Based Optical Network-on-Chip for Multiprocessor System-on-Chip [p. 3]
*H. Gu, J. Xu and W. Zhang*- SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips [p. 9]
*C. Seiculescu, S. Murali, L. Benini and G De Micheli*- User-Centric Design Space Exploration for Heterogeneous Network-on-Chip Platforms [p. 15]
*C.-L. Chou and R. Marculescu*- A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs [p. 21]
*D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester and D. Blaauw*

- Mapping of a Film Grain Removal Algorithm to a Heterogeneous Reconfigurable Architecture [p. 27]
*S. Whitty, H. Sahlbach, R. Ernst and W. Putzke-Roeming*- An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures [p. 33]
*Y. Yi, W. Han, X. Zhao, A.T. Erdogan and T. Arslan*- DPR in High Energy Physics [p. 39]
*W. Gao, A. Kugel, R. Maenner, N. Abel, N. Meier and U. Kebschull*- A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development and Verification [p. 45]
*A. Alimohammad, S. Fouladi Fard and B.F. Cockburn*

- Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms [p. 51]
*L. Huang, F. Yuan and Q. Xu*- Integrated Scheduling and Synthesis of Control Applications on Distributed Embedded Systems [p. 57]
*S. Samii, P. Eles, Z. Peng and A. Cervin*- Towards No-Cost Adaptive MPSoC Static Schedules through Exploitation of Logical-to-Physical Core Mapping Latitude [p. 63]
*C. Yang and A. Orailoglu*- Pipelined Data Parallel Task Mapping/Scheduling Technique for MPSoC [p. 69]
*H. Yang and S. Ha*

- Joint Logic Restructuring and Pin Reordering against NBTI-Induced Performance Degradation [p. 75]
*K.-C. Wu and D. Marculescu*- A Self-Adaptive System Architecture to Address Transistor Aging [p. 81]
*O. Khan and S. Kundu*- Masking Timing Errors on Speed-Paths In Logic Circuits [p. 87]
*M.R. Choudhury and K. Mohanram*

- WCRT Algebra and Interfaces for Esterel-Style Synchronous Processing [p. 93]
*M. Mendler, R. von Hanxleden and C. Traulsen*- Reliable Mode Changes in Real-Time Systems with Fixed Priority or EDF Scheduling [p. 99]
*N. Stoimenov, S. Perathoner and L. Thiele*- Improved Worst-Case Response-Time Calculations by Upper-Bound Conditions [p. 105]
*V. Pollex, S. Kollman, K. Albers and F. Slomka*- A Generalized Scheduling Approach for Dynamic Dataflow Applications [p. 111]
*W. Plishker, N. Sane and S.S. Bhattacharyya*

- Optimizing Data Flow Graphs to Minimize Hardware Implementation [p. 117]
*D. Gomez-Prado, Q. Ren, M. Ciesielski, J. Guillot and E. Boutillon*- Multi-Clock SOC Design Using Protocol Conversion [p. 123]
*R. Sinha, P.S. Roop, Z. Salcic and S. Basu*- A Formal Approach to Design Space Exploration of Protocol Converters [p. 129]
*K. Avnit and A. Sowmya*- Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms [p. 135]
*J. Keinert, H. Dutta, F. Hannig, C. Haubelt and J. Teich*

Moderator: G. De Micheli, EPFL, CH

*
Panelists: A. Domic, M. Montalti, M. Muller, J. Sawicki
*

- Variation Resilient Adaptive Controller for Subthreshold Circuits [p. 142]
*B. Mishra, B.M. Al-Hashimi and M. Zwolinski*- Minimization of NBTI Performance Degradation Using Internal Node Control [p. 148]
*D.R Bild, G.E. Bok and R.P. Dick*- Physically Clustered Forward Body Biasing for Variability Compensation in Nano-Meter CMOS Design [p. 154]
*A. Sathanur, A. Pullini, G. De Micheli, L. Benini and E. Macii*- An Event-Guided Approach to Reducing Voltage Noise in Processors [p. 160]
*M.S Gupta, V.J Reddi, G. Holloway, G.-Y. Wei and D. Brooks*

- Design and Implementation of a Database Filter for BLAST Acceleration [p. 166]
*P. Afratis, C. Galanakis, E. Sotiriades, G.-G. Mplemenos, G. Chrysos, I. Papaefstathiou and D. Pnevmatikatos*- A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs [p. 172]
*K. Siozios, V.F. Pavlidis and D. Soudris*- Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems [p. 178]
*O. Sander, B. Glas, C. Roth, J. Becker and K.D. Mueller-Glaser*- Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor [p. 184]
*S.Z. Ahmed, J. Eydoux, L. Rouge, J.-P. Cuelle, G. Sassatelli and L. Torres*

- Functional Qualification of TLM Verification [p. 190]
*N. Bombieri, F. Fummi, G. Pravadelli, M. Hampton and F. Letombe*- Solver Technology for System-level to RTL Equivalence Checking [p. 196]
*A. Koelbl, R. Jacoby, H. Jain and C. Pixley*

- A High-Level Debug Environment for Communication-Centric Debug [p. 202]
*K. Goossens, B. Vermeulen and A.B. Nejad*- Cache Aware Compression for Processor Debug Support [p. 208]
*A. Vishnoi, P.R. Panda and M. Balakrishnan*- Fault Insertion Testing of a Novel CPLD-Based Fail-Safe System [p. 214]
*G. Griessnig, R. Mader, C. Steger and R. Weiss*- Test Architecture Design and Optimization for Three-Dimensional SoCs [p. 220]
*L. Jiang, L. Huang and Q. Xu*

- A Co-Design Approach for Embedded System Modeling and Code Generation with UML and MARTE [p. 226]
*J. Vidal, F. de Lamotte, G. Gogniat, P. Soulard and J.-P. Diguet*- Componentizing Hardware/Software Interface Design [p. 232]
*K. Hao and F. Xie*- A UML Frontend for IP-XACT-Based IP Management [p. 238]
*T. Schattkowsky, T. Xie and W. Mueller*- Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA [p. 244]
*T. Arpinen, T. Koskinen, E. Salminen, T.D. Hamalainen and M. Hannikainen*

- aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services [p. 250]
*A. Hansson, M. Subburaman and K. Goossens*- Configurable Links for Runtime Adaptive On-Chip Communication [p. 256]
*M.A. Al Faruque, T. Ebi and J. Henkel*- Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces [p. 262]
*I. Loi, F. Angiolini and L. Benini*- SCORES: A Scalable and Parametric Streams-Based Communication Architecture for Modular Reconfigurable Systems [p. 268]
*A. Jara-Berrocal and A. Gordon-Ross*

*
Panelists: J. Cessna, G. Goelz, V. Meyer zu Bexten and E. Petrus
*

- Analog Layout Synthesis - Recent Advances in Topological Approaches [p. 274]
*H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F.V. Fernandez, P.-H. Lin and M. Strasser*

- An Accurate Interconnect Thermal Model Using Equivalent Transmission Line Circuit [p. 280]
*B. Wang and P. Mazumder*- Analogue Mixed Signal Simulation Using Spice and SystemC [p. 284]
*T. Kirchner, N. Bannow and C. Grimm*- Reliability Aware through Silicon Via Planning for 3D Stacked ICs [p. 288]
*A. Shayan, X. Hu, H. Peng, C.-K. Cheng, W. Yu, M. Popovich, T. Toms and X. Chen*- A Study on Placement of Post Silicon Clock Tuning Buffers for Mitigating Impact of Process Variation [p. 292]
*K. Nagaraj and S. Kundu*- Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees [p. 296]
*A. Chakraborty, G. Ganesan, A. Rajaram and D.Z. Pan*- Bitstream Relocation with Local Clock Domains for Partially Reconfigurable FPGAs [p. 300]
*A. Flynn, A. Gordon-Ross and A.D. George*- Parallel Transistor Level Full-Chip Circuit Simulation [p. 304]
*H. Peng and C.-K. Cheng*- Performance-Driven Dual-Rail Insertion for Chip-Level Pre-Fabricated Design [p. 308]
*F.-W. Chen and Y.-Y. Liu*- Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning [p. 312]
*M. Trautmann, S. Mamagkakis, B. Bougard, J. Declerck, E. Umans, A. Dejonghe, L. Van der Perre and F. Catthoor*- Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0 [p. 316]
*B. van Moll, H. Corporaal, V. Reyes and M. Boonen*- Incorporating Graceful Degradation into Embedded System Design [p. 320]
*M. Glass, M. Lukasiewycz, C. Haubelt and J. Teich*- Rewiring Using IRredundancy Removal and Addition [p. 324]
*C.-C. Lin and C.-Y. Wang*

- Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization [p. 328]
*Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie and H. Yang*- Enabling Concurrent Clock and Power Gating in an Industrial Design Flow [p. 334]
*L. Bolzani, A. Calimera, A. Macii, E. Macii and M. Poncino*- TRAM: A Tool for Temperature and Reliability Aware Memory Design [p. 340]
*A. Khajeh, A. Gupta, N. Dutt, F. Kurdahi, A. Eltawil, K. Khouri and M. Abadir*

- Aircraft Integration Real-Time Simulator Modeling with AADL for Architecture Tradeoffs [p. 346]
*J. Casteres and T. Ramaherirariny*- A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable Chips [p. 352]
*M. Sonza Reorda, M. Violante, C. Meinhardt and R. Reis*- Communication Minimization for In-Network Processing in Body Sensor Networks: A Buffer Assignment Technique [p. 358]
*H. Ghasemzadeh, N. Jain, M. Sgroi and R. Jafari*- A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard [p. 364]
*L. Larcher, R. Brama, M. Ganzerli, J. Iannacci, M. Bedani and A. Gnudi*- Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing [p. 369]
*J.A. Díaz-Madrid, H. Neubauer, H. Hauer, G. Doménech-Asensi and R. Ruiz-Merino*

Moderator: J. Cong, UCLA, US

*
Panelists: J. Cong, G. Clave, T. Makelainen, Z. Zhang, V. Kathail and J. Kunkel
*

- Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications [p. 375]
*S. Reda and S. Nassif*- On Linewidth-Based Yield Analysis for Nanometer Lithography [p. 381]
*A. Sreedhar and S. Kundu*- Impact of Voltage Scaling on Nanoscale SRAM Reliability [p. 387]
*V. Chandra and R. Aitken*

- A File-System-Aware FTL Design for Flash-Memory Storage Systems [p. 393]
*P.-L. Wu, Y.-H. Chang and T.-W. Kuo*- FSAF: File System Aware Flash Translation Layer for NAND Flash Memories [p. 399]
*S.K. Mylavarapu, S. Choudhuri, A. Shrivastava, J. Lee and A. Givargis*- A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement [p. 405]
*Y.-S. Chu, J.-W. Hsieh, Y.-H. Chang and T.-W. Kuo*

- Energy Efficient Multiprocessor Task Scheduling under Input-Dependent Variation [p. 411]
*J. Cong and K. Gururaj*- Program Phase and Runtime Distribution-Aware Online DVFS for Combined Vdd/Vbb Scaling [p. 417]
*J. Kim, S. Yoo and C.-M. Kyung*- ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration [p. 423]
*A.B. Kahng, B. Li, L.-S. Peh and K. Samadi*

Moderator: S. Mehta, Sun Microsystems, US

*
Panelists: J. Abraham, R. Goldman and J. McLean
*

Moderator: G. Smith, US

- Nano-electronics Challenge - Chip Designers Meet Real Nano-Electronics in 2010s? [p. 431]
*S. Fujita*- MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues [p. 433]
*S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, T. Endoh, H. Ohno and T. Hanyu*- Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect Ttransistors [p. 436]
*S. Mitra, J. Zhang, N. Patil and H. Wei*- Reconfigurable Circuit Design with Nanomaterials [p. 442]
*C. Dong, S. Chilstedt and D. Chen*

- An Architecture for Secure Software Defined Radio [p. 448]
*C. Li, A. Raghunathan and N.K. Jha*- Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage [p. 454]
*X. Guo and P. Schaumont*- Hardware Aging-Based Software Metering [p. 460]
*F. Dabiri and M. Potkonjak*

- On-Chip Communication Architecture Exploration for Processor-Pool-Based MPSoC [p. 466]
*Y.-P. Joo, S. Kim and S. Ha*- Combined System Synthesis and Communication Architecture Exploration for MPSoCs [p. 472]
*M. Lukasiewycz, M. Streubuehr, M. Glass, C. Haubelt and J. Teich*- UMTS MPSoC Design Evaluation Using a System Level Design Framework [p. 478]
*D. Densmore, A. Simalatsar, A. Davare, R. Passerone and A. Sangiovanni-Vincentelli*

- Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips [p. 484]
*M. Vayrynen, V. Singh and E. Larsson*- Improving Yield and Reliability of Chip Multiprocessors [p. 490]
*A. Pan, O. Khan and S. Kundu*- A Unified Online Fault Detection Scheme Via Checking of Stability Violation [p. 496]
*G. Yan, Y. Han and X. Li*- Statistical Fault Injection: Quantified Error and Confidence [p. 502]
*R. Leveugle, A. Calvez, P. Maistri and P. Vanhauwaert*

- KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems [p. 507]
*H. Cho, D. Shin and Y.I. Eom*- White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling [p. 513]
*A. Viehl, M. Pressler, O. Bringmann and W. Rosenstiel*- Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems [p. 519]
*F. Koenig, D. Boers, F. Slomka, U. Margull, M. Niemetz and G. Wirrer*- Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources [p. 524]
*M. Negrean, S. Schliecker and R. Ernst*

- Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap [p. 530]
*D. Suarez, T. Monreal, F. Vallejo, R. Beivide and V. Vinals*- ReSiM, A Trace-Driven, Reconfigurable ILP Processor Simulator [p. 536]
*S. Fytraki and D. Pnevmatikatos*- Heterogeneous Coarse-Grained Processing Elements: A Template Architecture for Embedded Processing Acceleration [p. 542]
*G. Ansaloni, P. Bonzini and L. Pozzi*- Algorithms for the Automatic Extension of an Instruction-Set [p. 548]
*C. Galuzzi, D. Theodoropoulos, R. Meeuws and K. Bertels*

- Dimensioning Heterogeneous MPSoCs via Parallelism Analysis [p. 554]
*B. Ristau, T. Limberg, O. Arnold and G. Fettweis*- MPSoCs Run-Time Monitoring through Networks-on-Chip [p. 558]
*L. Fiorin, G. Palermo and C. Silvano*- Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints [p. 562]
*D. Ludovici, F. Gilabert, S. Medardoni, C. Gomez, M.E. Gomez, P. Lopez, G. Gaydadjiev and D. Bertozzi*- A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM [p. 566]
*M. Modarressi, H. Sarbazi-Azad and M. Arjomand*- SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection [p. 570]
*L. Su, S. Courcambec, P. Guillemin, C. Schwarz and R. Pacalet*- A Link Arbitration Scheme for Quality of Service in a Latency-Optimized Network-on-Chip [p. 574]
*J. Diemer and R. Ernst*- Flow Regulation for On-Chip Communication [p. 578]
*Z. Lu, M. Millberg, A. Jantsch, A. Bruce, P. van Der Wolf and T. Henriksson*- Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't Cares [p. 582]
*K.-H. Chang, V. Bertacco and I.L. Markov*- Extending IP-XACT to Support an MDE Based Approach For SoC Design [p. 586]
*A. El Mrabti, F. Petrot and A. Bouchhima*- Overcoming Limitations of the SystemC Data Introspection [p. 590]
*C. Genz and R. Drechsler*- Selective Light Vth Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power Reduction [p. 594]
*H. Xu, R. Vemuri and W.-B. Jone*- A Power-Efficient Migration Mechanism for D-NUCA Caches [p. 598]
*A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli and C.A. Prete*

Moderator: P. Aycinena, US

*
Panelists: A. Aznar, J.-A. Carballo, R. Madhavan, M. Merced, A. Shubat and R. Yavatkar
*

- Trends and Challenges in Wireless Application Processors [p. 603]
*P. Garnier*

- System-Level Process Variability Analysis and Mitigation for 3D MPSoCs [p. 604]
*S. Garg and D. Marculescu*- Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs [p. 610]
*Y.-J. Lee, Y.-J. Kim, G. Huang, M. Bakir, Y. Joshi, A. Fedorov and S.K. Lim*- Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis [p. 616]
*S. Bobba, J. Zhang, A. Pullini, D. Atienza and G. De Micheli*- Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis [p. 622]
*M.H. Ben Jamaa, K. Mohanram and G. De Micheli*

- Enhancing Correlation Electro-Magnetic Attack Using Planar Near-Field Cartography [p. 628]
*D. Real, F. Valette and M. Drissi*- Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA [p. 634]
*V. Lomne, P. Maurine, L. Torres, M. Robert, R. Soares and N. Calazans*- Successful Attack of an FPGA-Based WDDL DES Cryptoprocessor without Place and Route Constraints [p. 640]
*L. Sauvage, S. Guilley, J.-L. Danger, Y. Mathieu and M. Nassar*- Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT [p. 646]
*L. Henzen, F. Carbognani, N. Felber and W. Fichtner*

- Architectural Support for Low Overhead Detection of Memory Violations [p. 652]
*S. Ghose, L. Gilgeous, P. Dudnik, A. Aggarwal and C. Waxman*- CASPAR: Hardware Patching for Multi-Core Processors [p. 658]
*I. Wagner and V. Bertacco*- A New Speculative Addition Architecture Suitable for Two's Complement Operations [p. 664]
*A. Cilardo*- Limiting the Number of Dirty Cache Lines [p. 670]
*P. De Langen and B. Juurlink*

- Contactless Testing: Possibility or Pipe-Dream? [p. 676]
*E.J. Marinissen, D.Y. Lee, J.P. Hayes, C. Sellathamby, B. Moore, S. Slupsky and L. Pujol*

- Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors [p. 682]
*V. Izosimov, I. Polian, P. Pop, P. Eles and Z. Peng*- On Bounding Response Times under Software Transactional Memory in Distributed Multiprocessor Real-Time Systems [p. 688]
*S.F. Fahmy, B. Ravindran and E.D. Jensen*- An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous Multiprocessor Systems [p. 694]
*C.-Y. Yang, J.-J. Che, T.-W. Kuo and L. Thiele*

- A Graph Grammar Based Approach to Automated Multi-Objective Analog Circuit Design [p. 700]
*A. Das and R. Vemuri*- Massively Multi-Topology Sizing of Analog Integrated Circuits [p. 706]
*P. Palmers, T. McConnaghy, M. Steyaert and G. Gielen*- Improved Performance and Variation Modelling for Hierarchical-Based Optimisation of Analogue Integrated Circuits [p. 712]
*S. Ali, L. Ke, R. Wilcock and P. Wilson*- Computation of IP3 Using Single-Tone Moments Analysis [p. 718]
*D. Tannir and R. Khazaka*

- Formal Approaches to Analog Circuit Verification [p. 724]
*E. Barke, D. Grabowski, H. Graeb, L. Hedrich, S. Heinen, R. Popp, S. Steinhorst and Y. Wang*

Moderator: W. Rhines, Mentor Graphics, US

- An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures [p. 731]
*H. Li and Y. Chen*- Power and Performance of Read-Write Aware Hybrid Caches with Non-volatile Memories [p. 737]
*X. Wu, J. Li, L. Zhang, E. Speight and Y. Xie*- Using Non-Volatile Memory to Save Energy in Servers [p. 743]
*D. Roberts, T. Kgil and T. Mudge*

- aEqualized: A Novel Routing Algorithm for the Spidergon Network on Chip [p. 749]
*N. Concer, S. Iamundo and L. Bononi*- Group-Caching for NoC Based Multicore Cache Coherent Systems [p. 755]
*W. Zuo, S. Feng, Z. Qi, J. Weixing, L. Jiaxin, D. Ning, X. Licheng, T. Yuan and Q. Baojun*- A Monitor Interconnect and Support Subsystem for Multicore Processors [p. 761]
*S. Madduri, R. Vadlamani, W. Burleson and R. Tessier*

- A Real-Time Application Design Methodology for MPSoCs [p. 767]
*G. Beltrame, L. Fossati and D. Sciuto*- Adaptive Prefetching for Shared Cache Based Chip Multiprocessors [p. 773]
*M. Kandemir, Y. Zhang and O. Ozturk*- CUFFS: An Instruction Count Based Architectural Framework for Security of MPSoCs [p. 779]
*K. Patel, S. Parameswaran and R. Ragel*

- Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits [p. 785]
*D. Holcomb, W. Li and S.A. Seshia*- Detecting Errors Using Multi-Cycle Invariance Information [p. 791]
*N. Alves, K. Nepal, J. Dworak and R.I. Bahar*- A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow [p. 797]
*P. Lu, D. Glaser, G. Uygur and K. Helmreich*

- Gate Sizing for Large Cell-Based Designs [p. 827]
*S. Held*- Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network [p. 833]
*N. MohammadZadeh, M. Mirsaeedi, A. Jahanian and M.S. Zamani*- Decoupling Capacitor Planning with Analytical Delay Model on RLC Power Grid [p. 839]
*Y. Tao and S.K. Lim*- Package Routability-and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design [p. 845]
*C.-H. Lu, H.-M. Chen, C.-N. J. Liu and W.-Y. Shih*

Moderator: M. di Natale, Scuola S Anna, IT

- Learning Early-Stage Platform Dimensioning from Late-Stage Timing Verification [p. 851]
*K. Richter, M. Jersak and R. Ernst*- The Influence of Real-time Constraints on the Design of FlexRay-based Systems [p. 858]
*S. Reichelt, O. Scheickl and G. Tabanoglu*- Time and Memory Tradeoffs in the Implementation of AUTOSAR Components [p. 864]
*A. Ferrari, M. Di Natale, G. Gentile and P. Gai*

- Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO System [p. 870]
*P. Bhagawat, R. Dash and G. Choi*- Co-Simulation Based Platform for Wireless Protocols Design Explorations [p. 874]
*A. Fourmique, B. Girodias, G. Nicolescu and E.M. Aboulhamid*- How To Speed-Up Your NLFSR-Based Stream Cipher [p. 878]
*E. Dubrova*- A High Performance Reconfigurable Motion Estimation Hardware Architecture [p. 882]
*O. Tasdizen, H. Kukner, A. Akin and I. Hamzaoglu*- Partition-Based Exploration for Reconfigurable JPEG Designs [p. 886]
*P.G Potter, W. Luk and P. Cheung*- Automated Synthesis of Streaming C Applications to Process Networks In Hardware [p. 890]
*S. van Haastregt and B. Kienhuis*- Distributed Sensor For Steering Wheel Grip Force Measurement In Driver Fatigue Detection [p. 894]
*F. Baronti, F. Lenzi, R. Roncella and R. Saletti*- Making DNA Self-Assembly Error-Proof: Attaining Small Growth Error Rates through Embedded Information Redundancy [p. 898]
*S. Garcia and A. Orailoglu*- Machine Learning-Based Volume Diagnosis [p. 902]
*S. Wang and W. Wei*- Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in Multiprocessor Systems-on-Chip [p. 906]
*F. Paterna, L. Benini, A. Acquaviva, F. Papariello, G. Desoli and M. Olivieri*

Moderator: E. Schubert, ESIC GmbH, DES

*
Panelists: A. Jantsch, P. Urard, F. Schirrmeister, P. Mosterman, L. Le-Toumelin and C. Engblom
*

- Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling [p. 911]
*A. Sasan (M.A. Makhzan), H. Homayoun, A. Eltawil and F. Kurdahi*- Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems [p. 917]
*J. Singh, D.K. Pradhan, S. Hollis, S.P. Mohanty and J. Mathew*- System-Level Power/Performance Evaluation of 3D Stacked Drams for Mobile Applications [p. 923]
*M. Facchini, T. Carlson, A. Vignon, M. Palcovic, F. Catthoor, W. Dehaene, L. Benini and P. Marchal*- A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context [p. 929]
*A. Vignon, S. Cosemans, W. Dehaene, P. Marchal and M. Facchini*

- A Case for Multi-Channel Memories in Video Recording [p. 934]
*E. Aho, J. Nikara, P.A. Tuominen and K. Kuusilinna*- High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation [p. 940]
*H.K. Zrida, A. Jemai, A.C. Ammari and M. Abid*- Temperature-Aware Scheduler Based on Thermal Behavior Grouping in Multicore Systems [p. 946]
*I. Yeo and E.J. Kim*- Hardware/Software Co-design Architecture for Thermal Management of Chip Multiprocessors [p. 952]
*O. Khan and S. Kundu*

- Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors [p. 958]
*L. Bauer, M. Shafique and J. Henkel*- Automatically Mapping Applications to a Self-Reconfiguring Platform [p. 964]
*K. Bruneel, F. Abouelella and D. Stroobandt*- OSSS+R: A Framework for Application Level Modelling and Synthesis of Reconfigurable Systems [p. 970]
*A. Schallenberg, W. Nebel, A. Herrholz, P.A. Hartmann and F. Oppenheimer*- Design Optimizations to Improve Placeability of Partial Reconfiguration Modules [p. 976]
*M. Koester, W. Luk, J. Hagemeyer and M. Porrmann*

- Automated Data Analysis Solutions to Silicon Debug [p. 982]
*Y.-S. Yang, N. Nicolici and A. Veneris*- Efficient and Accurate Method for Intra-gate Defect Diagnoses in Nanometer Technology and Volume Data [p. 988]
*A. Ladhar, M. Masmoudi and L. Bouzaida*- Selection of a Fault Model for Fault Diagnosis Based on Unique Responses [p. 994]
*I. Pomeranz and S.M. Reddy*- Improving Compressed Test Pattern Generation for Multiple Scan Chain Failure Diagnosis [p. 1000]
*X. Tang, R. Guo, W.-T. Cheng and S.M. Reddy*

- A Case Study in Distributed Deployment of Embedded Software for Camera Networks [p. 1006]
*F. Leonardi, A. Pinto and L.P. Carloni*- pTest: An Adaptive Testing Tool for Concurrent Software on Embedded Multicore Processors [p. 1012]
*S.-W. Chang, K.-Y. Hsieh and J.K. Lee*- A Generic Platform for Estimation of Multi-Threaded Program Performance on Heterogeneous Multiprocessor [p. 1018]
*A. Sahu, M. Balakrishnan and P.R. Panda*- Networked Embedded System Applications Design Driven by an Middleware Environment [p. 1024]
*F. Fummi, G. Perbellini and N. Roncolato*

- Health-Care Electronics: The Market, the Challenges, the Progress [p. 1030]
*W. Eberle, A.S. Mecheri, T.K. T. Nguyen, G. Gielen, R. Campagnolo, A. Burdett, C. Toumazou and B. Volckaerts*

- Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor [p. 1035]
*T. Kodaka, S. Sasaki, T. Tokuyoshi, R. Ohyama, N. Nonogaki, K. Kitayama, T. Mori, Y. Ueda, H. Arakida, Y. Okuda, T. Kizu, Y. Tsuboi and N. Matsumoto*- High Data Rate Fully Flexible SDR Modem [p. 1040]
*F. Kasperski, O. Pierrelee, F. Dotto and M. Sarlotte*- Cross-Coupling in 65nm Fully Integrated EDGE System on Chip - Design and Cross-Coupling Prevention of Complex 65nm SoC [p. 1045]
*P.-H. Bonnaud and G. Sommer*

Moderators: G. Nicolescu, Polytechnique Montreal, CA; A. Jerraya, CEA-LETI, FR

- Latency Criticality Aware On-Chip Communication [p. 1052]
*Z. Li, J. Wu, L. Shang, R.P. Dick and Y. Sun*- In-Network Reorder Buffer to Improve Overall NoC Performance While Resolving the In-Order Requirement Problem [p. 1058]
*W.-C. Kwon, S. Yoo, J. Um and S.-W. Jeong*- An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs [p. 1064]
*M. Ebrahimi, M. Daneshtalab, M.H. Neishaburi, S. Mohammadi, A. Afzali-Kusha, J. Plosila and H. Tenhunen*- Priority Based Forced Requeue to Reduce Worst Case Latencies for Bursty Traffic [p. 1070]
*M. Millberg and A. Jantsch*

- Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay [p. 1076]
*W. Li, M. Di Natale, W. Zheng, P. Giusto, A. Sangiovanni-Vincentelli and S.A. Seshia*- Remote Measurement of Local Oscillator Drifts in FlexRay Networks [p. 1082]
*E. Armengaud and A. Steininger*- CAN+: A New Backward-Compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates [p. 1088]
*T. Ziermann, S. Wildermann and J. Teich*- Shock Immunity Enhancement via Resonance Damping in Gyroscopes for Automotive Applications [p. 1094]
*E. Marchetti, L. Fanucci, A. Rocchi and M. De Marinis*- Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform [p. 1100]
*N. Martínez Madrid, R. Seepold, A. Reina Nieves, J. Saez Gomez, A. los Santos Aransay, P. Sanz Velasco, C. Rueda Morales and F. Ares*

- Finite Precision Bit-Width Allocation Using SAT-Modulo Theory [p. 1106]
*A.B. Kinsman and N. Nicolici*- HLS-L: High-Level Synthesis of High Performance Latch-Based Circuits [p. 1112]
*S. Paik, I. Shin and Y. Shin*- Automatic Generation of Streaming Datapaths for Arbitrary Fixed Permutations [p. 1118]
*P.A. Milder, J.C. Hoe and M. Pueschel*- SEU-Aware Resource Binding for Modular Redundancy Based Designs on FPGAs [p. 1124]
*S. Golshan and E. Bozorgzadeh*

- Generation of Compact Test Sets with High Defect Coverage [p. 1130]
*X. Kavousianos and K. Chakrabarty*- A Scalable Method for the Generation of Small Test Sets [p. 1136]
*S. Remersaro, J. Rajski, S.M. Reddy and I. Pomeranz*- QC-Fill: An X-Fill Method for Quick-and-Cool Scan Test [p. 1142]
*C.-W. Tzeng and S.-Y. Huang*

- Exploring Parallelizations of Applications for MPSoC Platforms Using MPA [p. 1148]
*R. Baert, E. Brockmeyer, S. Wuytack and T.J. Ashby*- An MDE Methodology for the Development of High-Integrity Real-Time Systems [p. 1154]
*S. Mazzini, S. Puri and T. Vardanega*- Mode-Based Reconfiguration of Critical Software Component Architectures [p. 1160]
*E. Borde, G. Haik and L. Pautet*- Towards a Formal Semantics for the AADL Behavior Annex [p. 1166]
*Z. Yang, K. Hu, D. Ma and L. Pi*

- On the Efficient Reduction of Complete EM Based Parametric Models [p. 1172]
*J. Fernandez Villena, G. Ciuprina, D. Ioan and L.M. Silveira*- Efficient Compression and Handling of Current Source Model Library Waveforms [p. 1178]
*S. Hatami, P. Feldmann, S. Abbaspour and M. Pedram*- New Simulation Methodology of 3D Surface Roughness Loss for Interconnects Modeling [p. 1184]
*Q. Chen and N. Wong*- An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models [p. 1190]
*X. Wang, Y. Cai, S. X.-D. Tan, X. Hong and J. Relles*

- An Automated Flow For Integrating Hardware IP into the Automotive Systems Engineering Process [p. 1196]
*J. Oetjens, R. Goergen, J. Gerlach and W. Nebel*- Model Based Design Needs High Level Synthesis [p. 1202]
*S. Perry*- EMC-Aware Design on a Microcontroller for Automotive Applications [p. 1208]
*P.J. Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi and D. Pandini*

- Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software [p. 1214]
*D. Lettnin, P.K. Nalla, J. Behrend, J. Ruf, J. Gerlach, T. Kropf, W. Rosenstiel, V. Schoenknecht and S. Reitemeyer*- On the Relationship between Stuck-At Fault Coverage and Transition Fault Coverage [p. 1218]
*J. Schat*- System-Level Hardware-Based Protection of Memories against Soft-Errors [p. 1222]
*V. Gherman, S. Evain, M. Cartron, N. Seymour and Y. Bonhomme*- A Study of the Single Event Effects Impact on Functional Mapping within Flash-Based FPGAs [p. 1226]
*F. Abate, L. Sterpone, M. Violante and F. Lima Kastensmidt*- Finite Precision Processing in Wireless Applications [p. 1230]
*D. Novo, M. Li, B. Bougard, L. Van der Perre and F. Catthoor*- A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test [p. 1234]
*W.-W. Hsieh, I.-S. Lin and T. Hwang*- Efficient Reliability Simulation of Analog ICs Including Variability and Time-Varying Stress [p. 1238]
*E. Maricau and G. Gielen*- A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications [p. 1242]
*F. Demangel, N. Fau, N. Drabik, F. Charot and C. Wolinski*- Property Analysis and Design Understanding [p. 1246]
*U. Kuehne, D. Grosse and R. Drechsler*- Test Exploration and Validation Using Transaction Level Models [p. 1250]
*M.A. Kochte, C.G. Zoellin, M.E. Imhof, R. Salimi Khaligh, M. Radetzki, H.-J. Wunderlich, S. Di Carlo and P. Prinetto*

Moderators: D. Lattard, CEA-LETI, FR; P. Van der Wolf, NXP Semiconductors, NL

- Heterogeneous Multi-Core Platform for Consumer Multimedia Applications [p. 1254]
*P. Kollig, C. Osborne and T. Henriksson*- Multi-Core for Mobile Phones [p. 1260]
*C.H. (K) van Berkel*

- Strategic Directions towards Multicore Application Specific Computing [p. 1266]
*E. Flamand*

- Energy-Efficient Spatially-Adaptive Clustering and Routing in Wireless Sensor Networks [p. 1267]
*H. Long, Y. Liu, X. Fan, R.P. Dick and H. Yang*- Online Adaptation Policy Design for Grid Sensor Networks with Reconfigurable Embedded Nodes [p. 1273]
*V. Subramanian, M. Gilberti and A. Doboli*- Defect-Aware Logic Mapping for Nanowire-Based Programmable Logic Arrays via Satisfiability [p. 1279]
*Y. Zheng and C. Huang*- Debugging of Toffoli Networks [p. 1284]
*R. Wille, D. Grosse, S. Frehse, G.W. Dueck and R. Drechsler*- Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips [p. 1290]
*Y. Zhao and K. Chakrabarty*

- Error Correction in Single-Hop Wireless Sensor Networks - A Case Study [p. 1296]
*D. Schmidt, M. Berning and N. Wehn*- Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT [p. 1302]
*X. Guan, H. Lin and Y. Fei*- A Novel LDPC Decoder for DVB-S2 IP [p. 1308]
*S. Mueller, M. Schreger, M. Kabutz, M. Alles, F. Kienle and N. Wehn*- A Flexible Floating-Point Wavelet Transform and Wavelet Packet Processor [p. 1314]
*A. Guntoro and M. Glesner*

- On Hierarchical Statistical Static Timing Analysis [p. 1320]
*B. Li, N. Chen, M. Schmidt, W. Schneider and U. Schlichtmann*- Increasing the Accuracy of SAT-Based Debugging [p. 1326]
*A. Suelflow, G. Fey, C. Braunsteine, U. Kuehne and R. Drechsler*- GCS: High-Performance Gate-Level Simulation with GP-GPUs [p. 1332]
*D. Chatterjee, A. DeOrio and V. Bertacco*- Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation [p. 1338]
*X. Liu and Q. Xu*

- A New Design-for-Test Technique for SRAM Core-Cell Stability Faults [p. 1344]
*A. Ney, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian and V. Gouin*- Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing [p. 1349]
*S. Khursheed, B.M. Al-Hashimi and P. Harrod*- A Diagnosis Algorithm for Extreme Space Compaction [p. 1355]
*S. Holst and H.-J. Wunderlich*

- Thermal-Aware Memory Mapping in 3D Designs [p. 1361]
*A.-C. Hsieh and T. Hwang*- Static Analysis to Mitigate Soft Errors in Register Files [p. 1367]
*J. Lee and A. Shrivastava*- Using Dynamic Compilation for Continuing Execution under Reduced Memory Availability [p. 1373]
*O. Ozturk and M. Kandemir*

- A Design Methodology for Fully Reconfigurable Delta-Sigma Data Converters [p. 1379]
*Y. Ke, J. Craninkx and G. Gielen*- Optimal Sizing of Configurable Devices to Reduce Variability in Integrated Circuits [p. 1385]
*P. Wilson and R. Wilcock*- An Automated Design Flow for Vibration-Based Energy Harvester Systems [p. 1391]
*L. Wang, T.J. Kazmierski, B.M. Al-Hashimi, S.P. Beeby and D. Zhu*- Enhanced Design of Filterless Class-D Audio Amplifier [p. 1397]
*C.W. Lin, B.-S. Hsieh and Y.C. Lin*

Moderator: R. Ernst, TU Braunschweig, DE

*
Panelists: N. Topham, D. Pulley, M. Harrand, J. Goodacre, G. Martin and Y. Tanurhan
*

- Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation Techniques for Full-Swing and Low-Swing On-Chip Communication Channels [p. 1404]
*G. Paci, D. Bertozzi and L. Benini*- Dynamic Thermal Management in 3D Multicore Architectures [p. 1410]
*A.K. Coskun, J. Ayala, D. Atienza, T. Simunic-Rosing and J. Leblebici*- Energy Minimization for Real-Time Systems with Non-Convex and Discrete Operation Modes [p. 1416]
*F. Dabiri, A. Vahdatpour, M. Potkonjak and M. Sarrafzadeh*- Exploiting Narrow-Width Values for Thermal-Aware Register File Designs [p. 1422]
*S. Wang, J. Hu, S.G. Ziavras and S. W. Chung*

- Visual Quality Analysis for Dynamic Backlight Scaling in LCD Systems [p. 1428]
*A. Bartolini, M. Ruggiero and L. Benini*- A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC Video Codec [p. 1434]
*M. Shafique, L. Bauer and J. Henkel*- Efficient Constant-Time Entropy Decoding for H.264 [p. 1440]
*N. Iqbal and J. Henkel*- Predictive Models for Multimedia Applications Power Consumption Based on Use-Case and OS Level Analysis [p. 1446]
*P. Bellasi, W. Fornaciari and D. Siorpaes*

- Algebraic Techniques to Enhance Common Sub-Expression Elimination for Polynomial System Synthesis [p. 1452]
*S. Gopalakrishnan and P. Kalla*- Sequential Logic Synthesis Using Symbolic Bi-Decompsition [p. 1458]
*V. Kravets and A. Mishchenko*- On Decomposing Boolean Functions via Extended Cofactoring [p. 1464]
*A. Bernasconi, V. Ciriani, G. Trucco and T. Villa*- Register Placement for High-Performance Circuits [p. 1470]
*M.-F. Chiang, T. Okamoto and T. Yoshimura*

- Scalable Adaptive Scan (SAS) [p. 1476]
*A. Chandra, R. Kapur and Y. Kanzawa*- LFSR-Based Test-Data Compression with Self-Stoppable Seeds [p. 1482]
*M. Koutsoupia, E. Kalligeros, X. Kavousianos and D. Nikolos*- Seed Selection in LFSR-Reseeding-Based Test Compression for the Detection of Small-Delay Defects [p. 1488]
*M. Yilmaz and K. Chakrabarty*- A Generic Framework for Scan Capture Power Reduction in Fixed-Length Symbol-Based Test Compression Environment [p. 1494]
*X. Liu and Q. Xu*

- Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches [p. 1500]
*N. Bombieri, F. Fummi, G. Pravadelli and S. Vinco*- Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures [p. 1506]
*J. Zhu, I. Sander and A. Jantsch*- A Formal Approach for Specification-Driven AMS Behavioral Model Generation [p. 1512]
*S. Mukherjee, A. Ain, S.K. Panda, R. Mukhopadhyay and P. Dasgupta*- SC-DEVS: An Efficient Systemc Extension for the DEVS Model of Computation [p. 1518]
*F. Madlener, H.G. Molter and S.A. Huss*

- Exploiting Clock Skew Scheduling for FPGA [p. 1524]
*S. Bae, P. Mangalagiri and N. Vijaykrishnan*- Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing [p. 1530]
*X. Chen, J. Kang, S. Lin and V. Akella*- Runtime Reconfiguration of Custom Instructions for Real-Time Embedded Systems [p. 1536]
*H.P. Huynh and T. Mitra*

- Digital Design at a Crossroads - How to Make Statistical Design Industrially Relevant [p. 1542]
*U. Schlichtmann, M. Schmidt, M. Pronath, V. Glöckel, H. Kinzelbach, M. Dietrich, U. Eichler and J. Haase*

- Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints [p. 1548]
*V. Hanumaiah, S. Vrudhula and K. Chatha*- Scalable Compile-Time Scheduler for Multi-Core Architectures [p. 1552]
*M. Pelcat, P. Menuet, S. Aridhi and J.-F. Nezan*- Distributed Peak Power Management for Many-Core Architectures [p. 1556]
*J. Sartori and R. Kumar*- Generating the Trace Qualification Configuration for MCDS from a High Level Language [p. 1560]
*J. Braunes and R.G. Spallek*- Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC [p. 1564]
*D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli and L. Torres*- A MILP-Based Approach to Path Sensitization of Embedded Software [p. 1568]
*J.C. Costa and J.C. Monteiro*- An Efficient and Deterministic Multi-Tasking Run-Time Environment for Ada and the Ravenscar Profile on Atmel AVR ®32 UC3 Microcontroller [p. 1572]
*K. Nyborg Gregertsen and A. Skavhaug*- Toward a Runtime System for Reconfigurable Computers: A Virtualization Approach [p. 1576]
*M. Sabeghi and K. Bertels*- Separate Compilation and Execution of Imperative Synchronous Modules [p. 1580]
*E. Vecchie, J.-P. Talpin and K. Schneider*

Moderator: M. de Lange, ACE, NL

- Programming MPSoC Platforms: Road Works Ahead! [p. 1584]
*R. Leupers, S. Ha, A. Vajda, R. Doemer, M. Bekooij and A. Nohl*

- Faster SAT Solving with Better CNF Generation [p. 1590]
*B. Chambers, P. Manolios and D. Vroon*- Exploiting Structure in an AIG Based QBF Solver [p. 1596]
*F. Pigorsch and C. Scholl*- An Efficient Path-Oriented Bitvector Encoding Width Computation Algorithm for Bit-Precise Verification [p. 1602]
*N. He and M.S. Hsiao*

- Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors [p. 1608]
*M. Li, R. Fasthuber, D. Novo, B. Bougard, L. Van Der Perre and F. Catthoor*- A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing [p. 1614]
*C. Bachmann, A. Genser, J. Hulzink, M. Berekovic and C. Steger*- ASIP-Based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications [p. 1620]
*A.R. Jafri, D. Karakolah, A. Baghdadi and M. Jezequel*- Implementation of a Reduced-Lattice MIMO Detector for OFDM Systems [p. 1626]
*J. Soler-Garrido, H. Vetter, M. Sandell, D. Milford and A. Lillie*

- Increased Accuracy through Noise Injection in RTOS Simulation [p. 1632]
*H. Zabel and W. Mueller*- Flexible Energy-Aware Simulation of Heterogeneous Wireless Sensor Networks [p. 1638]
*F. Fummi, G. Perbellini, D. Quaglia and A. Acquaviva*- Selective State Retention Design Using Symbolic Simulation [p. 1644]
*A. Darbari, B.M. Al-Hashimi, D. Flynn and J. Biggs*

- A Loopback-Based INL Test Method for D/A and A/D Converters Employing a Stimulus Identification Technique [p. 1650]
*E. Korhonen and J. KostamovaaraI*- A Novel Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles [p. 1656]
*A. Goyal, M. Swaminathan and A. Chatterjee*- An Approach to Linear Model-Based Testing and Diagnosis for Nonlinear Cascaded Mixed-Signal Systems [p. 1662]
*R. Mueller, C. Wegener, H.-J. Jentschel, S. Sattler and H. Mattes*- Enrichment of Limited Training Sets in Machine-Learning-Based Analog/RF Test [p. 1668]
*H.-G. Stratigopoulos, S. Mir and Y. Makris*

- Speculative Reduction-Based Scalable Redundancy Identification [p. 1674]
*H. Mony, J. Baumgartner, A. Mishchenko and R. Brayton*- Scalable Liveness Checking via Property-Preserving Transformations [p. 1680]
*J. Baumgartner and H. Mony*- Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints [p. 1686]
*G. Cabodi, P. Camurati, L. Garcia, M. Murciano, S. Nocco and S. Quer*- Strengthening Properties Using on Refinement [p. 1692]
*M. Purandare, T. Wahl and D. Kroening*

- Sequential Logic Rectifications with Approximate SPFDs [p. 1698]
*Y.-S. Yang, S. Sinha, A. Veneris, R.K. Brayton and D. Smith*- Variable-Latency Design by Function Speculation [p. 1704]
*D. Baneres, J. Cortadella and M. Kishinevsky*- Fixed Points for Multi-Cycle Path Detection [p. 1710]
*V. D'Silva and D. Kroening*