Aamodt, T.: Characterizing the Performance Benefits of Fused CPU/GPU Systems Using FusionSim [p. 685]
Abdi, S.: Hybrid Prototyping of Multicore Embedded Systems [p. 1627]
Abdulla, P.: Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory [p. 785]
Abe, K.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Abella, J.: A Cache Design for Probabilistically Analysable Real-time Systems [p. 513]; Probabilistic Timing Analysis on Conventional Cache Designs [p. 603]; Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes [p. 917]
Abouzeid, F.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Abraham, J.: Non-Speculative Double-Sampling Technique to Increase Energy-Efficiency in a High-Performance Processor [p. 254]
Aceituno, P. V.: Leveraging Variable Function Resilience for Selective Software Reliability on Unreliable Hardware [p. 1759]
Acquaviva, A.: HW-SW Integration for Energy-Efficient/Variability-Aware Computing [p. 607]
Adnan, M.: Utility-Aware Deferred Load Balancing in the Cloud Driven by Dynamic Pricing of Electricity [p. 262]
Afzali-Kusha, A.: An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications [p. 350]
Agostini, L.: Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding [p. 665]
Aguado, J.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]
Ahmad, M.: Formal Analysis of Steady State Errors in Feedback Control Systems Using HOL-Light [p. 1423]
Ahmadyan, S. N.: Runtime Verification of Nonlinear Analog Circuits Using Incremental Time-Augmented RRT Algorithm [p. 21]; Reachability Analysis of Nonlinear Analog Circuits through Iterative Reachable Set Reduction [p. 1436]
Ait Hmid, M.: Time- and Angle-triggered Real-time Kernel [p. 1060]
Aitken, R.: SlackProbe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology [p. 282]; Reliability Analysis Reloaded: How Will We Survive? [p. 358]; Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic Write Vmin [p. 1819]
Akesson, B.: System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs [p. 236]; Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis [p. 308]; Conservative Open-Page Policy for Mixed Time-Criticality Memory Controllers [p. 525]; Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller [p. 1307]
Akhlaghi, V.: An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications [p. 350]
Al Farisi, B.: An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits [p. 821]
Al-Ars, Z.: Hybrid Interconnect Design for Heterogeneous Hardware Accelerators [p. 843]; Efficient Software-Based Fault Tolerance Approach on Multicore Platforms [p. 921]
Al-Hashimi, B.M.: MALEC: A Multiple Access Low Energy Cache [p. 368]; DoE-based Performance Optimization of Energy Management in Sensor Nodes Powered by Tunable Energy-Harvesters [p. 484]; A Survy of Multi-Source Energy Harvesting Systems [p. 905]
Alias, C.: Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA [p. 575]
Aliee, H.: Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults [p. 1621]
Alpert, C.J.: CATALYST: Planning Layer Directives for Effective Design Closure [p. 1873]
Amarù, L.: Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]; Biconditional BDD: A Novel Canonical BDD for Logic Synthesis Targeting XOR-rich Circuits [p. 1014]
Amat, E.: Design and Implementation of an Adaptive Proactive Reconfiguration Technique for SRAM Caches [p. 1303]
Ambrose, J.A.: CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]
Aminifar, Amir: Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees [p. 1093]
Amory, A.: Topology-Agnostic Fault-Tolerant NoC Routing Method [p. 1595]
Ampadu, P.: Breaking the Energy Barrier in Fault-Tolerant Caches for Multicore Systems [p. 731]
Ananthanarayan, S.: Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors [p. 933]
Ancajas, D.M.: Proactive Aging Management in Heterogeneous NoCs through a Criticality-driven Routing Approach [p. 1032]
Anderson, J.H.: Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis [p. 194]
Andriamisaina, C.: An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the STHORM Many-Core Architecture [p. 531]
Ansaloni, G.: Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms [p. 396]; A Methodology for Embedded Classification of Heartbeats Using Random Projections [p. 899]
Antoniadis, C.: Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]
Antoniadis, D.: Statistical Modeling with the Virtual Source MOSFET Model [p. 1454]
Arima, E.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Ascheid, G.: High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]
Atat, Y.: Statically-scheduled Application-specific Processor Design: A Case-study on MMSE MIMO Equalization [p. 677]
Athanasopoulos, P.: 3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling [p. 1241]
Atienza, D.: Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms [p. 396]; A Methodology for Embedded Classification of Heartbeats Using Random Projections [p. 899]; Correlation-Aware Virtual Machine Allocation for Energy-Efficient Datacenters [p. 1345]; Closed-Loop Control for Power and Thermal Management in Multi-core Processors: Formal Methods and Industrial Practice [p. 1879]
Atta, I.: A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches [p. 89]
Axer, P.: Sensitivity Analysis for Arbitrary Activation Patterns in Real-time Systems [p. 135]
Ayad, G.: HW-SW Integration for Energy-Efficient/Variability-Aware Computing [p. 607]
Ayala, J.L.: Leakage and Temperature Aware Server Control for Improving Energy Efficiency in Data Centers [p. 266]

Backes, J.: Using Cubes of Non-state Variables with Property Directed Reachability [p. 807]
Badereddine, N.: Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]
Baghdadi, A.: Parameterized Area-efficient Multi-standard Turbo Decoder [p. 109]; Statically-scheduled Application-specific Processor Design: A Case-study on MMSE MIMO Equalization [p. 677]
Bahr, R.: Smart, Connected and Mobile: Architecting Future Electric Mobility Ecosystems [p. 1740]
Bai, K.: Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures [p. 593]
Bakkaloglu, B.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Bakshi, D.: LFSR Seed Computation and Reduction Using SMT-Based Fault-Chaining [p. 1071]
Balachandran, S.: An Efficient Wirelength Model for Analytical Placement [p. 1711]
Balasubramanian, L.: Towards Adaptive Test of Multi-core RF SoCs [p. 743]
Ballan, O.: On-Line Functionally Untestable Fault Identification in Embedded Processor Cores [p. 1462]
Balsamo, D.: Perpetual and Low-cost Power Meter for Monitoring Residential and Industrial Appliances [p. 1155]
Bampi, S.: Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding [p. 665]
BanaiyanMofrad, A.: Modeling and Analysis of Fault-tolerant Distributed Memories for Networks-on-Chip [p. 1605]
Baniasadi, A.: Using Synchronization Stalls in Power-aware Accelerators [p. 400]
Bartolini, A.: SCC Thermal Model Identification via Advanced Bias-Compensated Least-Squares [p. 230]
Bartolini, S.: Contrasting Wavelength-Routed Optical NoC Topologies for Power-Efficient 3D-Stacked Multicore Processors Using Physical-Layer Analysis [p. 1589]
Bauer, L.: Adaptive Cache Management for a Combined SRAM and DRAM Cache Hierarchy for Multi-cores [p. 77]; An H.264 Quad-FullHD Low-Latency Intra Video Encoder [p. 115]
Baumgartner, J.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]; GLA: Gate-Level Abstraction Revisited [p. 1399]
Bayrak, A.G.: An EDA-Friendly Protection Scheme against Side-Channel Attacks [p. 410]
Beanato, Giulia: 3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling [p. 1241]
Beck, A.C.S.: A Transparent and Energy Aware Reconfigurable Multiprocessor Platform for Simultaneous ILP and TLP Exploitation [p. 1559]
Becker, B.: Accurate QBF-based Test Pattern Generation in Presence of Unknown Values [p. 436]; Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths [p. 448]
Becker, J.: Hybrid Interconnect Design for Heterogeneous Hardware Accelerators [p. 843]
Beer, S.: Metastability Challenges for 65nm and Beyond; Simulation and Measurements [p. 1297]
Beigne, E.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]; A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits [p. 1056]
Belleville, M.: A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits [p. 1056]
Belov, A.: Core Minimization in SAT-based Abstraction [p. 1411]
Beltrame, G.: Explicit Transient Thermal Simulation of Liquid-Cooled 3D ICs [p. 1385]
Benazzouz, Y.: Self-aware Cyber-physical Systems and Applications in Smart Buildings and Cities [p. 1149]
Beneventi, F.: SCC Thermal Model Identification via Advanced Bias-Compensated Least-Squares [p. 230]
Benini, L.: SCC Thermal Model Identification via Advanced Bias-Compensated Least-Squares [p. 230]; Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters [p. 541]; A Survy of Multi-Source Energy Harvesting Systems [p. 905]; Design of an Ultra-low Power Device for Aircraft Structural Health Monitoring [p. 1127]; Enabling Fine-Grained OpenMP Tasking on Tightly-Coupled Shared Memory Clusters [p. 1504]; Hierarchically Focused Guardbanding: An Adaptive Approach to Mitigate PVT Variations and Aging [p. 1695]
Bennett, P.: Configurable IO Integration to Reduce System-on-Chip Time to Market: DDR, PCIe Examples [p. 169]
Benoist, T.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Berger, E.: Probabilistic Timing Analysis on Conventional Cache Designs [p. 603]
Bernard, S.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Bernardi, P.: On-Line Functionally Untestable Fault Identification in Embedded Processor Cores [p. 1462]
Bernasconi, A.: Minimization of P-Circuits Using Boolean Relations [p. 996]
Bertacco, V.: Machine Learning-based Anomaly Detection for Post-silicon Bug Diagnosis [p. 491]; On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]
Bertels, K.: Hybrid Interconnect Design for Heterogeneous Hardware Accelerators [p. 843]; Efficient Software-Based Fault Tolerance Approach on Multicore Platforms [p. 921]
Bertin, V.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
Bertozzi, D.: A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems [p. 332]; Contrasting Wavelength-Routed Optical NoC Topologies for Power-Efficient 3D-Stacked Multicore Processors Using Physical-Layer Analysis [p. 1589]
Besnard, L.: Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]
Bhadra, J.: Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step [p. 454]
Bhatta, D.: Periodic Jitter and Bounded Uncorrelated Jitter Decomposition Using Incoherent Undersampling [p. 1667]
Bhattacharjee, S.: A Fast and Efficient DFT for Test and Diagnosis of Power Switches in SoCs [p. 1089]
Bi, X.: STT-RAM Designs Supporting Dual-Port Accesses [p. 853]
Biere, A.: Bridging the Gap between Dual Propagation and CNF-based QBF Solving [p. 811]
Billoint, O.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Blanche, T.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Blouet, P.: PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future? [p. 1526]
Blystad, L.-C.: Smart, Connected and Mobile: Architecting Future Electric Mobility Ecosystems [p. 1740]
Bobba, S.: Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]
Boettcher, M.: MALEC: A Multiple Access Low Energy Cache [p. 368]
Bogdan, P.: SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model [p. 354]
Boley, J.: Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic Write Vmin [p. 1819]
Boll, D.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Bombieri, N.: On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]
Bonazza, M.: On-Line Functionally Untestable Fault Identification in Embedded Processor Cores [p. 1462]
Bonhomme, Y.: Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection [p. 1077]
Boning, D.: Statistical Modeling with the Virtual Source MOSFET Model [p. 1454]
Bonnot, P.: Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes [p. 129]
Bononi, L.: Interactions of Large Scale EV Mobility and Virtual Power Plants [p. 1725]
Borrmann, J.M.: An H.264 Quad-FullHD Low-Latency Intra Video Encoder [p. 115]
Bosio, A.: Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]
Botteron, C.: A Sub-μA Power Management Circuit in 0.18μm CMOS for Energy Harvesters [p. 1197]
Bouard, A.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]
Bouhadiba, T.: System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal Management [p. 1609]
Bozdas, K.: Exploiting Replicated Checkpoints for Soft Error Detection and Correction [p. 1494]
Bradford, R.: Optimized Scheduling of Multi-IMA Partitions with Exclusive Region for Synchronized Real- Time Multi-Core Systems [p. 970]; Holistic Design Parameter Optimization of Multiple Periodic Resources in Hierarchical Scheduling [p. 1313]
Brandon, A.: Support for Dynamic Issue Width in VLIW Processors Using Generic Binaries [p. 827]
Braojos, R.: Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms [p. 396]; A Methodology for Embedded Classification of Heartbeats Using Random Projections [p. 899]
Brayton, R.: A Semi-Canonical Form for Sequential AIGs [p. 797]; GLA: Gate-Level Abstraction Revisited [p. 1399]
Breuer, M.: Using Explicit Output Comparisons for Fault Tolerant Scheduling (FTS) on Modern High-Performance Processors [p. 927]; A New Paradigm for Trading Off Yield, Area and Performance to Enhance Performance per Wafer [p. 1753]
Brewer, F.: Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT [p. 1442]
Bringmann, O.: Shared Memory Aware MPSoC Software Deployment [p. 1771]
Brisk, P.: An EDA-Friendly Protection Scheme against Side-Channel Attacks [p. 410]
Brown, S.D.: Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis [p. 194]
Bruneel, K.: An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits [p. 821]
Brunelli, D.: A Survy of Multi-Source Energy Harvesting Systems [p. 905]; Design of an Ultra-low Power Device for Aircraft Structural Health Monitoring [p. 1127]; Perpetual and Low-cost Power Meter for Monitoring Residential and Industrial Appliances [p. 1155]
Brunschwiler, T.: Roadmap towards Ultimately-Efficient Zeta-Scale Datacenters [p. 1339]
Buckl, C.: Energy Optimization with Worst-Case Deadline Guarantee for Pipelined Multiprocessor Systems [p. 45]
Bund, T.: Event Density Analysis for Event Triggered Control Systems [p. 1111]
Burg, A.: Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms [p. 396]; Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]
Burgess, M.: Machine Learning-based Anomaly Detection for Post-silicon Bug Diagnosis [p. 491]
Burgio, P.: Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters [p. 541]; Enabling Fine-Grained OpenMP Tasking on Tightly-Coupled Shared Memory Clusters [p. 1504]
Burleson, W.: Run-time Probabilistic Detection of Miscalibrated Thermal Sensors in Many-core Systems [p. 1395]

Cabodi, G.: Optimization Techniques for Craig Interpolant Compaction in Unbounded Model Checking [p. 1417]
Cai, Y.: Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling [p. 1285]
Caione, C.: Design of an Ultra-low Power Device for Aircraft Structural Health Monitoring [p. 1127]
Calhoun, B.: Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic Write Vmin [p. 1819]
Calimera, A.: A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions [p. 877]
Canal, R.: Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]
Canis, A.: Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis [p. 194]
Cardoso, J.M.P.: An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits [p. 821]
Carloni, L.: PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead [p. 171]
Carrara, S.: Electronic Implants: Power Delivery and Management [p. 1540]
Carretero, J.: Capturing Vulnerability Variations for Register Files [p. 1468]
Carro, L.: A Transparent and Energy Aware Reconfigurable Multiprocessor Platform for Simultaneous ILP and TLP Exploitation [p. 1559]
Carulli J.: Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests [p. 553]
Carvajal, G.: An Open Platform for Mixed-Criticality Real-time Ethernet [p. 153]
Case, M.: A Semi-Canonical Form for Sequential AIGs [p. 797]
Cassano, L.: On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems [p. 717]
Castellana, V.G.: Scheduling Independent Liveness Analysis for Register Binding in High Level Synthesis [p. 1571]
Castro, F.: Reducing Writes in Phase-Change Memory Environments by Using Efficient Cache Replacement Policies [p. 93]
Cazorla, F. J.: A Cache Design for Probabilistically Analysable Real-time Systems [p. 513]; Probabilistic Timing Analysis on Conventional Cache Designs [p. 603]
Celanovic, I.: MARTHA: Architecture for Control and Emulation of Power Electronics and Smart Grid Systems [p. 519]
Cervin, A.: Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees [p. 1093]
Cesana, G.: UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-efficiency [p. 952]
Cevrero, A.: Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]; 3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling [p. 1241]
Cha, B.: Trojan Detection via Delay Measurements: A New Approach to Select Paths and Vectors to Maximize Effectiveness and Minimize Cost [p. 1265]
Cha, H.: Runtime Power Estimation of Mobile AMOLED Displays [p. 61]
Chabrol, D.: Time- and Angle-triggered Real-time Kernel [p. 1060]
Chakrabarty, K.: Fault Detection, Real-Time Error Recovery, and Experimental Demonstration for Digital Microfluidic Biochips [p. 559]; Testing for SoCs with Advanced Static and Dynamic Power-Management Capabilities [p. 737]; Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels [p. 1065]
Chakraborty, K.: Proactive Aging Management in Heterogeneous NoCs through a Criticality-driven Routing Approach [p. 1032]
Chakraborty, S.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]; Quality-Aware Media Scheduling on MPSoC Platforms [p. 976]; Priority Assignment for Event-triggered Systems Using Mathematical Programming [p. 982]; Compositional Analysis of Switched Ethernet Topologies [p. 1099]; Multirate Controller Design for Resource- and Schedule-Constrained Automotive ECUs [p. 1123]
Chan, T.-B.: Impact of Adaptive Voltage Scaling on Aging-Aware Signoff [p. 1683]
Chan, W.-T.: Impact of Adaptive Voltage Scaling on Aging-Aware Signoff [p. 1683]
Chandra, V.: SlackProbe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology [p. 282]; Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic Write Vmin [p. 1819]
Chandrakasan, A.P.: SMART: A Single-Cycle Reconfigurable NoC for SoC Applications [p. 338]; 40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS [p. 1637]
Chandran, S.: Space Sensitive Cache Dumping for Post-silicon Validation [p. 497]
Chandrasekar, K.: System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs [p. 236]
Chaney, T.: Metastability Challenges for 65nm and Beyond; Simulation and Measurements [p. 1297]
Chang, C.-L.(L.): Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step [p. 454]
Chang, N.: Optimal Control of a Grid-Connected Hybrid Electrical Energy Storage System for Homes [p. 881]; Capital Cost-Aware Design and Partial Shading-Aware Architecture Optimization of a Reconfigurable Photovoltaic System [p. 909]; Saliency Aware Display Power Management [p. 1203]; Adaptive Thermal Management for Portable System Batteries by Forced Convection Cooling [p. 1225]
Chantem, T.: Enhancing Multicore Reliability through Wear Compensation in Online Assignment and Scheduling [p. 1373]
Chatterjee, A.: Periodic Jitter and Bounded Uncorrelated Jitter Decomposition Using Incoherent Undersampling [p. 1667]
Chatterjee, D.: On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]
Chattopadhyay, A.: Accurate and Efficient Reliability Estimation Techniques during ADL-Driven Embedded Processor Design [p. 547]; High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]
Chaudhari, A.: Non-Speculative Double-Sampling Technique to Increase Energy-Efficiency in a High-Performance Processor [p. 254]
Chauhan, P.: A Semi-Canonical Form for Sequential AIGs [p. 797]
Chauvet, H.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
Chaver, D.: Reducing Writes in Phase-Change Memory Environments by Using Efficient Cache Replacement Policies [p. 93]
Chen, C.: Accurate and Efficient Reliability Estimation Techniques during ADL-Driven Embedded Processor Design [p. 547]
Chen, C.-C.: System-Level Modeling and Microprocessor Reliability Analysis for Backend Wearout Mechanisms [p. 1615]
Chen, C.-H.O.: SMART: A Single-Cycle Reconfigurable NoC for SoC Applications [p. 338]
Chen, D.: A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis under Process Variation [p. 1789]
Chen, G.: Energy Optimization with Worst-Case Deadline Guarantee for Pipelined Multiprocessor Systems [p. 45]
Chen, H.: Multi-level Phase Analysis for Sampling Simulation [p. 649]
Chen, H.: Core Minimization in SAT-based Abstraction [p. 1411]
Chen, H.-M.: Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming [p. 1701]; A Network-Flow Based Algorithm for Power Density Mitigation at Post-Placement Stage [p. 1707]; PAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Design [p. 1849]
Chen, H.-Y.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Chen, J.-J.: Leveraging Variable Function Resilience for Selective Software Reliability on Unreliable Hardware [p. 1759]
Chen, W.: Optimized Out-of-Order Parallel Discrete Event Simulation Using Predictions [p. 3]
Chen, X.: High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]
Chen, Y.: DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems [p. 380]; Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer [p. 859]; Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM [p. 1247]
Chen, Y.: Resource-Constrained High-Level Datapath Optimization in ASIP Design [p. 198]
Chen, Y.-C.: On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]
Chen, Y.-H.: Dual-addressing Memory Architecture for Two-dimensional Memory Access Patterns [p. 71]
Chen, Y.-L.: Automatic Circuit Sizing Technique for the Analog Circuits with Flexible TFTs Considering Process Variation and Bending Effects [p. 1458]
Chen, Y.-Y.: A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis under Process Variation [p. 1789]
Cheng, C.-H.: Co-Synthesis of Data Paths and Clock Control Paths for Minimum-Period Clock Gating [p. 1831]
Cheng, K.-T.: Mutation Analysis with Coverage Discounting [p. 31]
Chiang, C.-E.: On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]
Cho, M.: Perceptual Quality Preserving SRAM Architecture for Color Motion Pictures [p. 103]
Choi, K.: Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication [p. 1579]
Chokshi, D.B.: A Satisfiability Approach to Speed Assignment for Distributed Real-Time Systems [p. 749]
Ciesielski, M.: FPGA Latency Optimization Using System-level Transformations and DFG Restructuring [p. 1553]
Cilardo, A.: Efficient and Scalable OpenMP-based System-level Design [p. 988]
Cinotti, T. S.: Interactions of Large Scale EV Mobility and Virtual Power Plants [p. 1725]
Ciriani, V.: Minimization of P-Circuits Using Boolean Relations [p. 996]
Clerc, S.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Coenen, T.: High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]
Constantin, J.: Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms [p. 396]
Coppola, G.: e-Mobility - The Next Frontier for Automotive Industry [p. 1745]
Coppola, M.: From Embedded Multi-core SoCs to Scale-out Processors [p. 947]
Cornet, J.: Fast and Accurate TLM Simulations Using Temporal Decoupling for FIFO-based Communications [p. 1185]
Corporaal, H.: Future of GPGPU Micro-Architectural Parameters [p. 392]
Coskun, A.K.: Leakage and Temperature Aware Server Control for Improving Energy Efficiency in Data Centers [p. 266]; 3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling [p. 1241]
Cotofana, S.D.: Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? [p. 1251]
Courtois, B.: PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead [p. 171]
Cox, J.: Metastability Challenges for 65nm and Beyond; Simulation and Measurements [p. 1297]
Cozzi, D.: On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems [p. 717]
Cristal, A.: FaulTM: Error Detection and Recovery Using Hardware Transactional Memory [p. 220]
Cronsioe, J.: Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]
Curtsinger, C.: Probabilistic Timing Analysis on Conventional Cache Designs [p. 603]

Daloukas, K.: A Parallel Fast Transform-Based Preconditioning Approach for Electrical-Thermal Co- Simulation of Power Delivery Networks [p. 1689]
Daneshtalab, M.: CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems [p. 1048]; Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy [p. 1601]
Danneels, H.: A Low-Power and Low-Voltage BBPLL-Based Sensor Interface in 130nm CMOS for Wireless Sensor Networks [p. 1431]
Dar, T.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Darbel, N.: SoC Low-Power Practices for Wireless Applications [p. 778]
Darte, A.: Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA [p. 575]
Das, A.: Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems [p. 689]; Communication and Migration Energy Aware Design Space Exploration for Multicore Systems with Intermittent Faults [p. 1631]
Datta, S.: On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]
David, R.: An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the STHORM Many-Core Architecture [p. 531]; A Fast and Accurate Methodology for Power Estimation and Reduction of Programmable Architectures [p. 1054]; ARTM: A Lightweight Fork-join Framework for Many-core Embedded Systems [p. 1510]
David, V.: Time- and Angle-triggered Real-time Kernel [p. 1060]
Davoodi, A.: A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug [p. 485]
de Barros Naviner, L.A.: Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection [p. 1077]
De Jonghe, D.: Extracting Analytical Nonlinear Models from Analog Circuits by Recursive Vector Fitting of Transfer Function Trajectories [p. 1448]
de Man, H.: PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead [p. 171]
De Marchi, L.: Design of an Ultra-low Power Device for Aircraft Structural Health Monitoring [p. 1127]
De Marchi, M.: Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]
De Micheli, G.: Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]; Biconditional BDD: A Novel Canonical BDD for Logic Synthesis Targeting XOR-rich Circuits [p. 1014]; Electronic Implants: Power Delivery and Management [p. 1540]
de Schryver, C.: A Multi-Level Monte Carlo FPGA Accelerator for Option Pricing in the Heston Model [p. 248]
De Smedt, V.: A Low-Power and Low-Voltage BBPLL-Based Sensor Interface in 130nm CMOS for Wireless Sensor Networks [p. 1431]
De Venuto, D.: Dr. Frankenstein's Dream Made Possible: Implanted Electronic Devices [p. 1531]
De, V.: Near-Threshold Voltage Design in Nanoscale CMOS [p. 612]
Degomme, A.: Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]
Dehaene, W.: A Low-Power and Low-Voltage BBPLL-Based Sensor Interface in 130nm CMOS for Wireless Sensor Networks [p. 1431]
Del Barrio, A.A.: Multispeculative Additive Trees in High-Level Synthesis [p. 188]
Deng, L.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Deng, P.: Robust and Extensible Task Implementations of Synchronous Finite State Machines [p. 1319]
DeOrio, A.: Machine Learning-based Anomaly Detection for Post-silicon Bug Diagnosis [p. 491]
Deruyter, T.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
Derwig, R.: Modular SoC Integration with Subsystems: The Audio Subsystem Case [p. 157]
Deschrijver, D.: Extracting Analytical Nonlinear Models from Analog Circuits by Recursive Vector Fitting of Transfer Function Trajectories [p. 1448]
Deutsch, S.: Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels [p. 1065]
Devadas, S.: MARTHA: Architecture for Control and Emulation of Power Electronics and Smart Grid Systems [p. 519]
Devanathan, V. R.: Towards Adaptive Test of Multi-core RF SoCs [p. 743]
Dhaene, T.: Extracting Analytical Nonlinear Models from Analog Circuits by Recursive Vector Fitting of Transfer Function Trajectories [p. 1448]
Di Natale, M.: Robust and Extensible Task Implementations of Synchronous Finite State Machines [p. 1319]
Díaz, A.: Wireless Sensor Network Simulation for Security and Performance Analysis [p. 432]
Dick, R.P.: Enhancing Multicore Reliability through Wear Compensation in Online Assignment and Scheduling [p. 1373]
Dilillo, L.: Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]
Dimitrakopoulos, G.: Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports [p. 344]
Diversi, R.: SCC Thermal Model Identification via Advanced Bias-Compensated Least-Squares [p. 230]
Dömer, R.: Optimized Out-of-Order Parallel Discrete Event Simulation Using Predictions [p. 3]
Domic, A.: PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead [p. 171]
Dong, X.: OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches [p. 847]
dos Santos, L.C.V.: On-the-fly Verification of Memory Consistency with Concurrent Relaxed Scoreboards [p. 631]
Drechsler, R.: Scalable Fault Localization for SystemC TLM Designs [p. 35]; Determining Relevant Model Elements for the Verification of UML/OCL Specifications [p. 1189]; Towards a Generic Verification Methodology for System Models [p. 1193]
Duato, J.: Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]
Duderstadt, B.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]
Dündar, G.: Area Optimization on Fixed Analog Floorplans Using Convex Area Functions [p. 1843]
Dutoit, D.: 3D Integration for Power-Efficient Computing [p. 779]
Dutt, N.: Modeling and Analysis of Fault-tolerant Distributed Memories for Networks-on-Chip [p. 1605]
Dwarkadas, S.: Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory [p. 785]

Earl, J.: Intuitive ECO Synthesis for High Performance Circuits [p. 1002]
Ebrahimi, M.: CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems [p. 1048]; Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy [p. 1601]
Een, N.: A Semi-Canonical Form for Sequential AIGs [p. 797]; GLA: Gate-Level Abstraction Revisited [p. 1399]
Eichwald , C.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
El Alaoui, S.: Accuracy vs Speed Tradeoffs in the Estimation of Fixed-Point Errors on Linear Time-Invariant Systems [p. 15]
El-Nacouzi, M.: A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches [p. 89]
Elbayoumi, M.: A Novel Concurrent Cache-friendly Binary Decision Diagram Construction for Multi-core Platforms [p. 1427]
Eles, P.: Dynamic Configuration Prefetching Based on Piecewise Linear Prediction [p. 815]; Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees [p. 1093]; Optimization of Secure Embedded Systems with Dynamic Task Sets [p. 1765]
Elfadel, I. (A.): Statistical Modeling with the Virtual Source MOSFET Model [p. 1454]; Closed-Loop Control for Power and Thermal Management in Multi-core Processors: Formal Methods and Industrial Practice [p. 1879]
ElNainay, M.: A Novel Concurrent Cache-friendly Binary Decision Diagram Construction for Multi-core Platforms [p. 1427]
Elshambakey, M.: FBLT: A Real-Time Contention Manager with Improved Schedulability [p. 1325]
Enachescu, M.: Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? [p. 1251]
Engels, S.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Erb, D.: Accurate QBF-based Test Pattern Generation in Presence of Unknown Values [p. 436]
Ergin, O.: Exploiting Replicated Checkpoints for Soft Error Detection and Correction [p. 1494]
Erichsen, A.: Topology-Agnostic Fault-Tolerant NoC Routing Method [p. 1595]
Ernst, R.: Sensitivity Analysis for Arbitrary Activation Patterns in Real-time Systems [p. 135]; Timing Analysis of Multi-Mode Applications on AUTOSAR Conform Multi-Core Systems [p. 302]; Formal Analysis of Sporadic Bursts in Real-Time Systems [p. 767]
Evain, S.: Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection [p. 1077]
Evans, A.: Error Detection in Ternary CAMs Using Bloom Filters [p. 1474]
Evmorfopoulos, N.: Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]; A Parallel Fast Transform-Based Preconditioning Approach for Electrical-Thermal Co- Simulation of Power Delivery Networks [p. 1689]

Fahmy, S.A.: An Approach for Redundancy in FlexRay Networks Using FPGA Partial Reconfiguration [p. 721]
Fair, R.: Fault Detection, Real-Time Error Recovery, and Experimental Demonstration for Digital Microfluidic Biochips [p. 559]
Fakih, M.: Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking [p. 1167]
Fallah, F.: Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]
Falsafi, B.: From Embedded Multi-core SoCs to Scale-out Processors [p. 947]
Farine, P.A.: A Sub-μA Power Management Circuit in 0.18μm CMOS for Energy Harvesters [p. 1197]
Farley, B.: PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future? [p. 1526]
Feld, T.: Sufficient Real-Time Analysis for an Engine Control Unit with Constant Angular Velocities [p. 1335]
Feng, Z.: Large-Scale Flip-Chip Power Grid Reduction with Geometric Templates [p. 1679]
Fernández, F.: Area Optimization on Fixed Analog Floorplans Using Convex Area Functions [p. 1843]
Ferrandi, F.: Scheduling Independent Liveness Analysis for Register Binding in High Level Synthesis [p. 1571]
Fettweis, G.: Wireless Interconnect for Board and Chip Level [p. 958]
Fey, G.: Reliability Analysis Reloaded: How Will We Survive? [p. 358]; Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis [p. 939]; Tuning Dynamic Data Flow Analysis to Support Design Understanding [p. 1179]
Finder, A.: Tuning Dynamic Data Flow Analysis to Support Design Understanding [p. 1179]
Fiori, G.: A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis under Process Variation [p. 1789]
Fiorini, P.: Model Predictive Control over Delay-Based Differentiated Services Control Networks [p. 1117]
Firouzi, F.: Instruction-Set Extension under Process Variation and Aging Effects [p. 182]; Incorporating the Impacts of Workload-Dependent Runtime Variations into Timing Analysis [p. 1022]
Fischer, E.: Wireless Interconnect for Board and Chip Level [p. 958]
Fischmeister, S.: An Open Platform for Mixed-Criticality Real-time Ethernet [p. 153]
Flatresse, P.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]; UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-efficiency [p. 952]
Fontanelli, A.: PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future? [p. 1526]
Fornaciari, W.: Sensor-wise Methodology to Face NBTI Stress of NoC Buffers [p. 1038]
Fourmigue, A.: Explicit Transient Thermal Simulation of Liquid-Cooled 3D ICs [p. 1385]
Fränzle, M.: Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking [p. 1167]
Frehse, S.: Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis [p. 939]
Freitas, L.S.: On-the-fly Verification of Memory Consistency with Concurrent Relaxed Scoreboards [p. 631]
Fuhrmann, I.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]
Fujita, S.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Fummi, F.: On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]

Gabrielli, G.: MALEC: A Multiple Access Low Energy Cache [p. 368]
Gaillardon, P.-E.: Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]; Biconditional BDD: A Novel Canonical BDD for Logic Synthesis Targeting XOR-rich Circuits [p. 1014]
Galilée, B.: Fast and Accurate TLM Simulations Using Temporal Decoupling for FIFO-based Communications [p. 1185]
Galissot, M.: Self-aware Cyber-physical Systems and Applications in Smart Buildings and Cities [p. 1149]
Gallo, L.: Efficient and Scalable OpenMP-based System-level Design [p. 988]
Gang, S.: A 100 GOPS ASP Based Baseband Processor for Wireless Communication [p. 121]
Gangadharan, D.: Quality-Aware Media Scheduling on MPSoC Platforms [p. 976]
Ganguly, A.: Energy-Efficient Multicore Chip Design through Cross-Layer Approach [p. 725]
Gao, Y.: Using Explicit Output Comparisons for Fault Tolerant Scheduling (FTS) on Modern High-Performance Processors [p. 927]; A New Paradigm for Trading Off Yield, Area and Performance to Enhance Performance per Wafer [p. 1753]
Gardner, D.S.: Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]
Garg, S.: Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors [p. 39]; Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors [p. 933]
Gautier, T.: Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]
Gelado, I.: Experiences with Mobile Processors for Energy Efficient HPC [p. 464]
Georgiadis, N.: Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports [p. 344]
Ghaida, R.S.: Role of Design in Multiple Patterning: Technology Development, Design Enablement and Process Control [p. 314]
Gherman, V.: Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection [p. 1077]
Ghiribaldi, A.: A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems [p. 332]
Ghoreishizadeh, S.S.: Electronic Implants: Power Delivery and Management [p. 1540]
Ghosh, S.: Automated Determination of Top Level Control Signals [p. 509]
Gielen, G.: Stochastic Degradation Modeling and Simulation for Analog Integrated Circuits in Nanometer CMOS [p. 326]; A Low-Power and Low-Voltage BBPLL-Based Sensor Interface in 130nm CMOS for Wireless Sensor Networks [p. 1431]; Extracting Analytical Nonlinear Models from Analog Circuits by Recursive Vector Fitting of Transfer Function Trajectories [p. 1448]
Ginosar, R.: Metastability Challenges for 65nm and Beyond; Simulation and Measurements [p. 1297]
Girão, G.: Exploring Resource Mapping Policies for Dynamic Clustering on NoC-based MPSoCs [p. 681]; Modeling and Analysis of Fault-tolerant Distributed Memories for Networks-on-Chip [p. 1605]
Girard, P.: Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]
Girard , S.: A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits [p. 1056]
Giraud, B.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Giraud, O.-A.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
Gizopoulos, D.: Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes [p. 129]
Glaß, M.: Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults [p. 1621]
Gogolla, M.: Towards a Generic Verification Methodology for System Models [p. 1193]
Gomez-Prado, D.: FPGA Latency Optimization Using System-level Transformations and DFG Restructuring [p. 1553]
Gomony, M.D.: Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller [p. 1307]
Goodacre, J.: From Embedded Multi-core SoCs to Scale-out Processors [p. 947]
Goossens K.: System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs [p. 236]; Conservative Open-Page Policy for Mixed Time-Criticality Memory Controllers [p. 525]; Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller [p. 1307]
Goossens, S.: Conservative Open-Page Policy for Mixed Time-Criticality Memory Controllers [p. 525]
Gordillo-Gonzales, V.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Goswami, D.: Compositional Analysis of Switched Ethernet Topologies [p. 1099]; Multirate Controller Design for Resource- and Schedule-Constrained Automotive ECUs [p. 1123]
Goultiaeva, A.: Bridging the Gap between Dual Propagation and CNF-based QBF Solving [p. 811]
Grani, P.: Contrasting Wavelength-Routed Optical NoC Topologies for Power-Efficient 3D-Stacked Multicore Processors Using Physical-Layer Analysis [p. 1589]
Grasset, A.: Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes [p. 129]
Green, K.: Innovative Energy Storage Solutions for Future Electromobility in Smart Cities [p. 1730]
Greim, M.: A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot [p. 1331]
Grellert, M.: Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder [p. 125]
Grimm, C.: Ultra-Low Power: An EDA Challenge [p. 483]
Gross, K.: Leakage and Temperature Aware Server Control for Improving Energy Efficiency in Data Centers [p. 266]
Große, D.: Scalable Fault Localization for SystemC TLM Designs [p. 35]
Grover, A.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Grüttner, K.: Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking [p. 1167]
Gu, Z.: PT-AMC: Integrating Preemption Thresholds into Mixed-Criticality Scheduling [p. 141]
Guan, N.: FIFO Cache Analysis for WCET Estimation: A Quantitative Approach [p. 296]
Guerre, A.: ARTM: A Lightweight Fork-join Framework for Many-core Embedded Systems [p. 1510]
Guido, G.: Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes [p. 129]
Gunalp, O.: Self-aware Cyber-physical Systems and Applications in Smart Buildings and Cities [p. 1149]
Güntzel, J.L.: Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing [p. 1855]
Guo, J.: DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems [p. 380]; Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer [p. 859]
Gupta, P.: SlackProbe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology [p. 282]; Role of Design in Multiple Patterning: Technology Development, Design Enablement and Process Control [p. 314]
Gupta, R.: Utility-Aware Deferred Load Balancing in the Cloud Driven by Dynamic Pricing of Electricity [p. 262]; Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters [p. 541]; Hierarchically Focused Guardbanding: An Adaptive Approach to Mitigate PVT Variations and Aging [p. 1695]
Gupta, S.K.: Using Explicit Output Comparisons for Fault Tolerant Scheduling (FTS) on Modern High-Performance Processors [p. 927]; Trojan Detection via Delay Measurements: A New Approach to Select Paths and Vectors to Maximize Effectiveness and Minimize Cost [p. 1265]
Gurgen, L.: Self-aware Cyber-physical Systems and Applications in Smart Buildings and Cities [p. 1149]
Guth, C.: Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing [p. 1855]
Guthmuller, E.: 3D Integration for Power-Efficient Computing [p. 779]

Hagemeyer, J.: On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems [p. 717]
Hakim, N.: Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]
Hamdioui, S.: Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes [p. 129]; Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? [p. 1251]
Hameed, F.: Adaptive Cache Management for a Combined SRAM and DRAM Cache Hierarchy for Multi-cores [p. 77]
Han, K.: Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication [p. 1579]
Han, Y.: SmartCap: User Experience-Oriented Power Adaptation for Smartphone's Application Processor [p. 57]
Hank, P.: Automotive Ethernet: In-vehicle Networking and Smart Mobility [p. 1735]; Smart, Connected and Mobile: Architecting Future Electric Mobility Ecosystems [p. 1740]
Hara-Azumi, Y.: Instruction-Set Extension under Process Variation and Aging Effects [p. 182]
Haratsch, E.: Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling [p. 1285]
Harris, W.R.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]
Hasan, O.: Formal Analysis of Steady State Errors in Feedback Control Systems Using HOL-Light [p. 1423]
Haugou, G.: Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]
He, X.: Utilizing Voltage-Frequency Islands in C-to-RTL Synthesis for Streaming Applications [p. 992]
Heidmann, N.: Reliability Analysis for Integrated Circuit Amplifiers Used in Neural Measurement Systems [p. 713]
Heine, D.: Configurability in IP Subsystems: Baseband Examples [p. 163]
Heisswolf, J.: Hybrid Interconnect Design for Heterogeneous Hardware Accelerators [p. 843]
Heitz, M.: Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]
Hellwege, N.: Reliability Analysis for Integrated Circuit Amplifiers Used in Neural Measurement Systems [p. 713]
Helmstetter, C.: Fast and Accurate TLM Simulations Using Temporal Decoupling for FIFO-based Communications [p. 1185]
Henkel, J.: Self-Adaptive Hybrid Dynamic Power Management for Many-Core Systems [p. 51]; Adaptive Cache Management for a Combined SRAM and DRAM Cache Hierarchy for Multi-cores [p. 77]; An H.264 Quad-FullHD Low-Latency Intra Video Encoder [p. 115]; Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder [p. 125]; Fast and Accurate Cache Modeling in Source-Level Simulation of Embedded Software [p. 587]; Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding [p. 665]; CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]; DANCE: Distributed Application-aware Node Configuration Engine in Shared Reconfigurable Sensor Networks [p. 839]; Pipelets: Self-Organizing Software Pipelines for Many-Core Architctures [p. 1516]; Leveraging Variable Function Resilience for Selective Software Reliability on Unreliable Hardware [p. 1759]
Hermida, R.: Multispeculative Additive Trees in High-Level Synthesis [p. 188]
Herndl, T.: Alternative Power Supply Concepts for Self-Sufficient Wireless Sensor Nodes by Energy Harvesting [p. 481]
Herrero, E.: Capturing Vulnerability Variations for Register Files [p. 1468]
Hillebrecht, S.: Accurate QBF-based Test Pattern Generation in Presence of Unknown Values [p. 436]
Hills, G.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Hiromoto, M.: Hot-Swapping Architecture with Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array [p. 535]
Hoeffmann, J.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Hofer, G.: Alternative Power Supply Concepts for Self-Sufficient Wireless Sensor Nodes by Energy Harvesting [p. 481]
Hofmann, K.: Fast and Optimized Task Allocation Method for Low Vertical Link Density 3-Dimensional Networks-on-Chip Based Many Core Systems [p. 1777]
Hollstein, T.: Fast and Optimized Task Allocation Method for Low Vertical Link Density 3-Dimensional Networks-on-Chip Based Many Core Systems [p. 1777]
Holweg, G.: Alternative Power Supply Concepts for Self-Sufficient Wireless Sensor Nodes by Energy Harvesting [p. 481]
Hong, S.: AVICA: An Access-time Variation Insensitive L1 Cache Architecture [p. 65]
Hong, T.: Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]
Hsiao, M.: LFSR Seed Computation and Reduction Using SMT-Based Fault-Chaining [p. 1071]; A Novel Concurrent Cache-friendly Binary Decision Diagram Construction for Multi-core Platforms [p. 1427]
Hsiao, S.-W.: Periodic Jitter and Bounded Uncorrelated Jitter Decomposition Using Incoherent Undersampling [p. 1667]
Hsieh, C.-M.: DANCE: Distributed Application-aware Node Configuration Engine in Shared Reconfigurable Sensor Networks [p. 839]
Hsu, B.-N.: Fault Detection, Real-Time Error Recovery, and Experimental Demonstration for Digital Microfluidic Biochips [p. 559]
Hu, J.: Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems [p. 599]
Hu, K.: Fault Detection, Real-Time Error Recovery, and Experimental Demonstration for Digital Microfluidic Biochips [p. 559]
Hu, K.: High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization [p. 1271]
Hu, S.: CATALYST: Planning Layer Directives for Effective Design Closure [p. 1873]
Hu, X.: Orchestrator: A Low-cost Solution to Reduce Voltage Emergencies for Multi-threaded Applications [p. 208]
Hu, X.S.: Utilizing Voltage-Frequency Islands in C-to-RTL Synthesis for Streaming Applications [p. 992]; Enhancing Multicore Reliability through Wear Compensation in Online Assignment and Scheduling [p. 1373]; Systematic Design of Nanomagnet Logic Circuits [p. 1795]
Hu, Y.: Orchestrator: A Low-cost Solution to Reduce Voltage Emergencies for Multi-threaded Applications [p. 208]; Capturing Post-Silicon Variation by Layout-aware Path-delay Testing [p. 288]
Huang, C,-Yi: On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]
Huang, C.-C.: Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming [p. 1701]
Huang, K.: Energy Optimization with Worst-Case Deadline Guarantee for Pipelined Multiprocessor Systems [p. 45]
Huang, Ke: Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests [p. 553]
Huang, P.-Y.: NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs [p. 1379]
Huang, S.-H.: Co-Synthesis of Data Paths and Clock Control Paths for Minimum-Period Clock Gating [p. 1831]
Huang, X.: A Fast and Efficient DFT for Test and Diagnosis of Power Switches in SoCs [p. 1089]
Huang, Y.-H.: A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations [p. 643]
Huang, Z.: A Dynamic Self-Adaptive Correction Method for Error Resilient Application [p. 943]

Iannaccone, G.: A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis under Process Variation [p. 1789]
Idgunji, S.: Memory Array Protection: Check on Read or Check on Write? [p. 214]
Ienne, P.: Accuracy vs Speed Tradeoffs in the Estimation of Fixed-Point Errors on Linear Time-Invariant Systems [p. 15]; Phoenix: Reviving MLC Blocks as SLC to Extend NAND Flash Devices Lifetime [p. 226]; An EDA-Friendly Protection Scheme against Side-Channel Attacks [p. 410]; Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]
Im, S.: Optimized Scheduling of Multi-IMA Partitions with Exclusive Region for Synchronized Real- Time Multi-Core Systems [p. 970]
Imagawa, T.: A Cost-Effective Selective TMR for Heterogeneous Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis [p. 701]
Irick, K.: Saliency Aware Display Power Management [p. 1203]
Iyer, S.: Mempack: An Order of Magnitude Reduction in the Cost, Risk, and Time for Memory Compiler Certification [p. 1490]

Jafari, R.: An Ultra-Low Power Hardware Accelerator Architecture for Wearable Computers Using Dynamic Time Warping [p. 913]
Jahn, J.: Pipelets: Self-Organizing Software Pipelines for Many-Core Architctures [p. 1516]
Jain, J.: Optimizing BDDs for Time-Series Dataset Manipulation [p. 1018]
Jain, R.: Automated Determination of Top Level Control Signals [p. 509]
Jan, M.: Time- and Angle-triggered Real-time Kernel [p. 1060]
Janin, Y.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
Jeong, Y.: Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs [p. 1575]
Jerger, N. E.: A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches [p. 89]
Jézéquel, M.: Parameterized Area-efficient Multi-standard Turbo Decoder [p. 109]; Statically-scheduled Application-specific Processor Design: A Case-study on MMSE MIMO Equalization [p. 677]
Jha, S.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]
Ji, W.: A Work-Stealing Scheduling Framework Supporting Fault Tolerance [p. 695]
Jiang, K.: Optimization of Secure Embedded Systems with Dynamic Task Sets [p. 1765]
Jimenez, X.: Phoenix: Reviving MLC Blocks as SLC to Extend NAND Flash Devices Lifetime [p. 226]
Jinglin, S.: A 100 GOPS ASP Based Baseband Processor for Wireless Communication [p. 121]
Johann, M. O.: Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing [p. 1855]
John, R.: Smart, Connected and Mobile: Architecting Future Electric Mobility Ecosystems [p. 1740]; Semiconductor Technologies for Smart Mobility Management [p. 1749]
Jooya, A.: Using Synchronization Stalls in Power-aware Accelerators [p. 400]
Jose, J.: DeBAR: Deflection Based Adaptive Router with Minimal Buffering [p. 1583]
Joshi, S.: A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits [p. 1056]
Juan, D.-C.: SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model [p. 354]
Juan, H.: A 100 GOPS ASP Based Baseband Processor for Wireless Communication [p. 121]
Jung, W.: Runtime Power Estimation of Mobile AMOLED Displays [p. 61]

Kae-Nune, N.: Qualification and Testing Process to Implement Anti-Counterfeiting Technologies into IC Packages [p. 1131]
Kahng, A. B.: Active-Mode Leakage Reduction with Data-Retained Power Gating [p. 1209]; Impact of Adaptive Voltage Scaling on Aging-Aware Signoff [p. 1683]; Enhanced Metamodeling Techniques for High-Dimensional IC Design Estimation Problems [p. 1861]
Kalbarczyk, Z. T.: Reliability Analysis Reloaded: How Will We Survive? [p. 358]
Kalligeros, E.: Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports [p. 344]
Kamal, M.: An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications [p. 350]
Kang, S.: Active-Mode Leakage Reduction with Data-Retained Power Gating [p. 1209]
Kappel, R.: Alternative Power Supply Concepts for Self-Sufficient Wireless Sensor Nodes by Energy Harvesting [p. 481]
Karri, R.: Is Split Manufacturing Secure? [p. 1259]
Karsli, B.: Exploiting Replicated Checkpoints for Soft Error Detection and Correction [p. 1494]
Kasapaki, E.: An Area-efficient Network Interface for a TDM-based Network-on-Chip [p. 1044]
Kastner, R.: A Practical Testing Framework for Isolating Hardware Timing Channels [p. 1281]
Katoen, J.-P.: Model-Based Energy Optimization of Automotive Control Systems [p. 761]
Kaushik, A.M.: On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]
Kavousianos, X.: Testing for SoCs with Advanced Static and Dynamic Power-Management Capabilities [p. 737]
Kawoosa, M.: Towards Adaptive Test of Multi-core RF SoCs [p. 743]
Kazmierski, T.J.: DoE-based Performance Optimization of Energy Management in Sensor Nodes Powered by Tunable Energy-Harvesters [p. 484]
Keinert, J.: Intuitive ECO Synthesis for High Performance Circuits [p. 1002]
Kershaw, D.: MALEC: A Multiple Access Low Energy Cache [p. 368]
Khan, M.U.K.: An H.264 Quad-FullHD Low-Latency Intra Video Encoder [p. 115]; Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder [p. 125]
Khan, O.: MARTHA: Architecture for Control and Emulation of Power Electronics and Smart Grid Systems [p. 519]
Khatri, S.P.: Exploring Topologies for a Source-synchronous Ring-based Network-on-Chip [p. 1026]; Crosstalk Avoidance Codes for 3D VLSI [p. 1673]
Kiaei, S.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Kiamehr, S.: Instruction-Set Extension under Process Variation and Aging Effects [p. 182]; Incorporating the Impacts of Workload-Dependent Runtime Variations into Timing Analysis [p. 1022]
Kim, D.: Runtime Power Estimation of Mobile AMOLED Displays [p. 61]
Kim, J.: Capital Cost-Aware Design and Partial Shading-Aware Architecture Optimization of a Reconfigurable Photovoltaic System [p. 909]
Kim, J.: Configurability in IP Subsystems: Baseband Examples [p. 163]
Kim, J.: An Integrated Approach for Managing the Lifetime of Flash-Based SSDs [p. 1522]
Kim, J.: Correlation-Aware Virtual Machine Allocation for Energy-Efficient Datacenters [p. 1345]
Kim, J.-E.: Optimized Scheduling of Multi-IMA Partitions with Exclusive Region for Synchronized Real- Time Multi-Core Systems [p. 970]; Holistic Design Parameter Optimization of Multiple Periodic Resources in Hierarchical Scheduling [p. 1313]
Kim, K.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Kim, M.: ClockPUF: Physical Unclonable Functions Based on Clock Networks [p. 422]
Kim, S.: AVICA: An Access-time Variation Insensitive L1 Cache Architecture [p. 65]
Kim, T.: An Integrated Approach for Managing the Lifetime of Flash-Based SSDs [p. 1522]
Kinsy, M.A.: MARTHA: Architecture for Control and Emulation of Power Electronics and Smart Grid Systems [p. 519]
Kizu, T.: A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Klawitter, S.: Timing Analysis of Multi-Mode Applications on AUTOSAR Conform Multi-Core Systems [p. 302]
Kloos, J.: Supervisor Synthesis for Controller Upgrades [p. 1105]
Knoll, A.: Energy Optimization with Worst-Case Deadline Guarantee for Pipelined Multiprocessor Systems [p. 45]; Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis [p. 308]
Koc, F.: Exploiting Replicated Checkpoints for Soft Error Detection and Correction [p. 1494]
Kocabas, Ü.: Memristor PUFs: A New Generation of Memory-based Physically Unclonable Functions [p. 428]
Kochte, M.A.: Accurate QBF-based Test Pattern Generation in Presence of Unknown Values [p. 436]
Kodaka, T.: Development of Low Power Many-Core SoC for Multimedia Applications [p. 773]; A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Koeberl, P.: Memristor PUFs: A New Generation of Memory-based Physically Unclonable Functions [p. 428]
Kondratyev, A.: Share with Care: A Quantitative Evaluation of Sharing Approaches in High-level Synthesis [p. 1547]
Korf, S.: On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems [p. 717]
Kornaros, G.: From Embedded Multi-core SoCs to Scale-out Processors [p. 947]
Kosmidis, L.: A Cache Design for Probabilistically Analysable Real-time Systems [p. 513]; Probabilistic Timing Analysis on Conventional Cache Designs [p. 603]
Koushanfar, F.: ClockPUF: Physical Unclonable Functions Based on Clock Networks [p. 422]; High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization [p. 1271]
Kozyrakis, C.: Resource Efficient Computing for Warehouse-scale Datacenters [p. 1351]
Kreiter, A.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Kriebel, F.: Leveraging Variable Function Resilience for Selective Software Reliability on Unreliable Hardware [p. 1759]
Kriegel, K.: Semiconductor Technologies for Smart Mobility Management [p. 1749]
Krishna, T.: SMART: A Single-Cycle Reconfigurable NoC for SoC Applications [p. 338]
Krishnaswamy, S.: Intuitive ECO Synthesis for High Performance Circuits [p. 1002]
Kuehlmann, A.: QF_BV Model Checking with Property Directed Reachability [p. 791]
Kuhlmann, M.: Towards a Generic Verification Methodology for System Models [p. 1193]
Kumar, Y.B., C.: Towards Adaptive Test of Multi-core RF SoCs [p. 743]
Kumar, A.: Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems [p. 689]; Communication and Migration Energy Aware Design Space Exploration for Multicore Systems with Intermittent Faults [p. 1631]
Kumar, J.A.: Runtime Verification of Nonlinear Analog Circuits Using Incremental Time-Augmented RRT Algorithm [p. 21]
Kumar, K.: DeBAR: Deflection Based Adaptive Router with Minimal Buffering [p. 1583]
Kumar, P.: A Satisfiability Approach to Speed Assignment for Distributed Real-Time Systems [p. 749]
Kumar, R.: Crosstalk Avoidance Codes for 3D VLSI [p. 1673]
Kundur, V.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Kupp, N.: Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests [p. 553]
Kursun, E.: Thermomechanical Stress-Aware Management for 3D IC Designs [p. 1255]

Lagraa, S.: Data Mining MPSoC Simulation Traces to Identify Concurrent Memory Access Patterns [p. 755]
Lai, L.: SlackProbe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology [p. 282]
Landau, L.: Wireless Interconnect for Board and Chip Level [p. 958]
Lang, W.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Lavagno, L.: Share with Care: A Quantitative Evaluation of Sharing Approaches in High-level Synthesis [p. 1547]
Le Beux, S.: Optical Look Up Table [p. 873]
Le Coz, J.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Le Guernic, P.: Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]
Le, H.M.: Scalable Fault Localization for SystemC TLM Designs [p. 35]
Leblebici, Y.: Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]; Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]; 3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling [p. 1241]
Lecomte, S.: SoC Low-Power Practices for Wireless Applications [p. 778]
Lederberger, M.: Correlation-Aware Virtual Machine Allocation for Energy-Efficient Datacenters [p. 1345]
Ledochowitsch, P.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Leduc, P.: PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future? [p. 1526]
Lee, C.-H.: Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming [p. 1701]
Lee, C.-J.: Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming [p. 1701]
Lee, C.-R.: A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations [p. 643]
Lee, C.-S.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Lee, J.: Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs [p. 1575]; Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication [p. 1579]
Lee, S.: An Integrated Approach for Managing the Lifetime of Flash-Based SSDs [p. 1522]
Lee, W.: Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT [p. 242]
Lee, Y.-M.: NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs [p. 1379]
Lefter, M.: Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? [p. 1251]
Legrand, A.: Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]
Lehner, W.: Energy-Efficient In-Memory Database Computing [p. 470]
Lehner, W.: Energy-Efficient In-Memory Database Computing [p. 470]
Lemaire, R.: HW-SW Integration for Energy-Efficient/Variability-Aware Computing [p. 607]
Lepley, T.: Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]
Lesperance, N.: Mutation Analysis with Coverage Discounting [p. 31]
Letartre, X.: Optical Look Up Table [p. 873]
Lhuillier, Y.: An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the STHORM Many-Core Architecture [p. 531]; ARTM: A Lightweight Fork-join Framework for Many-core Embedded Systems [p. 1510]
Li, H.: DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems [p. 380]; STT-RAM Designs Supporting Dual-Port Accesses [p. 853]
Li, J.: Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM [p. 1247]
Li, J.: ClockPUF: Physical Unclonable Functions Based on Clock Networks [p. 422]
Li, J.: Multi-level Phase Analysis for Sampling Simulation [p. 649]
Li, M.: A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug [p. 485]
Li, Q.: Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM [p. 1247]
Li, Q.: Machine Learning-based Anomaly Detection for Post-silicon Bug Diagnosis [p. 491]
Li, S.: High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]
Li, S.: Utilizing Voltage-Frequency Islands in C-to-RTL Synthesis for Streaming Applications [p. 992]
Li, S.: DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems [p. 380]
Li, T.: CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]
Li, X.: SmartCap: User Experience-Oriented Power Adaptation for Smartphone's Application Processor [p. 57]; Orchestrator: A Low-cost Solution to Reduce Voltage Emergencies for Multi-threaded Applications [p. 208]; Capturing Post-Silicon Variation by Layout-aware Path-delay Testing [p. 288]
Li, Y.: Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]
Li, Y.Z.: DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems [p. 380]
Li, Z.: Optical Look Up Table [p. 873]
Li, Z.: CATALYST: Planning Layer Directives for Effective Design Closure [p. 1873]
Liang, H.: A Dynamic Self-Adaptive Correction Method for Error Resilient Application [p. 943]
Lifa, A.: Dynamic Configuration Prefetching Based on Piecewise Linear Prediction [p. 815]
Lin, B.: Enhanced Metamodeling Techniques for High-Dimensional IC Design Estimation Problems [p. 1861]
Lin, C.-C.: PAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Design [p. 1849]
Lin, C.-T.: Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming [p. 1701]
Lin, D.: Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]
Lin, R.-B.: Slack Budgeting and Slack to Length Converting for Multi-Bit Flip-Flop Merging [p. 1837]
Lin, X.: Optimal Control of a Grid-Connected Hybrid Electrical Energy Storage System for Homes [p. 881]; Capital Cost-Aware Design and Partial Shading-Aware Architecture Optimization of a Reconfigurable Photovoltaic System [p. 909]
Lindwer, M.: High-performance Imaging Subsystems and Their Integration in Mobile Devices [p. 170]
Lisherness, P.: Mutation Analysis with Coverage Discounting [p. 31]
Liu, C.-N.J.: Automatic Circuit Sizing Technique for the Analog Circuits with Flexible TFTs Considering Process Variation and Bending Effects [p. 1458]
Liu, H.: Radar Signature in Multiple Target Tracking System for Driver Assistant Application [p. 887]
Liu, S.S.-Y.: Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming [p. 1701]; A Network-Flow Based Algorithm for Power Density Mitigation at Post-Placement Stage [p. 1707]
Liu, X.-X.: A Power-Driven Thermal Sensor Placement Algorithm for Dynamic Thermal Management [p. 1215]
Liu, Y.: SPaC: A Segment-based Parallel Compression for Backup Acceleration in Nonvolatile Processors [p. 865]; Utilizing Voltage-Frequency Islands in C-to-RTL Synthesis for Streaming Applications [p. 992]
Liu, Y.-Y.: Dual-addressing Memory Architecture for Two-dimensional Memory Access Patterns [p. 71]
Livramento, V.S.: Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing [p. 1855]
Liyanage, L.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Loiacono, C.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]; Optimization Techniques for Craig Interpolant Compaction in Unbounded Model Checking [p. 1417]
Lombardot, A.: A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits [p. 1056]
López, P.: Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]
Lorente, V.: Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]
Lorquet, V.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
Lotfian, R.: An Ultra-Low Power Hardware Accelerator Architecture for Wearable Computers Using Dynamic Time Warping [p. 913]
Lu, C.-C.: Slack Budgeting and Slack to Length Converting for Multi-Bit Flip-Flop Merging [p. 1837]
Lu, G.-R.: Automatic Circuit Sizing Technique for the Analog Circuits with Flexible TFTs Considering Process Variation and Bending Effects [p. 1458]
Lu, K.: Fast Cache Simulation for Host-Compiled Simulation of Embedded Software [p. 637]; Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts [p. 1161]; A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot [p. 1331]
Lu, S.(J.): Run-time Probabilistic Detection of Miscalibrated Thermal Sensors in Many-core Systems [p. 1395]
Lu, Y.: Retiming for Soft Error Minimization under Error-Latching Window Constraints [p. 1008]
Ludwig, F.: Low Complexity QR-Decomposition Architecture Using the Logarithmic Number System [p. 97]
Lukasiewycz, M.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]; An Approach for Redundancy in FlexRay Networks Using FPGA Partial Reconfiguration [p. 721]; Priority Assignment for Event-triggered Systems Using Mathematical Programming [p. 982]
Luo, R.-G.: A Network-Flow Based Algorithm for Power Density Mitigation at Post-Placement Stage [p. 1707]
Lv, M.: FIFO Cache Analysis for WCET Estimation: A Quantitative Approach [p. 296]
Lyras, G.: Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems [p. 655]

Ma, Y.: Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]
Macii, E.: HW-SW Integration for Energy-Efficient/Variability-Aware Computing [p. 607]; A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions [p. 877]
Mader, R.: Sufficient Real-Time Analysis for an Engine Control Unit with Constant Angular Velocities [p. 1335]
Madison, A.: Fault Detection, Real-Time Error Recovery, and Experimental Demonstration for Digital Microfluidic Biochips [p. 559]
Magarshack, P.: UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-efficiency [p. 952]
Magno, M.: A Survy of Multi-Source Energy Harvesting Systems [p. 905]
Mahapatra, R.N.: Exploring Topologies for a Source-synchronous Ring-based Network-on-Chip [p. 1026]
Maharbiz, M.M.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Mai, K.: Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling [p. 1285]
Majumdar, R.: Supervisor Synthesis for Controller Upgrades [p. 1105]
Makris, Y.: Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests [p. 553]; AVF-driven Parity Optimization for MBU Protection of In-core Memory Arrays [p. 1480]
Malburg, J.: Tuning Dynamic Data Flow Analysis to Support Design Understanding [p. 1179]
Malik, S.: Extracting Useful Computation from Error-Prone Processors for Streaming Applications [p. 202]; Reverse Engineering Digital Circuits Using Functional Analysis [p. 1277]
Mandal, A.: Exploring Topologies for a Source-synchronous Ring-based Network-on-Chip [p. 1026]
Mandon, S.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Maneglia, Y.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Maniatakos, M.: AVF-driven Parity Optimization for MBU Protection of In-core Memory Arrays [p. 1480]
Marangozova-Martin, V.: Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]
Maraninchi, F.: System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal Management [p. 1609]
Marculescu, D.: Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors [p. 39]; SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model [p. 354]
Marculescu, R.: SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model [p. 354]; Closed-Loop Control for Power and Thermal Management in Multi-core Processors: Formal Methods and Industrial Practice [p. 1879]
Margull, U.: Sufficient Real-Time Analysis for an Engine Control Unit with Constant Angular Velocities [p. 1335]
Maric, B.: Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes [p. 917]
Maricau, E.: Stochastic Degradation Modeling and Simulation for Analog Integrated Circuits in Nanometer CMOS [p. 326]
Markov, I L.: ClockPUF: Physical Unclonable Functions Based on Clock Networks [p. 422]
Marnari, A.: A Parallel Fast Transform-Based Preconditioning Approach for Electrical-Thermal Co- Simulation of Power Delivery Networks [p. 1689]
Marongiu, A.: Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters [p. 541]; Enabling Fine-Grained OpenMP Tasking on Tightly-Coupled Shared Memory Clusters [p. 1504]
Marques-Silva, J.: Core Minimization in SAT-based Abstraction [p. 1411]
Martin, F.: Configurable IO Integration to Reduce System-on-Chip Time to Market: DDR, PCIe Examples [p. 169]
Martin, G.: Configurability in IP Subsystems: Baseband Examples [p. 163]
Martonosi, M.: Extracting Useful Computation from Error-Prone Processors for Streaming Applications [p. 202]
Marzani, A.: Design of an Ultra-low Power Device for Aircraft Structural Health Monitoring [p. 1127]
Masrur, A.: Compositional Analysis of Switched Ethernet Topologies [p. 1099]; Multirate Controller Design for Resource- and Schedule-Constrained Automotive ECUs [p. 1123]
Massey, T.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Mathew, J.: A Fast and Efficient DFT for Test and Diagnosis of Power Switches in SoCs [p. 1089]
Matsumoto, N.: A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Mazzeo, A.: Efficient and Scalable OpenMP-based System-level Design [p. 988]
Mazzocca, N.: Efficient and Scalable OpenMP-based System-level Design [p. 988]
Méhaut, J.-F.: Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]
Meijer, I.: Roadmap towards Ultimately-Efficient Zeta-Scale Datacenters [p. 1339]
Meiklejohn, S.: A Practical Testing Framework for Isolating Hardware Timing Channels [p. 1281]
Melpignano, D.: Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]
Memik, S.O.: Multispeculative Additive Trees in High-Level Synthesis [p. 188]
Mendis, J.M.: Multispeculative Additive Trees in High-Level Synthesis [p. 188]
Mendler, M.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]
Menhorn, B.: Event Density Analysis for Event Triggered Control Systems [p. 1111]
Mercer, S.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]
Merli, D.: Comprehensive Analysis of Software Countermeasures against Fault Attacks [p. 404]
Merrett, G.: DoE-based Performance Optimization of Energy Management in Sensor Nodes Powered by Tunable Energy-Harvesters [p. 484]; A Survy of Multi-Source Energy Harvesting Systems [p. 905]
Meyer, M.: Share with Care: A Quantitative Evaluation of Sharing Approaches in High-level Synthesis [p. 1547]
Michael, M.K.: AVF-driven Parity Optimization for MBU Protection of In-core Memory Arrays [p. 1480]
Michaels, T.: Sensitivity Analysis for Arbitrary Activation Patterns in Real-time Systems [p. 135]
Michel, B.: Roadmap towards Ultimately-Efficient Zeta-Scale Datacenters [p. 1339]
Milano, M.: Sustainable Energy Policies: Research Challenges and Opportunities [p. 1143]
Miller, M.: Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT [p. 1442]
Milojevic, D.: PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future? [p. 1526]
Milor, L.: System-Level Modeling and Microprocessor Reliability Analysis for Backend Wearout Mechanisms [p. 1615]
Miro-Panades, I.: 3D Integration for Power-Efficient Computing [p. 779]
Miryrala, S.: A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions [p. 877]
Mishchenko, A.: A Semi-Canonical Form for Sequential AIGs [p. 797]; GLA: Gate-Level Abstraction Revisited [p. 1399]; Core Minimization in SAT-based Abstraction [p. 1411]
Mishra, B.: A Sub-μA Power Management Circuit in 0.18μm CMOS for Energy Harvesters [p. 1197]
Mishra, V.: Placement Optimization of Power Supply Pads Based on Locality [p. 1655]
Mitcheson, P.D.: Adaptable, High Performance Energy Harvesters [p. 482]
Mitra, S.: Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]; Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Mittal, R.: Towards Adaptive Test of Multi-core RF SoCs [p. 743]
Miwa, S.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Miyamori, T.: Development of Low Power Many-Core SoC for Multimedia Applications [p. 773]; A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Mock, R.: Interactions of Large Scale EV Mobility and Virtual Power Plants [p. 1725]
Mohana, Y.: Statically-scheduled Application-specific Processor Design: A Case-study on MMSE MIMO Equalization [p. 677]
Mohanram, K.: Mempack: An Order of Magnitude Reduction in the Cost, Risk, and Time for Memory Compiler Certification [p. 1490]
Molina, M.C.: Multispeculative Additive Trees in High-Level Synthesis [p. 188]
Moll, F.: Design and Implementation of an Adaptive Proactive Reconfiguration Technique for SRAM Caches [p. 1303]
Monat, C.: Optical Look Up Table [p. 873]
Monchiero, M.: Capturing Vulnerability Variations for Register Files [p. 1468]
Montazeri, M.: A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions [p. 877]
Mony, H.: GLA: Gate-Level Abstraction Revisited [p. 1399]
Moolenaar, D.: Configurability in IP Subsystems: Baseband Examples [p. 163]
Moraes, F.: Topology-Agnostic Fault-Tolerant NoC Routing Method [p. 1595]
Moreno, J.: Ultra-Low Power: An EDA Challenge [p. 483]
Moritz, G.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Moscatelli, A.: Smart, Connected and Mobile: Architecting Future Electric Mobility Ecosystems [p. 1740]
Moshovos, A.: A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches [p. 89]; Characterizing the Performance Benefits of Fused CPU/GPU Systems Using FusionSim [p. 685]
Motika, C.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]
Moy, M.: Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach [p. 9]; Fast and Accurate TLM Simulations Using Temporal Decoupling for FIFO-based Communications [p. 1185]; System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal Management [p. 1609]
Moya, J.: Leakage and Temperature Aware Server Control for Improving Energy Efficiency in Data Centers [p. 266]
Müller, S.: Automotive Ethernet: In-vehicle Networking and Smart Mobility [p. 1735]
Mueller-Gritschneder, D.: Fast Cache Simulation for Host-Compiled Simulation of Embedded Software [p. 637]; Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts [p. 1161]; A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot [p. 1331]; A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis [p. 1783]
Mukhopadhyay, S.: Perceptual Quality Preserving SRAM Architecture for Color Motion Pictures [p. 103]
Muller, R.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Muradore, R.: Model Predictive Control over Delay-Based Differentiated Services Control Networks [p. 1117]
Murray, J.: Energy-Efficient Multicore Chip Design through Cross-Layer Approach [p. 725]
Murugappa, P.: Parameterized Area-efficient Multi-standard Turbo Decoder [p. 109]
Mushtaq, H.: Efficient Software-Based Fault Tolerance Approach on Multicore Platforms [p. 921]
Mutlu, O.: Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling [p. 1285]
Mutyam, M.: DeBAR: Deflection Based Adaptive Router with Minimal Buffering [p. 1583]

Naga, N.S.J.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Nahas, J.: Systematic Design of Nanomagnet Logic Circuits [p. 1795]
Nakada, T.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Nakamura, H.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Nakamura, Y.: Hot-Swapping Architecture with Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array [p. 535]
Nalla, P.: GLA: Gate-Level Abstraction Revisited [p. 1399]
Narayanan, V.: Saliency Aware Display Power Management [p. 1203]; On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]
Nassif, S.: Incorporating the Impacts of Workload-Dependent Runtime Variations into Timing Analysis [p. 1022]
Nath, S.: Enhanced Metamodeling Techniques for High-Dimensional IC Design Estimation Problems [p. 1861]
Navas, B.: The RecoBlock SoC Platform: A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks [p. 833]
Nayak, B.: DeBAR: Deflection Based Adaptive Router with Minimal Buffering [p. 1583]
Ndreu, L.: Memory Array Protection: Check on Read or Check on Write? [p. 214]
Negrean, M.: Timing Analysis of Multi-Mode Applications on AUTOSAR Conform Multi-Core Systems [p. 302]; Formal Analysis of Sporadic Bursts in Real-Time Systems [p. 767]
Neukirchner, M.: Sensitivity Analysis for Arbitrary Activation Patterns in Real-time Systems [p. 135]
Niaki, S.H.A.: An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems [p. 27]
Niar, S.: Radar Signature in Multiple Target Tracking System for Driver Assistant Application [p. 887]
Nicolaidis, M.: Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes [p. 129]
Nicolescu, G.: Explicit Transient Thermal Simulation of Liquid-Cooled 3D ICs [p. 1385]
Nicopoulos, C.: Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports [p. 344]
Niemier, M.: Systematic Design of Nanomagnet Logic Circuits [p. 1795]
Nikdast, M.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Nikolaou, P.: Memory Array Protection: Check on Read or Check on Write? [p. 214]
Noel, J.P.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Noguchi, H.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Noll, T.: Model-Based Energy Optimization of Automotive Control Systems [p. 761]
Noll, T.G.: High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]
Nomura, K.: D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]
Novo, D.: Accuracy vs Speed Tradeoffs in the Estimation of Fixed-Point Errors on Linear Time-Invariant Systems [p. 15]; Phoenix: Reviving MLC Blocks as SLC to Extend NAND Flash Devices Lifetime [p. 226]; An EDA-Friendly Protection Scheme against Side-Channel Attacks [p. 410]
Nowick, S.M.: A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems [p. 332]
Nowroz, A.N.: High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization [p. 1271]
Nugteren, C.: Future of GPGPU Micro-Architectural Parameters [p. 392]

O'Connor, I.: Optical Look Up Table [p. 873]
Oberg, J.: A Practical Testing Framework for Isolating Hardware Timing Channels [p. 1281]
Öberg, J.: The RecoBlock SoC Platform: A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks [p. 833]
Oboril, F.: MTTF-Balanced Pipeline Design [p. 270]
O'Brien, O.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]
Ochi, H.: Hot-Swapping Architecture with Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array [p. 535]; A Cost-Effective Selective TMR for Heterogeneous Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis [p. 701]
Ojail, M.: ARTM: A Lightweight Fork-join Framework for Many-core Embedded Systems [p. 1510]
Olivo, J.: Electronic Implants: Power Delivery and Management [p. 1540]
Orailoglu, A.: Profit Maximization through Process Variation Aware High Level Synthesis with Speed Binning [p. 176]
Ottavi, M.: Error Detection in Ternary CAMs Using Bloom Filters [p. 1474]
Oudin, P.: Time- and Angle-triggered Real-time Kernel [p. 1060]
Ozel, M.K.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Özer, E.: Memory Array Protection: Check on Read or Check on Write? [p. 214]
Ozev, S.: Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits [p. 292]; Fault Analysis and Simulation of Large Scale Industrial Mixed-Signal Circuits [p. 565]; Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]

Paci, G.: Perpetual and Low-cost Power Meter for Monitoring Residential and Industrial Appliances [p. 1155]
Palena, M.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]
Palermo, G.: A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization [p. 659]; Thermal-Aware Datapath Merging for Coarse-Grained Reconfigurable Processors [p. 1649]
Palit, I.: Systematic Design of Nanomagnet Logic Circuits [p. 1795]
Pan, P.-C.: PAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Design [p. 1849]
Pan, X.: Ultra-Low Power: An EDA Challenge [p. 483]
Panda, P.R.: Space Sensitive Cache Dumping for Post-silicon Validation [p. 497]
Pande, P.: Energy-Efficient Multicore Chip Design through Cross-Layer Approach [p. 725]
Paone, E.: Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]
Papadopoulou, M.: A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches [p. 89]
Papanikolaou, A.: Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems [p. 655]
Parameswaran, S.: CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]; An Extremely Compact JPEG Encoder for Adaptive Embedded Systems [p. 1063]
Paredes, S.: Roadmap towards Ultimately-Efficient Zeta-Scale Datacenters [p. 1339]
Parekhji, R.A.: Towards Adaptive Test of Multi-core RF SoCs [p. 743]
Park, B.: Active-Mode Leakage Reduction with Data-Retained Power Gating [p. 1209]
Park, J.: Non-Speculative Double-Sampling Technique to Increase Energy-Efficiency in a High-Performance Processor [p. 254]
Park, J.-S.: An Integrated Approach for Managing the Lifetime of Flash-Based SSDs [p. 1522]
Park, S.: SMART: A Single-Cycle Reconfigurable NoC for SoC Applications [p. 338]; Optimal Control of a Grid-Connected Hybrid Electrical Energy Storage System for Homes [p. 881]; 40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS [p. 1637]
Pasini, P.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]
Pasricha, K.: Reverse Engineering Digital Circuits Using Functional Analysis [p. 1277]
Patel, H.D.: Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors [p. 933]; On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]
Paterna, F.: Mitigating Dark Silicon Problems Using Superlattice-based Thermoelectric Coolers [p. 1391]
Patti, D.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]
Paul, S.: Low Complexity QR-Decomposition Architecture Using the Logarithmic Number System [p. 97]; Reliability Analysis for Integrated Circuit Amplifiers Used in Neural Measurement Systems [p. 713]; Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Pawelzik, K.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Pedersen, M.R.: High-performance Imaging Subsystems and Their Integration in Mobile Devices [p. 170]
Pedram, M.: Creating a Sustainable Information and Communication Infrastructure [p. 2]; An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications [p. 350]; Optimal Control of a Grid-Connected Hybrid Electrical Energy Storage System for Homes [p. 881]; Capital Cost-Aware Design and Partial Shading-Aware Architecture Optimization of a Reconfigurable Photovoltaic System [p. 909]; Adaptive Thermal Management for Portable System Batteries by Forced Convection Cooling [p. 1225]; Reversible Logic Synthesis of k-Input, m-Output Lookup Tables [p. 1235]
Peh, L.-S.: SMART: A Single-Cycle Reconfigurable NoC for SoC Applications [p. 338]; 40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS [p. 1637]
Pelloux-Prayer, B.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Penders, J.: Addressing the Healthcare Cost Dilemma by Managing Health instead of Managing Illness - An Opportunity for Wearable Wireless Sensors [p. 1537]
Peng, Z.: Dynamic Configuration Prefetching Based on Piecewise Linear Prediction [p. 815]; Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees [p. 1093]; Optimization of Secure Embedded Systems with Dynamic Task Sets [p. 1765]
Perelli, A.: Design of an Ultra-low Power Device for Aircraft Structural Health Monitoring [p. 1127]
Pesseguier, S.: Qualification and Testing Process to Implement Anti-Counterfeiting Technologies into IC Packages [p. 1131]
Peters-Drolshagen, D.: Reliability Analysis for Integrated Circuit Amplifiers Used in Neural Measurement Systems [p. 713]; Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Petit, S.: Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]
Pétrot, F.: Data Mining MPSoC Simulation Traces to Identify Concurrent Memory Access Patterns [p. 755]
Peyrin, T.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]
Pham-Quoc, C.: Hybrid Interconnect Design for Heterogeneous Hardware Accelerators [p. 843]
Philippe, J.-M.: An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the STHORM Many-Core Architecture [p. 531]
Pigorsch, F.: Lemma Localization: A Practical Method for Downsizing SMT-Interpolants [p. 1405]
Pinuel, L.: Reducing Writes in Phase-Change Memory Environments by Using Efficient Cache Replacement Policies [p. 93]
Piriou, E.: A Fast and Accurate Methodology for Power Estimation and Reduction of Programmable Architectures [p. 1054]
Pistor, J.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Plesco, A.: Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA [p. 575]
Plosila, J.: CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems [p. 1048]; Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy [p. 1601]
Polian, I.: Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths [p. 448]
Pollex, V.: Sufficient Real-Time Analysis for an Engine Control Unit with Constant Angular Velocities [p. 1335]
Pomeranz, I.: On Candidate Fault Sets for Fault Diagnosis and Dominance Graphs of Equivalence Classes [p. 1083]
Poncino, M.: A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions [p. 877]
Pontarelli, S.: Error Detection in Ternary CAMs Using Bloom Filters [p. 1474]
Porcarelli, D.: Perpetual and Low-cost Power Meter for Monitoring Residential and Industrial Appliances [p. 1155]
Porrmann, M.: On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems [p. 717]
Poschmann, A.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]
Pouyan, P.: Design and Implementation of an Adaptive Proactive Reconfiguration Technique for SRAM Caches [p. 1303]
Pradhan, D.K.: A Fast and Efficient DFT for Test and Diagnosis of Power Switches in SoCs [p. 1089]
Pratab, D.: Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Puri, R.: Intuitive ECO Synthesis for High Performance Circuits [p. 1002]
Puzovic, N.: Experiences with Mobile Processors for Energy Efficient HPC [p. 464]

Qazi, M.: 40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS [p. 1637]
Qian, Z.: SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model [p. 354]
Qiu, Q.: User-Aware Energy Efficient Streaming Strategy for Smartphone Based Video Playback Applications [p. 258]
Qu, G.: Design and Implementation of a Group-based RO PUF [p. 416]
Quaglia, D.: Model Predictive Control over Delay-Based Differentiated Services Control Networks [p. 1117]
Quer, S.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]
Quiñones, E.: A Cache Design for Probabilistically Analysable Real-time Systems [p. 513]; Probabilistic Timing Analysis on Conventional Cache Designs [p. 603]
Quinton, S.: Sensitivity Analysis for Arbitrary Activation Patterns in Real-time Systems [p. 135]; Formal Analysis of Sporadic Bursts in Real-Time Systems [p. 767]

Rabaey, J.: PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead [p. 171]
Radhakrishnan, S.: CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]
Ragel, R.: CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]
Raghunathan, A.: Substitute-and-Simplify: A Unified Design Paradigm for Approximate and Quality Configurable Circuits [p. 1367]; DWM-TAPESTRI - An Energy Efficient All-Spin Cache Using Domain Wall Shift Based Writes [p. 1825]
Raghunathan, B.: Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors [p. 39]
Rahim, F.: A Fast and Accurate Methodology for Power Estimation and Reduction of Programmable Architectures [p. 1054]
Rahim, S.: A Fast and Accurate Methodology for Power Estimation and Reduction of Programmable Architectures [p. 1054]
Rahimi, A.: Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters [p. 541]; Hierarchically Focused Guardbanding: An Adaptive Approach to Mitigate PVT Variations and Aging [p. 1695]
Rajendran, J.: Is Split Manufacturing Secure? [p. 1259]
Rajovic, N.: Experiences with Mobile Processors for Energy Efficient HPC [p. 464]
Rákossy, Z.E.: Hot-Swapping Architecture with Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array [p. 535]
Rambo, E.A.: On-the-fly Verification of Memory Consistency with Concurrent Relaxed Scoreboards [p. 631]
Ramini, L.: Contrasting Wavelength-Routed Optical NoC Topologies for Power-Efficient 3D-Stacked Multicore Processors Using Physical-Layer Analysis [p. 1589]
Ramirez, A.: Experiences with Mobile Processors for Energy Efficient HPC [p. 464]
Ramírez, T.: Capturing Vulnerability Variations for Register Files [p. 1468]
Rao, W.: Defect-Tolerant Logic Hardening for Crossbar-based Nanosystems [p. 1801]
Ravindran, B.: FBLT: A Real-Time Contention Manager with Improved Schedulability [p. 1325]
Ray, B.N.B.: An Efficient Wirelength Model for Analytical Placement [p. 1711]
Reda, S.: High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization [p. 1271]; Mitigating Dark Silicon Problems Using Superlattice-based Thermoelectric Coolers [p. 1391]
Reddy, L.: Intuitive ECO Synthesis for High Performance Circuits [p. 1002]
Regazzoni, F.: An EDA-Friendly Protection Scheme against Side-Channel Attacks [p. 410]
Rehman, S.: CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]; Leveraging Variable Function Resilience for Selective Software Reliability on Unreliable Hardware [p. 1759]
Reichenbach, F.: Reliability Analysis Reloaded: How Will We Survive? [p. 358]
Reimann, F.: Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults [p. 1621]
Reimer, S.: Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths [p. 448]
Reinig, H.: A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis [p. 1783]
Reinschke, J.: Interactions of Large Scale EV Mobility and Virtual Power Plants [p. 1725]
Reisman, D.: Reverse Engineering Digital Circuits Using Functional Analysis [p. 1277]
Ren, H.: Intuitive ECO Synthesis for High Performance Circuits [p. 1002]
Renaudin, M.: Advances in Asynchronous Logic: From Principles to GALS & NoC, Recent Industry Applications, and Commercial CAD Tools [p. 1715]
Rettberg, A.: Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking [p. 1167]
Rezine, A.: Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory [p. 785]
Rico, A.: Experiences with Mobile Processors for Energy Efficient HPC [p. 464]
Rico, J.: Wireless Sensor Network Simulation for Security and Performance Analysis [p. 432]
Ricossa, S.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]
Riedel, M. D.: Using Cubes of Non-state Variables with Property Directed Reachability [p. 807]
Riener, H.: Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis [p. 939]
Rizk, M.: Statically-scheduled Application-specific Processor Design: A Case-study on MMSE MIMO Equalization [p. 677]
Robert, C.: A Sub-μA Power Management Circuit in 0.18μm CMOS for Energy Harvesters [p. 1197]
Roche, P.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Rodopoulos, D.: Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems [p. 655]
Rodriguez González, S.: Innovative Energy Storage Solutions for Future Electromobility in Smart Cities [p. 1730]
Rodríguez-Rodríguez, R.: Reducing Writes in Phase-Change Memory Environments by Using Efficient Cache Replacement Policies [p. 93]
Rogachev, A.: A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis under Process Variation [p. 1789]
Rosenstiel, W.: Shared Memory Aware MPSoC Software Deployment [p. 1771]
Rotermund, D.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Roux, D.: Time- and Angle-triggered Real-time Kernel [p. 1060]
Roy, K.: Substitute-and-Simplify: A Unified Design Paradigm for Approximate and Quality Configurable Circuits [p. 1367]; DWM-TAPESTRI - An Energy Efficient All-Spin Cache Using Domain Wall Shift Based Writes [p. 1825]
Roy, S.: Proactive Aging Management in Heterogeneous NoCs through a Criticality-driven Routing Approach [p. 1032]
Rubio, A.: Design and Implementation of an Adaptive Proactive Reconfiguration Technique for SRAM Caches [p. 1303]
Ruch, P.: Roadmap towards Ultimately-Efficient Zeta-Scale Datacenters [p. 1339]
Ruggiero, M.: Correlation-Aware Virtual Machine Allocation for Energy-Efficient Datacenters [p. 1345]
Rust, J.: Low Complexity QR-Decomposition Architecture Using the Logarithmic Number System [p. 97]
Rutzig, M.B.: A Transparent and Energy Aware Reconfigurable Multiprocessor Platform for Simultaneous ILP and TLP Exploitation [p. 1559]

Saboori, E.: Hybrid Prototyping of Multicore Embedded Systems [p. 1627]
Sacchetto, D.: Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]
Sadeghi, A.-R.: Memristor PUFs: A New Generation of Memory-based Physically Unclonable Functions [p. 428]
Saeedi, M.: Reversible Logic Synthesis of k-Input, m-Output Lookup Tables [p. 1235]
Sagstetter, F.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]
Sahbi, B.: HW-SW Integration for Energy-Efficient/Variability-Aware Computing [p. 607]
Sahuquillo, J.: Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]
Sampaio, F.: Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding [p. 665]
Sanchez, E.: On-Line Functionally Untestable Fault Identification in Embedded Processor Cores [p. 1462]
Sanchez, P.: Wireless Sensor Network Simulation for Security and Performance Analysis [p. 432]
Sancho, J.: Wireless Sensor Network Simulation for Security and Performance Analysis [p. 432]
Sander, I.: An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems [p. 27]; The RecoBlock SoC Platform: A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks [p. 833]
Sangai, A.: A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis under Process Variation [p. 1789]
Sangiovanni Vincentelli, A.: PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead [p. 171]; Dr. Frankenstein's Dream Made Possible: Implanted Electronic Devices [p. 1531]
Sano, T.: Development of Low Power Many-Core SoC for Multimedia Applications [p. 773]; A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Santen, T.: Model-Based Energy Optimization of Automotive Control Systems [p. 761]
Santini, T.: Exploring Resource Mapping Policies for Dynamic Clustering on NoC-based MPSoCs [p. 681]
Sapatnekar, S.S.: Placement Optimization of Power Supply Pads Based on Locality [p. 1655]; CATALYST: Planning Layer Directives for Effective Design Closure [p. 1873]
Sarangi, S.R.: Space Sensitive Cache Dumping for Post-silicon Validation [p. 497]
Sarrazin, S.: Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection [p. 1077]
Sasaki, S.: A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Sato, H.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Sato, T.: Hot-Swapping Architecture with Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array [p. 535]; A Cost-Effective Selective TMR for Heterogeneous Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis [p. 701]
Sauer, M.: Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths [p. 448]
Sazeides, Y.: Memory Array Protection: Check on Read or Check on Write? [p. 214]
Schellenberg, T.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Schleifer, J.: High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]
Schlichtmann, U.: Fast Cache Simulation for Host-Compiled Simulation of Embedded Software [p. 637]; Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts [p. 1161]; A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot [p. 1331]; A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis [p. 1783]
Schneider, J.: An Extremely Compact JPEG Encoder for Adaptive Embedded Systems [p. 1063]
Schneider, M.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Schneider, R.: Compositional Analysis of Switched Ethernet Topologies [p. 1099]; Multirate Controller Design for Resource- and Schedule-Constrained Automotive ECUs [p. 1123]
Schoeberl, M.: An Area-efficient Network Interface for a TDM-based Network-on-Chip [p. 1044]
Scholl, C.: Lemma Localization: A Practical Method for Downsizing SMT-Interpolants [p. 1405]
Schönwald, T.: Shared Memory Aware MPSoC Software Deployment [p. 1771]
Schubert, T.: Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths [p. 448]
Schulz, M.: Semiconductor Technologies for Smart Mobility Management [p. 1749]
Seidl, M.: Bridging the Gap between Dual Propagation and CNF-based QBF Solving [p. 811]
Seifert, D.: Model-Based Energy Optimization of Automotive Control Systems [p. 761]
Seiter, J.: Determining Relevant Model Elements for the Verification of UML/OCL Specifications [p. 1189]
Seo, S.: Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs [p. 1575]
Sha, E.H.-M.: Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems [p. 599]
Sha, L.: Optimized Scheduling of Multi-IMA Partitions with Exclusive Region for Synchronized Real- Time Multi-Core Systems [p. 970]; Holistic Design Parameter Optimization of Multiple Periodic Resources in Hierarchical Scheduling [p. 1313]
Shafaei, A.: Reversible Logic Synthesis of k-Input, m-Output Lookup Tables [p. 1235]
Shafik, R.A.: A Fast and Efficient DFT for Test and Diagnosis of Power Switches in SoCs [p. 1089]
Shafique, M.: Self-Adaptive Hybrid Dynamic Power Management for Many-Core Systems [p. 51]; An H.264 Quad-FullHD Low-Latency Intra Video Encoder [p. 115]; Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder [p. 125]; Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding [p. 665]; CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]; Leveraging Variable Function Resilience for Selective Software Reliability on Unreliable Hardware [p. 1759]
Shah, H.: Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis [p. 308]
Shan, T.: A 100 GOPS ASP Based Baseband Processor for Wireless Communication [p. 121]
Sharad, M.: DWM-TAPESTRI - An Energy Efficient All-Spin Cache Using Domain Wall Shift Based Writes [p. 1825]
Sharma, N.: A Semi-Canonical Form for Sequential AIGs [p. 797]
Shen, H.: User-Aware Energy Efficient Streaming Strategy for Smartphone Based Video Playback Applications [p. 258]
Sheng, X.: SPaC: A Segment-based Parallel Compression for Backup Acceleration in Nonvolatile Processors [p. 865]
Sherwood, T.: A Practical Testing Framework for Isolating Hardware Timing Channels [p. 1281]
Shi, F.: A Work-Stealing Scheduling Framework Supporting Fault Tolerance [p. 695]
Shi, L.: Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM [p. 1247]
Shih, H.-C.: An Enhanced Double-TSV Scheme for Defect Tolerance in 3D-IC [p. 1486]
Shin, D.: Saliency Aware Display Power Management [p. 1203]; Adaptive Thermal Management for Portable System Batteries by Forced Convection Cooling [p. 1225]
Shirazi, B.: Energy-Efficient Multicore Chip Design through Cross-Layer Approach [p. 725]
Shofner, G.: Fault Analysis and Simulation of Large Scale Industrial Mixed-Signal Circuits [p. 565]
Shreejith, S.: An Approach for Redundancy in FlexRay Networks Using FPGA Partial Reconfiguration [p. 721]
Shriraman, A.: Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory [p. 785]
Shrivastava, A.: Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures [p. 593]
Shulaker, M.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Sigl, G.: Comprehensive Analysis of Software Countermeasures against Fault Attacks [p. 404]
Silvano, C.: A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization [p. 659]; Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]; Thermal-Aware Datapath Merging for Coarse-Grained Reconfigurable Processors [p. 1649]
Sinanoglu, O.: Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits [p. 292]; Is Split Manufacturing Secure? [p. 1259]
Singh, K.: Accurate and Efficient Reliability Estimation Techniques during ADL-Driven Embedded Processor Design [p. 547]
Slomka, F.: Event Density Analysis for Event Triggered Control Systems [p. 1111]; Sufficient Real-Time Analysis for an Engine Control Unit with Constant Angular Velocities [p. 1335]
Smith, S.: PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future? [p. 1526]
Smola, M.: Comprehensive Analysis of Software Countermeasures against Fault Attacks [p. 404]
Soeken, M.: Determining Relevant Model Elements for the Verification of UML/OCL Specifications [p. 1189]; Towards a Generic Verification Methodology for System Models [p. 1193]
Sonza Reorda, M.: Reliability Analysis Reloaded: How Will We Survive? [p. 358]; On-Line Functionally Untestable Fault Identification in Embedded Processor Cores [p. 1462]
Soudris, D.: Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems [p. 655]
Sparsø, Jens: An Area-efficient Network Interface for a TDM-based Network-on-Chip [p. 1044]
Stamoulis, G.: Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]; A Parallel Fast Transform-Based Preconditioning Approach for Electrical-Thermal Co- Simulation of Power Delivery Networks [p. 1689]
Stanisic, L.: Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]
Steinhorst, S.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]; Priority Assignment for Event-triggered Systems Using Mathematical Programming [p. 982]
Stergiou, S.: Optimizing BDDs for Time-Series Dataset Manipulation [p. 1018]
Sterpone, L.: On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems [p. 717]
Stevens, K.S.: Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT [p. 242]
Stojanovic, V.: Breaking the Energy Barrier in Fault-Tolerant Caches for Multicore Systems [p. 731]
Stroobandt, D.: An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits [p. 821]
Struzyna, M.: Sub-Quadratic Objectives in Quadratic Placement [p. 1867]
Stumpf, F.: Comprehensive Analysis of Software Countermeasures against Fault Attacks [p. 404]
Su, H.: An Elastic Mixed-Criticality Task Model and Its Scheduling Algorithm [p. 147]
Su, Y.: Defect-Tolerant Logic Hardening for Crossbar-based Nanosystems [p. 1801]
Subramanian, S.: SMART: A Single-Cycle Reconfigurable NoC for SoC Applications [p. 338]
Subramanyan, P.: Reverse Engineering Digital Circuits Using Functional Analysis [p. 1277]
Suresh, C.K.H.: Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits [p. 292]
Susnea, A.: Reverse Engineering Digital Circuits Using Functional Analysis [p. 1277]
Swarup, S.: A Power-Driven Thermal Sensor Placement Algorithm for Dynamic Thermal Management [p. 1215]
Sze, C.: CATALYST: Planning Layer Directives for Effective Design Closure [p. 1873]

Tagliavini, G.: Enabling Fine-Grained OpenMP Tasking on Tightly-Coupled Shared Memory Clusters [p. 1504]
Tahoori, M.: Instruction-Set Extension under Process Variation and Aging Effects [p. 182]; MTTF-Balanced Pipeline Design [p. 270]; Incorporating the Impacts of Workload-Dependent Runtime Variations into Timing Analysis [p. 1022]
Takeda, A.: A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Talpin, J.-P.: Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]
Tan, S.X.-D.: A Power-Driven Thermal Sensor Placement Algorithm for Dynamic Thermal Management [p. 1215]
Tanabe, J.: Development of Low Power Many-Core SoC for Multimedia Applications [p. 773]; A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Tang, L.-F.: On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]
Taouil, M.: Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? [p. 1251]
Taskin, B.: Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction [p. 1229]
Tasselli, G.: A Sub-μA Power Management Circuit in 0.18μm CMOS for Energy Harvesters [p. 1197]
Teich, J.: Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-Core Systems [p. 1498]; Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults [p. 1621]
Teng, Y.: Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction [p. 1229]
Tenhunen, H.: CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems [p. 1048]
Termier, A.: Data Mining MPSoC Simulation Traces to Identify Concurrent Memory Access Patterns [p. 755]
Tessier, R.: Run-time Probabilistic Detection of Miscalibrated Thermal Sensors in Many-core Systems [p. 1395]; FPGA Latency Optimization Using System-level Transformations and DFG Restructuring [p. 1553]
Thabet, F.: An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the STHORM Many-Core Architecture [p. 531]
Thatcher, A.R.: Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT [p. 242]
Theißing, N.: Comprehensive Analysis of Software Countermeasures against Fault Attacks [p. 404]
Thery, T.: Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]
Thiele, L.: A Satisfiability Approach to Speed Assignment for Distributed Real-Time Systems [p. 749]
Thomas, O.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Thomas, P.-X.: Configurability in IP Subsystems: Baseband Examples [p. 163]
Thonnart, Y.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Tiefenauer, R.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Tilli, A.: SCC Thermal Model Identification via Advanced Bias-Compensated Least-Squares [p. 230]
Tirado, F.: Reducing Writes in Phase-Change Memory Environments by Using Efficient Cache Replacement Policies [p. 93]
Tiwari, P.: Automated Determination of Top Level Control Signals [p. 509]
Todorov, V.: A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis [p. 1783]
Todri, A.: Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]
Tokuyoshi, T.: A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Tolstosheeva, E.: Development of a Fully Implantable Recording System for ECoG Signals [p. 893]
Torruella, P.: A Multi-Level Monte Carlo FPGA Accelerator for Option Pricing in the Heston Model [p. 248]
Trucco, G.: Minimization of P-Circuits Using Boolean Relations [p. 996]
Tsay, R.-S.: A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations [p. 643]
Tseng, W.-C.: Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems [p. 599]
Tsiskaridze, N.: Reverse Engineering Digital Circuits Using Functional Analysis [p. 1277]
Tsompanopoulou, P.: A Parallel Fast Transform-Based Preconditioning Approach for Electrical-Thermal Co- Simulation of Power Delivery Networks [p. 1689]
Tsui, C.-Y.: SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model [p. 354]
Tsutsui, H.: Hot-Swapping Architecture with Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array [p. 535]; A Cost-Effective Selective TMR for Heterogeneous Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis [p. 701]
Tu, W.-P.: Co-Synthesis of Data Paths and Clock Control Paths for Minimum-Period Clock Gating [p. 1831]
Turakhia, Y.: Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors [p. 39]
Tuyls, P.: Anti-Counterfeiting with Hardware Intrinsic Security [p. 1137]
Tzou, N.L.: Periodic Jitter and Bounded Uncorrelated Jitter Decomposition Using Incoherent Undersampling [p. 1667]

ul Hassan, N.: Wireless Interconnect for Board and Chip Level [p. 958]
Unsal, O.: FaulTM: Error Detection and Recovery Using Hardware Transactional Memory [p. 220]
Unutulmaz, A.: Area Optimization on Fixed Analog Floorplans Using Convex Area Functions [p. 1843]
Usman, M.: An H.264 Quad-FullHD Low-Latency Intra Video Encoder [p. 115]; Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder [p. 125]
Usui, H.: Development of Low Power Many-Core SoC for Multimedia Applications [p. 773]; A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]

Vahabi, N.: Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]
Vaidyanathan, K.: Leakage and Temperature Aware Server Control for Improving Energy Efficiency in Data Centers [p. 266]
Valentian, A.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Valero, A.: Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]
Valero, M.: Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes [p. 917]
van den Braak, G.-J.: Future of GPGPU Micro-Architectural Parameters [p. 392]
Van Den Keybus, J.: Automotive Ethernet: In-vehicle Networking and Smart Mobility [p. 1735]
van der Leest, V.: Anti-Counterfeiting with Hardware Intrinsic Security [p. 1137]
van der Wolf, P.: Modular SoC Integration with Subsystems: The Audio Subsystem Case [p. 157]
Van Hoof, C.: Addressing the Healthcare Cost Dilemma by Managing Health instead of Managing Illness - An Opportunity for Wearable Wireless Sensors [p. 1537]
Van Kleef, J.: Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]
Van Rethy, J.: A Low-Power and Low-Voltage BBPLL-Based Sensor Interface in 130nm CMOS for Wireless Sensor Networks [p. 1431]
Vasudevan, S.: Runtime Verification of Nonlinear Analog Circuits Using Incremental Time-Augmented RRT Algorithm [p. 21]; Reachability Analysis of Nonlinear Analog Circuits through Iterative Reachable Set Reduction [p. 1436]
Veeravalli, B.: Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems [p. 689]; Communication and Migration Energy Aware Design Space Exploration for Multicore Systems with Intermittent Faults [p. 1631]
Velickovic, N.: An EDA-Friendly Protection Scheme against Side-Channel Attacks [p. 410]
Vendraminetto, D.: Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]; Optimization Techniques for Craig Interpolant Compaction in Unbounded Model Checking [p. 1417]
Venkataramani, S.: Substitute-and-Simplify: A Unified Design Paradigm for Approximate and Quality Configurable Circuits [p. 1367]
Venkatesan, R.: DWM-TAPESTRI - An Energy Efficient All-Spin Cache Using Domain Wall Shift Based Writes [p. 1825]
Vera, X.: Capturing Vulnerability Variations for Register Files [p. 1468]
Vermesan, O.: Automotive Ethernet: In-vehicle Networking and Smart Mobility [p. 1735]; Smart, Connected and Mobile: Architecting Future Electric Mobility Ecosystems [p. 1740]; e-Mobility - The Next Frontier for Automotive Industry [p. 1745]; Semiconductor Technologies for Smart Mobility Management [p. 1749]
Videau, B.: Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]
Viehl, A.: Shared Memory Aware MPSoC Software Deployment [p. 1771]
Vigna, B.: Smart Systems for Internet of Things [p. 1]
Vigouroux, X.: What Designs for Coming Supercomputers? [p. 469]
Vij, V.S.: Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT [p. 242]
Villa, T.: Minimization of P-Circuits Using Boolean Relations [p. 996]
Vinco, S.: On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]
Vipin, K.: An Approach for Redundancy in FlexRay Networks Using FPGA Partial Reconfiguration [p. 721]
Vipond, J.: Experiences with Mobile Processors for Energy Efficient HPC [p. 464]
Virazel, A.: Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]
Vivet, P.: Fast and Accurate TLM Simulations Using Temporal Decoupling for FIFO-based Communications [p. 1185]; Advances in Asynchronous Logic: From Principles to GALS & NoC, Recent Industry Applications, and Commercial CAD Tools [p. 1715]
Vogel, B.: Self-Adaptive Hybrid Dynamic Power Management for Many-Core Systems [p. 51]
Voicu, G.R.: Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? [p. 1251]
von Hanxleden, R.: Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]

Wachter, E.: Topology-Agnostic Fault-Tolerant NoC Routing Method [p. 1595]
Wagner, F.R.: Exploring Resource Mapping Policies for Dynamic Clustering on NoC-based MPSoCs [p. 681]
Wagner, M.: Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications [p. 276]
Wallander, E.: A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot [p. 1331]
Wang, B.: 3D Reconfgurable Power Switch Network for Demand-supply Matching between Multi-output Power Converters and Many-core Microprocessors [p. 1643]
Wang, C.: TreeFTL: Efficient RAM Management for High Performance of NAND Flash-based Storage Systems [p. 374]
Wang, C.-Y.: On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]
Wang, H.: A Power-Driven Thermal Sensor Placement Algorithm for Dynamic Thermal Management [p. 1215]
Wang, J.: OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches [p. 847]
Wang, K.: 3D Reconfgurable Power Switch Network for Demand-supply Matching between Multi-output Power Converters and Many-core Microprocessors [p. 1643]
Wang, L.: DoE-based Performance Optimization of Energy Management in Sensor Nodes Powered by Tunable Energy-Harvesters [p. 484]
Wang, X.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Wang, Y.: Efficient Importance Sampling for High-sigma Yield Analysis with Adaptive Online Surrogate Modeling [p. 1291]
Wang, Y.: Optimal Control of a Grid-Connected Hybrid Electrical Energy Storage System for Homes [p. 881]; Capital Cost-Aware Design and Partial Shading-Aware Architecture Optimization of a Reconfigurable Photovoltaic System [p. 909]; A New Paradigm for Trading Off Yield, Area and Performance to Enhance Performance per Wafer [p. 1753]
Wang, Y.: SPaC: A Segment-based Parallel Compression for Backup Acceleration in Nonvolatile Processors [p. 865]
Wang, Y.: A Work-Stealing Scheduling Framework Supporting Fault Tolerance [p. 695]
Wang, Z.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Wang, Z.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Wang, Z.: Accurate and Efficient Reliability Estimation Techniques during ADL-Driven Embedded Processor Design [p. 547]
Wang, Z.: Fast and Accurate Cache Modeling in Source-Level Simulation of Embedded Software [p. 587]; DANCE: Distributed Application-aware Node Configuration Engine in Shared Reconfigurable Sensor Networks [p. 839]
Wartell, M.: Mempack: An Order of Magnitude Reduction in the Cost, Risk, and Time for Memory Compiler Certification [p. 1490]
Washburn, C.: Intuitive ECO Synthesis for High Performance Circuits [p. 1002]
Watanabe, Y.: Share with Care: A Quantitative Evaluation of Sharing Approaches in High-level Synthesis [p. 1547]
Weddell, A.S.: A Survy of Multi-Source Energy Harvesting Systems [p. 905]
Wehn, N.: System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs [p. 236]; A Multi-Level Monte Carlo FPGA Accelerator for Option Pricing in the Heston Model [p. 248]
Wei, H.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Wei, L.: Statistical Modeling with the Virtual Source MOSFET Model [p. 1454]
Wei, Y.: CATALYST: Planning Layer Directives for Effective Design Closure [p. 1873]
Weis, C.: System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs [p. 236]
Weldon, M.A.: STT-RAM Designs Supporting Dual-Port Accesses [p. 853]
Welp, T.: QF_BV Model Checking with Property Directed Reachability [p. 791]
Wen, C.H.-P.: Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step [p. 454]
Wen, S.-J.: Error Detection in Ternary CAMs Using Bloom Filters [p. 1474]
Wen, W.: DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems [p. 380]
Werner, S.: Hybrid Interconnect Design for Heterogeneous Hardware Accelerators [p. 843]
Wettin, P.: Energy-Efficient Multicore Chip Design through Cross-Layer Approach [p. 725]
Wijtvliet, R.: Innovative Energy Storage Solutions for Future Electromobility in Smart Cities [p. 1730]
Wildermann, S.: Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-Core Systems [p. 1498]
Wille, R.: Determining Relevant Model Elements for the Verification of UML/OCL Specifications [p. 1189]; Towards a Generic Verification Methodology for System Models [p. 1193]
Wilson, R.: Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]
Winemberg, L.: Fault Analysis and Simulation of Large Scale Industrial Mixed-Signal Circuits [p. 565]
Wirrer, G.: Sufficient Real-Time Analysis for an Engine Control Unit with Constant Angular Velocities [p. 1335]
Wolf, M.: Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]
Wong, S.: Support for Dynamic Issue Width in VLIW Processors Using Generic Binaries [p. 827]
Wong, W.-F.: TreeFTL: Efficient RAM Management for High Performance of NAND Flash-based Storage Systems [p. 374]
Wong, H.-S.P.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Wu, C.-W.: An Enhanced Double-TSV Scheme for Defect Tolerance in 3D-IC [p. 1486]
Wu, H.: Model-Based Energy Optimization of Automotive Control Systems [p. 761]
Wu, H.-I.: A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations [p. 643]
Wu, T.-H.: NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs [p. 1379]
Wu, W.-R.: Automatic Circuit Sizing Technique for the Analog Circuits with Flexible TFTs Considering Process Variation and Bending Effects [p. 1458]
Wu, X.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Wunderlich, H.-J.: Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications [p. 276]; Accurate QBF-based Test Pattern Generation in Presence of Unknown Values [p. 436]

Xiang, Y.: Enhancing Multicore Reliability through Wear Compensation in Online Assignment and Scheduling [p. 1373]
Xiao, Yang: Saliency Aware Display Power Management [p. 1203]
Xie, Q.: Adaptive Thermal Management for Portable System Batteries by Forced Convection Cooling [p. 1225]
Xie, Y.: OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches [p. 847]; Future Memory and Interconnect Technologies [p. 964]; Thermomechanical Stress-Aware Management for 3D IC Designs [p. 1255]
Xu, H.: Development of Low Power Many-Core SoC for Multimedia Applications [p. 773]; A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Xu, J.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Xu, Y.: Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM [p. 1247]
Xue, C.J.: Profit Maximization through Process Variation Aware High Level Synthesis with Speed Binning [p. 176]; Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems [p. 599]; Multirate Controller Design for Resource- and Schedule-Constrained Automotive ECUs [p. 1123]; Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM [p. 1247]
Xydis, S.: A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization [p. 659]; Thermal-Aware Datapath Merging for Coarse-Grained Reconfigurable Processors [p. 1649]

Yakovlev, A.: Advances in Asynchronous Logic: From Principles to GALS & NoC, Recent Industry Applications, and Commercial CAD Tools [p. 1715]
Yalcin, G.: FaulTM: Error Detection and Recovery Using Hardware Transactional Memory [p. 220]
Yan, G.: SmartCap: User Experience-Oriented Power Adaptation for Smartphone's Application Processor [p. 57]; Orchestrator: A Low-cost Solution to Reduce Voltage Emergencies for Multi-threaded Applications [p. 208]
Yan, L.: A Dynamic Self-Adaptive Correction Method for Error Resilient Application [p. 943]
Yang, C.-P.: NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs [p. 1379]
Yang, H.: SPaC: A Segment-based Parallel Compression for Backup Acceleration in Nonvolatile Processors [p. 865]; Utilizing Voltage-Frequency Islands in C-to-RTL Synthesis for Streaming Applications [p. 992]
Yang, J.: Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer [p. 859]; The Design of Sustainable Wireless Sensor Network Node Using Solar Energy and Phase Change Memory [p. 869]
Yang, X.: FIFO Cache Analysis for WCET Estimation: A Quantitative Approach [p. 296]
Yao, J.: Efficient Importance Sampling for High-sigma Yield Analysis with Adaptive Online Surrogate Modeling [p. 1291]
Yao, Y.: ClockPUF: Physical Unclonable Functions Based on Clock Networks [p. 422]
Yasir Dogan, A.: Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms [p. 396]
Ye, J.: Capturing Post-Silicon Variation by Layout-aware Path-delay Testing [p. 288]
Ye, Y.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Ye, Z.: Efficient Importance Sampling for High-sigma Yield Analysis with Adaptive Online Surrogate Modeling [p. 1291]
Yetim, Y.: Extracting Useful Computation from Error-Prone Processors for Streaming Applications [p. 202]
Yi, W.: FIFO Cache Analysis for WCET Estimation: A Quantitative Approach [p. 296]
Yilmaz, E.: Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits [p. 292]; Fault Analysis and Simulation of Large Scale Industrial Mixed-Signal Circuits [p. 565]; Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]
Yin, C.-E.: Design and Implementation of a Group-based RO PUF [p. 416]
Ying, H.: Fast and Optimized Task Allocation Method for Low Vertical Link Density 3-Dimensional Networks-on-Chip Based Many Core Systems [p. 1777]
Yokosawa, A.: A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]
Yongtao, S.: A 100 GOPS ASP Based Baseband Processor for Wireless Communication [p. 121]
Yoon, M.-K.: Optimized Scheduling of Multi-IMA Partitions with Exclusive Region for Synchronized Real- Time Multi-Core Systems [p. 970]; Holistic Design Parameter Optimization of Multiple Periodic Resources in Hierarchical Scheduling [p. 1313]
Yu, F.-W.: A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations [p. 643]
Yu, H.: 3D Reconfgurable Power Switch Network for Demand-supply Matching between Multi-output Power Converters and Many-core Microprocessors [p. 1643]
Yu, H.: Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]
Yu, L.: Statistical Modeling with the Virtual Source MOSFET Model [p. 1454]
Yu, W.: GPU-Friendly Floating Random Walk Algorithm for Capacitance Extraction of VLSI Interconnects [p. 1661]
Yue, J.: Exploiting Subarrays inside a Bank to Improve Phase Change Memory Performance [p. 386]
Yue, S.: Adaptive Thermal Management for Portable System Batteries by Forced Convection Cooling [p. 1225]
Yueh, W.: Perceptual Quality Preserving SRAM Architecture for Color Motion Pictures [p. 103]

Zaccaria, V.: A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization [p. 659]; Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]
Zafalon, R.: e-Mobility - The Next Frontier for Automotive Industry [p. 1745]
Zakharenko, V.: Characterizing the Performance Benefits of Fused CPU/GPU Systems Using FusionSim [p. 685]
Zang, B.: Multi-level Phase Analysis for Sampling Simulation [p. 649]
Zapater, M.: Leakage and Temperature Aware Server Control for Improving Energy Efficiency in Data Centers [p. 266]
Zar, D.M.: Metastability Challenges for 65nm and Beyond; Simulation and Measurements [p. 1297]
Zatt, B.: Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding [p. 665]
Zebchuk, J.: A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches [p. 89]
Zeng, B.-H.: A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations [p. 643]
Zeng, H.: PT-AMC: Integrating Preemption Thresholds into Mixed-Criticality Scheduling [p. 141]; Robust and Extensible Task Implementations of Synchronous Finite State Machines [p. 1319]
Zeppa, G.: Time- and Angle-triggered Real-time Kernel [p. 1060]
Zhai, K.: GPU-Friendly Floating Random Walk Algorithm for Capacitance Extraction of VLSI Interconnects [p. 1661]
Zhang, C.: 3D Reconfgurable Power Switch Network for Demand-supply Matching between Multi-output Power Converters and Many-core Microprocessors [p. 1643]
Zhang, J.: Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]
Zhang, L.: Compositional Analysis of Switched Ethernet Topologies [p. 1099]
Zhang, M.: Breaking the Energy Barrier in Fault-Tolerant Caches for Multicore Systems [p. 731]
Zhang, T.: Thermomechanical Stress-Aware Management for 3D IC Designs [p. 1255]
Zhang, T.: 3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling [p. 1241]
Zhang, W.: Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]
Zhang, W.: Multi-level Phase Analysis for Sampling Simulation [p. 649]
Zhang, X.: Capturing Post-Silicon Variation by Layout-aware Path-delay Testing [p. 288]
Zhang, Y.: Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer [p. 859]; The Design of Sustainable Wireless Sensor Network Node Using Solar Energy and Phase Change Memory [p. 869]
Zhao, J.: Run-time Probabilistic Detection of Miscalibrated Thermal Sensors in Many-core Systems [p. 1395]
Zhao, M.: Profit Maximization through Process Variation Aware High Level Synthesis with Speed Binning [p. 176]
Zhao, Q.: PT-AMC: Integrating Preemption Thresholds into Mixed-Criticality Scheduling [p. 141]
Zhou, H.: Resource-Constrained High-Level Datapath Optimization in ASIP Design [p. 198]; Retiming for Soft Error Minimization under Error-Latching Window Constraints [p. 1008]
Zhou, P.: The Design of Sustainable Wireless Sensor Network Node Using Solar Energy and Phase Change Memory [p. 869]
Zhou, P.: Placement Optimization of Power Supply Pads Based on Locality [p. 1655]
Zhou, Q.: Design and Implementation of a Group-based RO PUF [p. 416]
Zhu, D.: An Elastic Mixed-Criticality Task Model and Its Scheduling Algorithm [p. 147]
Zhu, Q.: Robust and Extensible Task Implementations of Synchronous Finite State Machines [p. 1319]
Zhu, Y.: Exploiting Subarrays inside a Bank to Improve Phase Change Memory Performance [p. 386]
Zhu, Y.: Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory [p. 785]
Zhuang, H.: GPU-Friendly Floating Random Walk Algorithm for Capacitance Extraction of VLSI Interconnects [p. 1661]
Zhuge, Q.: Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems [p. 599]
Ziermann, T.: Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-Core Systems [p. 1498]
Zimmermann, R.: Quality-Aware Media Scheduling on MPSoC Platforms [p. 976]
Ziyuan, Z.: A 100 GOPS ASP Based Baseband Processor for Wireless Communication [p. 121]
Zoni, D.: Sensor-wise Methodology to Face NBTI Stress of NoC Buffers [p. 1038]
Zordan, L.B.: Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]
Zou, Q.: Thermomechanical Stress-Aware Management for 3D IC Designs [p. 1255]
Zuo, Q.: A Work-Stealing Scheduling Framework Supporting Fault Tolerance [p. 695]

DATE 2013 TABLE OF CONTENTS