[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]
A
- Abelein, Ulrich
- [1] [2] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1
- Abella, Jaume
- [3] [4] Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2
- Abellán, José L.
- [5] [6] Thermal Management of Manycore Systems with Silicon-Photonic Networks 11.2_2
- Abraham, Jacob A.
- [7] [8] A Novel Low Power 11-bit Hybrid ADC Using Flash and Delay Line Architectures - 02.4_6
- Abraham, Jacob A.
- [9] [10] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5
- Acquaviva, Jean-Thomas
- [11] [12] A Unified Methodology for a Fast Benchmarking of Parallel Architecture - 07.6_7
- Adam, Daniel
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Adler, Oshri
- [15] [16] Facilitating Timing Debug by Logic Path Correspondence - 09.7_1
- Adyanthaya, S.
- [17] [18] Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2
- Afacan, Engin
- [19] [20] Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5
- Afzali Kusha, Ali
- [21] [22] Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits - 05.4_5
- Afzali-Kusha, Ali
- [23] [24] Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions - 08.6_7
- Agbo, Innocent
- [25] [26] Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2
- Aghaee, Nima
- [27] [28] An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs - 05.7_5
- Agrawal, Prashant
- [29] [30] Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5
- Agrawal, Supriya
- [31] [32] EDT: A Specification Notation for Reactive Systems - 08.5_3
- Aguilera, Paula
- [33] [34] Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4
- Ahari, Ali
- [35] [36] A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology - 11.7_2
- Ahmad, Tariq B.
- [37] [38] Fast STA Prediction-based Gate-level Timing Simulation - 09.4_1
- Ahmad, Ubaid
- [39] [40] Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1
- Ahrendts, Leonie
- [41] [42] Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5
- Aitken, Rob
- [43] [44] Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2
- Akesson, Benny
- [45] [46] Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems - 03.5_1
- Akesson, Benny
- [47] [48] Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1
- Aksanli, Baris
- [49] [50] Providing Regulation Services and Managing Data Center Peak Power Budgets - 06.3_6
- Aksoy, Levent
- [51] [52] Optimization of Design Complexity in Time-Multiplexed Constant Multiplications - 10.7_7
- Al Faruque, Mohammad Abdullah
- [53] [54] GPU-EvR: Run-time Event Based Real-time Scheduling Framework on GPGPU Platform - 08.6_2
- Al Faruque, Mohammad Abdullah
- [55] [56] Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems - 11.3_5
- Alaghi, Armin
- [57] [58] Fast and Accurate Computation Using Stochastic Circuits - 04.4_4
- Alam, Faisal
- [59] [60] Energy Optimization in Android Applications through Wakelock Placement - 04.6_5
- Al-Dujaily, Ra'ed
- [61] [62] Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4
- Alekseyev, Arseniy
- [63] [64] Design of Safety Critical Systems by Refinement - 04.6_4
- Alexandrescu, Dan
- [65] [66] Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1
- Alexandrescu, Dan
- [67] [68] INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4
- Alhammad, Ahmed
- [69] [70] Time-predictable Execution of Multithreaded Applications on Multicore Systems - 02.6_4
- Al-Hashimi, Bashir M.
- [71] [72] Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6
- Al-Hashimi, Bashir M.
- [73] [74] Clock-Modulation Based Watermark for Protection of Embedded Processors - 03.3_3
- Alì, Giuseppe
- [75] [76] Implicit Index-aware Model Order Reduction for RLC/RC Networks 03.4_3
- Alizadeh, Bijan
- [21] [22] Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits - 05.4_5
- Alorda, B.
- [77] [78] Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications - 06.7_2
- Althaus, Ernst
- [79] [80] Simple Interpolants for Linear Arithmetic - 05.5_3
- Altmeyer, Sebastian
- [81] [82] On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis - 02.6_1
- Amano, Hideharu
- [83] [84] Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1
- Amano, Hideharu
- [85] [86] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3
- Amaru, Luca
- [87] [88] Advanced System on a Chip Design Based on Controllable-Polarity FETs - 09.1_2
- Amarú, Luca
- [89] [90] An Efficient Manipulation Package for Biconditional Binary Decision Diagrams - 10.7_3
- Aminifar, Amir
- [91] [92] Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees - 03.6_2
- Aminot, Alexandre
- [93] [94] Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4
- Amir, Mohammad Faisal
- [95] [96] Ultra-low Power Electronics with Si/Ge Tunnel FET - 08.8_1
- Amrouch, Hussam
- [97] [98] hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6
- Amrouch, Hussam
- [99] [100] mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2
- Andrades, Cristian
- [101] [102] Signature Indexing of Design Layouts for Hotspot Detection - 12.4_2
- Annaswamy, Anuradha M.
- [103] [104] Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3
- Annavaram, Murali
- [105] [106] Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W - 05.3_2
- Ansaloni, Giovanni
- [107] [108] Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1
- Anton, Mario
- [109] [110] Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2
- Antoniadis, Dimitri
- [111] [112] Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1
- Araújo, Guido
- [113] [114] Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5
- Arbel, Eli
- [15] [16] Facilitating Timing Debug by Logic Path Correspondence - 09.7_1
- Arora, Divya
- [115] [116] Formal Verification of Taint-propagation Security Properties in a Commercial SoC Design - 11.3_3
- Asadi, Hossein
- [35] [36] A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology - 11.7_2
- Ashammagari, Adarsh Reddy
- [117] [118] Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design - 11.7_1
- Ascheid, Gerd
- [119] [120] Time-Decoupled Parallel SystemC Simulation - 07.6_6
- Ascheid, Gerd
- [121] [122] Automatic Detection of Concurrency Bugs through Event Ordering Constraints - 10.4_1
- Ascheid, Gerd
- [123] [124] Optimized Buffer Allocation in Multicore Platforms - 11.5_2
- Ascheid, Gerd
- [125] [126] A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2
- Ascia, Giuseppe
- [127] [128] An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs - 10.2_1
- Atienza, David
- [129] [130] Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2
- Atienza, David
- [107] [108] Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1
- Atienza, David
- [131] [132] A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4
- Atienza, David
- [133] [134] Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3
- Atienza, David
- [135] [136] Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1
- Averbouch, Ilia
- [15] [16] Facilitating Timing Debug by Logic Path Correspondence - 09.7_1
- Ay, Simge
- [19] [20] Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5
- Ayari, H.
- [137] [138] New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7
- Aysu, Aydin
- [139] [140] Analyzing and Eliminating the Causes of Fault Sensitivity Analysis - 08.3_2
- Azais, F.
- [137] [138] New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7
- Azevedo, Rodolfo
- [113] [114] Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5
- Azim, Akramul
- [141] [142] Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications - 10.6_3
B
- Bacivarov, Iuliana
- [143] [144] COOLIP: Simple yet Effective Job Allocation for Distributed Thermally-Throttled Processors - 10.3_5
- Bacivarov, Iuliana
- [145] [146] Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5
- Baghdadi, Amer
- [147] [148] Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL - 08.4_2
- Bahar, R. Iris
- [149] [150] ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits - 12.5_2
- Bähr, Steffen
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Bahrebar, Poona
- [151] [152] Improving Hamiltonian-based Routing Methods for On-chip Networks: A Turn Model Approach - 09.2_5
- Bai, Yu
- [153] [154] Isochronous Networks by Construction - 06.6_2
- Balachandran, Shankar
- [155] [156] Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control - 04.5_3
- Balck, Kenneth
- [157] [158] Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP - 07.6_5
- Bamakhrama, Mohamed A.
- [159] [160] System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach - 12.5_4
- Bampi, Sergio
- [161] [162] dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2
- Banagaaya, Nicodemus
- [75] [76] Implicit Index-aware Model Order Reduction for RLC/RC Networks 03.4_3
- Bandinu, M.
- [163] [164] Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications - 03.4_1
- Banerjee, Kajori
- [165] [166] Acceptance and Random Generation of Event Sequences under Real Time Calculus Constraints - 09.6_2
- Bao, Jiming
- [167] [168] Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3
- Bapp, Falco
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Bardizbanyan, Alen
- [169] [170] Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD3) - 04.5_6
- Barke, E.
- [171] [172] Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4
- Bartolini, Andrea
- [173] [174] A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5
- Bartolini, Andrea
- [175] [176] Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2
- Bartolini, Andrea
- [177] [178] Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2
- Bartolini, Andrea
- [179] [180] Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4
- Bartolini, Sandro
- [181] [182] Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3
- Baskaya, Faik
- [19] [20] Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5
- Basten, Twan
- [183] [184] Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming - 11.5_3
- Batude, Perrine
- [185] [186] 3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4
- Bautista Gomez, L.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
- Bazargan, Kia
- [189] [190] IIR Filters Using Stochastic Arithmetic - 04.4_1
- Becker, Andrew
- [191] [192] SKETCHILOG: Sketching Combinational Circuits - 06.5_5
- Becker, Bernd
- [193] [194] Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1
- Becker, Bernd
- [195] [196] An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3
- Becker, Bernd
- [197] [198] Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1
- Becker, Jürgen
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Beer, Ilan
- [15] [16] Facilitating Timing Debug by Logic Path Correspondence - 09.7_1
- Beerel, Peter
- [199] [200] Stochastic Analysis of Bubble Razor - 05.4_3
- Beltrame, Giovanni
- [201] [202] Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias - 04.4_2
- Beneventi, Francesco
- [179] [180] Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4
- Benini, Luca
- [203] [204] A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7
- Benini, Luca
- [205] [206] A Multi Banked - Multi Ported - non Blocking Shared L2 Cache for MPSoC Platforms 04.5_4
- Benini, Luca
- [207] [208] Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs - 05.3_1
- Benini, Luca
- [173] [174] A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5
- Benini, Luca
- [209] [210] Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3
- Benini, Luca
- [175] [176] Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2
- Benini, Luca
- [211] [212] Context Aware Power Management for Motion-sensing Body Area Network Nodes - 07.3_3
- Benini, Luca
- [177] [178] Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2
- Benini, Luca
- [213] [214] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh - 10.3_6
- Benini, Luca
- [179] [180] Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4
- Beretta, Ivan
- [107] [108] Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1
- Bergmann, Neil W.
- [215] [216] A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures 10.5_3
- Bernard, Florent
- [217] [218] On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models - 03.3_2
- Bernard, S.
- [137] [138] New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7
- Bernardi, Paolo
- [195] [196] An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3
- Beroulle, Vincent
- [219] [220] A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4
- Bertacco, Valeria
- [221] [222] Brisk and Limited-Impact NoC Routing Reconfiguration - 11.2_1
- Bertacco, Valeria
- [223] [224] ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1
- Bertozzi, Davide
- [225] [226] SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3
- Bertozzi, Davide
- [181] [182] Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3
- Beyranvand Nejad, Ashkan
- [227] [228] CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4
- Bhargava, Mudit
- [229] [230] An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS - 04.3_2
- Bhunia, Swarup
- [231] [232] Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3
- Bhunia, Swarup
- [233] [234] Energy-Efficient Hardware Acceleration through Computing in the Memory - 09.8_3
- Biewer, Alexander
- [235] [236] A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving - 08.5_5
- Bin Nasir, Saad
- [237] [238] Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3
- Bini, Enrico
- [91] [92] Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees - 03.6_2
- Bini, Enrico
- [239] [240] Rate-Adaptive Tasks: Model, Analysis, and Design Issues - 09.6_1
- Bishnoi, Rajendra
- [241] [242] Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM - 07.5_1
- Bocquet, Marc
- [243] [244] Resistive Memories: Which Applications? - 10.1_4
- Boettcher, Matthias
- [71] [72] Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6
- Bogdan, Paul
- [85] [86] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3
- Boit, Christian
- [245] [246] Physical Vulnerabilities of Physically Unclonable Functions - 12.2_5
- Bolchini, C.
- [247] [248] Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs - 03.7_2
- Bolle, Michael
- [249] [250] The Connected Car and Its Implication to the Automotive Chip Roadmap - 07.0
- Bombieri, N.
- [251] [252] A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2
- Boning, Duane
- [111] [112] Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1
- Borg, B.M.
- [253] [254] III-V Semiconductor Nanowires for Future Devices - 09.1_1
- Bortolotti, Daniele
- [175] [176] Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2
- Bota, S.
- [77] [78] Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications - 06.7_2
- Bouganis, Christos
- [255] [256] Image Progressive Acquisition for Hardware Systems - 12.3_3
- Bournoutian, Garo
- [257] [258] On-Device Objective-C Application Optimization Framework for High-Performance Mobile Processors - 04.6_2
- Boussetta, Hela
- [93] [94] Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4
- Braojos, Rubén
- [107] [108] Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1
- Bringmann, Oliver
- [259] [260] Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3
- Brück, Rainer
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Brunelli, Davide
- [263] [264] Real-time Optimization of the Battery Banks Lifetime in Hybrid Residential Electrical Systems - 06.3_2
- Burg, Andreas
- [131] [132] A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4
- Burger, Andreas
- [259] [260] Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3
- Burger, Doug
- [265] [266] EVX: Vector Execution on Low Power EDGE Cores - 02.5_4
- Burghartz, Joachim N.
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Burgio, Paolo
- [203] [204] A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7
- Burgio, Paolo
- [209] [210] Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3
- Burleson, Wayne
- [269] [270] Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks - 12.2_1
- Burleson, Wayne
- [271] [272] Hybrid Side-Channel / Machine-Learning Attacks on PUFs: A New Threat? - 12.2_4
- Burlyaev, Dmitry
- [273] [274] Verification-guided Voter Minimization in Triple-Modular Redundant Circuits - 04.7_2
- Büter, Wolfgang
- [275] [276] DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs. - 11.2_4
- Butschke, Jörg
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Buttazzo, Giorgio C.
- [239] [240] Rate-Adaptive Tasks: Model, Analysis, and Design Issues - 09.6_1
- Buttle, Darren
- [239] [240] Rate-Adaptive Tasks: Model, Analysis, and Design Issues - 09.6_1
C
- Cabodi, G.
- [277] [278] Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization - 05.5_4
- Cacciari, Matteo
- [177] [178] Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2
- Calimera, Andrea
- [279] [280] Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits - 09.7_7
- Canal, Ramon
- [281] [282] SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis - 02.7_3
- Canal, Ramon
- [67] [68] INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4
- Canal, Ramon
- [283] [284] DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy - 04.5_5
- Canedo, Arquimedes
- [55] [56] Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems - 11.3_5
- Canelas, António
- [285] [286] Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1
- Cannella, Emanuele
- [159] [160] System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach - 12.5_4
- Caplan, Jonah
- [287] [288] Trade-offs in Execution Signature Compression for Reliable Processor Systems - 04.7_3
- Cappello, F.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
- Carmona, C.
- [77] [78] Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications - 06.7_2
- Carro, L.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
- Carvajal, Gonzalo
- [141] [142] Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications - 10.6_3
- Casamassima, Filippo
- [211] [212] Context Aware Power Management for Motion-sensing Body Area Network Nodes - 07.3_3
- Caspar, Mirko
- [289] [290] Automated System Testing Using Dynamic and Resource Restricted Clients - 11.4_6
- Castellana, Vito Giovanni
- [291] [292] An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems - 07.4_7
- Castrillon, Jeronimo
- [121] [122] Automatic Detection of Concurrency Bugs through Event Ordering Constraints - 10.4_1
- Castro-López, R.
- [293] [294] Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits - 02.4_3
- Catania, Vincenzo
- [127] [128] An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs - 10.2_1
- Catthoor, Francky
- [295] [296] Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3
- Catthoor, Francky
- [25] [26] Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2
- Catthoor, Francky
- [133] [134] Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3
- Catthoor, Francky
- [39] [40] Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1
- Catthoor, Francky
- [29] [30] Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5
- Cauwenberghs, Gert
- [297] [298] Video Analytics Using Beyond CMOS Devices - 12.1_3
- Cavazzoni, Carlo
- [177] [178] Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2
- Cazorla, Francisco J.
- [3] [4] Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2
- Cech, Christian
- [299] [300] Power Modeling and Analysis in Early Design Phases - 08.1_1
- Cha, Daeseo
- [301] [302] Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6
- Chakrabarty, Krishnendu
- [303] [304] Multi-Site Test Optimization for Multi-Vdd SoCs Using Space- and Time-Division Multiplexing - 05.7_4
- Chakraborty, Koushik
- [305] [306] DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors - 03.7_3
- Chakraborty, Samarjit
- [103] [104] Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3
- Chakraborty, Samarjit
- [307] [308] Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3
- Chandra, Vikas
- [309] [310] Cross Layer Resiliency in Real World - 07.2
- Chandramoorthy, Nandhini
- [311] [312] Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2
- Chandrasekar, Karthik
- [47] [48] Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1
- Chang, Doohwang
- [313] [314] Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation - 02.7_6
- Chang, Naehyuck
- [315] [316] Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles - 05.4_4
- Chang, Naehyuck
- [317] [318] Optimal Design and Management of a Smart Residential PV and Energy Storage System - 06.3_4
- Chang, Naehyuck
- [319] [320] FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4
- Chang, Ru-Hua
- [321] [322] Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs - 11.5_1
- Chang, Shih-Chieh
- [323] [324] Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5
- Chang, Shih-Chieh
- [325] [326] Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6
- Chang, Yuan-Hao
- [327] [328] Garbage Collection for Multi-version Index on Flash Memory - 03.6_4
- Chappert, Claude
- [329] [330] Spintronics for Low-Power Computing - 11.1_1
- Chatterjee, Debapriya
- [223] [224] ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1
- Chen, Chien-Hao
- [331] [332] An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations - 08.5_1
- Chen, Deming
- [333] [334] Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3
- Chen, Gang
- [335] [336] Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3
- Chen, Hu
- [305] [306] DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors - 03.7_3
- Chen, Hung-Ming
- [337] [338] Cost-Effective Decap Selection for Beyond Die Power Integrity - 03.4_6
- Chen, Hung-Ming
- [339] [340] Memcomputing: The Cape of Good Hope - 09.8_1
- Chen, Jian-Yu
- [341] [342] Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints - 05.6_6
- Chen, Kevin J.
- [343] [344] Characterizing Power Delivery Systems with On/Off-Chip Voltage Regulators for Many-Core Processors - 03.4_7
- Chen, Licheng
- [345] [346] Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests - 04.5_1
- Chen, Lizhong
- [347] [348] Application Mapping for Express Channel-Based Networks-on-Chip - 09.2_1
- Chen, Mingyu
- [345] [346] Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests - 04.5_1
- Chen, Qiuwen
- [349] [350] Battery Aware Stochastic QoS Boosting in Mobile Computing Devices - 07.3_5
- Chen, Shi-Hao
- [337] [338] Cost-Effective Decap Selection for Beyond Die Power Integrity - 03.4_6
- Chen, Shuang
- [351] [352] Concurrent Placement, Capacity Provisioning, and Request Flow Control for a Distributed Cloud Infrastructure - 10.3_4
- Chen, Shu-Yung
- [331] [332] An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations - 08.5_1
- Chen, Tai-Chen
- [353] [354] Design-for-Debug Routing for FIB Probing - 11.4_4
- Chen, Weiwei
- [355] [356] May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models - 10.5_1
- Chen, Yi-En
- [337] [338] Cost-Effective Decap Selection for Beyond Die Power Integrity - 03.4_6
- Chen, Yi-Hang
- [341] [342] Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints - 05.6_6
- Chen, Yi-Jung
- [321] [322] Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs - 11.5_1
- Chen, Ying-Yu
- [333] [334] Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3
- Chen, Yiran
- [357] [358] ICE: Inline Calibration for Memristor Crossbar-based Computing Engine - 07.5_5
- Chen, Yiran
- [359] [360] Energy Efficient Neural Networks for Big Data Analytics - 12.1_4
- Chen, Yi-Ting
- [321] [322] Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs - 11.5_1
- Chen, Yong
- [361] [362] A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6
- Chen, Yuankai
- [363] [364] Recovery-Based Resilient Latency-Insensitive Systems - 05.3_4
- Chen, Yu-Guang
- [325] [326] Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6
- Chen, Yung-Chih
- [365] [366] Rewiring for Threshold Logic Circuit Minimization - 05.6_4
- Chen, Yung-Chih
- [367] [368] Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5
- Cheng, Kwang-Ting
- [369] [370] Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction - 08.7_2
- Cheshmi, Kazem
- [371] [372] CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2
- Cheung, Peter Y.K.
- [255] [256] Image Progressive Acquisition for Hardware Systems - 12.3_3
- Chevallaz, Christophe
- [373] [374] Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8
- Chiang, Chang-En
- [367] [368] Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5
- Chiang, Charles C.
- [101] [102] Signature Indexing of Design Layouts for Hotspot Detection - 12.4_2
- Chiarulli, Don
- [297] [298] Video Analytics Using Beyond CMOS Devices - 12.1_3
- Chien, Hsi-An
- [375] [376] Mask-Cost-Aware ECO Routing - 03.4_8
- Chien, Jui-Hung
- [323] [324] Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5
- Chien, Tzu-Kai
- [377] [378] Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost - 12.4_3
- Childers, Bruce R.
- [379] [380] Program Affinity Performance Models for Performance and Utilization - 02.5_5
- Chinea, A.
- [163] [164] Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications - 03.4_1
- Cho, Yeongon
- [381] [382] Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1
- Cibrario, Gérald
- [185] [186] 3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4
- Ciesielski, Maciej J.
- [37] [38] Fast STA Prediction-based Gate-level Timing Simulation - 09.4_1
- Ciganda, Lyl
- [195] [196] An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3
- Cilardo, Alessandro
- [383] [384] Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems - 11.7_5
- Clay, Steve
- [385] [386] Cross-correlation of Specification and RTL for Soft IP Analysis - 10.5_4
- Clediere, Jessy
- [387] [388] Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1
- Clermidy, Fabien
- [243] [244] Resistive Memories: Which Applications? - 10.1_4
- Clermidy, Fabien
- [185] [186] 3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4
- Comte, M.
- [137] [138] New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7
- Cong, Kai
- [389] [390] Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes - 11.4_2
- Conos, Nathaniel A.
- [391] [392] Provably Minimal Energy Using Coordinated DVS and Power Gating - 10.7_1
- Conti, Francesco
- [209] [210] Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3
- Cook, Alejandro
- [1] [2] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1
- Corporaal, H.
- [17] [18] Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2
- Cortadella, J.
- [393] [394] Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8
- Cortez, Mafalda
- [395] [396] Testing PUF-Based Secure Key Storage Circuits - 07.7_2
- Coskun, Ayse K.
- [5] [6] Thermal Management of Manycore Systems with Silicon-Photonic Networks 11.2_2
- Costenaro, Enrico
- [65] [66] Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1
- Costenaro, Enrico
- [67] [68] INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4
- Coussy, Philippe
- [203] [204] A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7
- Cristal, Adrian
- [265] [266] EVX: Vector Execution on Low Power EDGE Cores - 02.5_4
- Crouch, Al
- [397] [398] Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network - 07.7_3
D
- Dabiri, Foad
- [391] [392] Provably Minimal Energy Using Coordinated DVS and Power Gating - 10.7_1
- Dahir, Nizar
- [61] [62] Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4
- Damodaran, Preethi P.
- [399] [400] Distributed Cooperative Shared Last-Level Caching in Tiled Multiprocessor System on Chip - 04.5_7
- Daneshtalab, Masoud
- [401] [402] Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model - 11.6_5
- Danger, Jean-Luc
- [403] [404] Hacking and Protecting IC Hardware - 05.2
- Danilo, Robin
- [203] [204] A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7
- Das, A.
- [247] [248] Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs - 03.7_2
- Das, Anup
- [405] [406] Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia MPSoCs - 05.3_3
- Dasgupta, Pallab
- [165] [166] Acceptance and Random Generation of Event Sequences under Real Time Calculus Constraints - 09.6_2
- Das Kunungo, P.
- [253] [254] III-V Semiconductor Nanowires for Future Devices - 09.1_1
- Datta, Suman
- [367] [368] Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5
- Datta, Suman
- [297] [298] Video Analytics Using Beyond CMOS Devices - 12.1_3
- Davis, Robert I.
- [81] [82] On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis - 02.6_1
- De Micheli, Giovanni
- [43] [44] Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2
- De Micheli, Giovanni
- [87] [88] Advanced System on a Chip Design Based on Controllable-Polarity FETs - 09.1_2
- De Micheli, Giovanni
- [89] [90] An Efficient Manipulation Package for Biconditional Binary Decision Diagrams - 10.7_3
- Deb, Abhijit
- [407] [408] Startup Error Detection and Containment to Improve the Robustness of Hybrid FlexRay Networks - 02.3_2
- DeBardeleben, N.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
- Dehbaoui, Amine
- [387] [388] Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1
- Del Bel, Brandon
- [409] [410] Improving STT-MRAM Density through Multibit Error Correction - 07.5_3
- Delvaux, Jeroen
- [411] [412] Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation - 04.3_4
- Deng, Peng
- [413] [414] MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2
- Deng, Qingxu
- [415] [416] Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms - 10.6_2
- Devitt, Simon
- [417] [418] Software-based Pauli Tracking in Fault-tolerant Quantum Circuits - 05.6_7
- Dhruva, Neil
- [419] [420] Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems - 07.6_2
- Di Carlo, Stefano
- [225] [226] SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3
- Di Natale, Giorgio
- [403] [404] Hacking and Protecting IC Hardware - 05.2
- Di Natale, Giorgio
- [395] [396] Testing PUF-Based Secure Key Storage Circuits - 07.7_2
- Di Pendina, G.
- [421] [422] Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3
- Diemer, Jonas
- [41] [42] Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5
- Dieny, B.
- [421] [422] Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3
- Dietrich, Manfred
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Dimitrakopoulos, G.
- [423] [424] ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers - 09.2_3
- Dimitrakopoulos, G.
- [393] [394] Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8
- Ding, Huping
- [425] [426] WCET-Centric Dynamic Instruction Cache Locking - 02.6_2
- Dinh, Trung Anh
- [427] [428] A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips - 04.4_3
- Disch, Stefan
- [79] [80] Simple Interpolants for Linear Arithmetic - 05.5_3
- Doan, Hong Chinh
- [429] [430] Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs - 12.3_1
- Doboli, Alex
- [431] [432] Novel Circuit Topology Synthesis Method Using Circuit Feature Mining and Symbolic Comparison - 02.4_8
- Dogan, Ahmed
- [107] [108] Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1
- Dogaru, Emanuel
- [433] [434] A Flexible BIST Strategy for SDR Transmitters - 12.7_3
- Dömer, Rainer
- [355] [356] May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models - 10.5_1
- Domic, Antun
- [43] [44] Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2
- Dong, Chuansheng
- [435] [436] Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms - 02.6_3
- Dou, Wenhua
- [437] [438] SAFE: Security-Aware FlexRay Scheduling Engine - 02.3_5
- Drechsler, Rolf
- [439] [440] Towards Verifying Determinism of SystemC Designs - 06.5_6
- Drechsler, Rolf
- [373] [374] Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8
- Du, Yuelin
- [441] [442] Optimization of Standard Cell Based Detailed Placement for 16 nm FinFET Process - 12.4_1
- Duan, Guangshan
- [443] [444] Exploiting Narrow-Width Values for Improving Non-Volatile Cache Lifetime - 03.5_4
- Dubois, Michel
- [105] [106] Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W - 05.3_2
- Dündar, Günhan
- [19] [20] Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5
- Dupont de Dinechin, Benoît
- [445] [446] Time-Critical Computing on a Single Chip Massively Parallel Processor - 05.1_2
- Duric, Milovan
- [265] [266] EVX: Vector Execution on Low Power EDGE Cores - 02.5_4
- Dutertre, Jean-Max
- [387] [388] Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1
- Dutoit, Denis
- [179] [180] Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4
- Dutt, Nikil
- [447] [448] Minimal Sparse Observability of Complex Networks: Application to MPSoC Sensor Placement and Run-time Thermal Estimation & Tracking - 11.6_1
- Duy, Viet Vu
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Dweik, Waleed
- [105] [106] Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W - 05.3_2
- Dworak, Jennifer
- [397] [398] Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network - 07.7_3
- Dwyer, Chris
- [449] [450] RETLab: A Fast Design-automation Framework for Arbitrary RET Networks - 05.6_1
E
- Ebi, Thomas
- [99] [100] mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2
- Ebrahimi, Mojtaba
- [65] [66] Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1
- Ebrahimi, Mojtaba
- [241] [242] Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM - 07.5_1
- Ebrahimi, Mojtaba
- [451] [452] Aging-aware Standard Cell Library Design - 09.7_6
- Echeverri, Juan
- [453] [454] Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling - 11.3_2
- Echeverri, Juan Diego
- [455] [456] Standard Cell Library Tuning for Variability Tolerant Designs - 08.7_4
- Ecker, Wolfgang
- [457] [458] The Metamodeling Approach to System Level Synthesis - 11.3_1
- Eles, Petru
- [91] [92] Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees - 03.6_2
- Eles, Petru
- [27] [28] An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs - 05.7_5
- Elfadel, Ibrahim (Abe) M.
- [111] [112] Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1
- Elfadel, Ibrahim (Abe) M.
- [459] [460] Unified, Ultra Compact, Quadratic Power Proxies for Multi-Core Processors - 11.6_6
- Engelke, Piet
- [1] [2] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1
- Erb, Dominik
- [193] [194] Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1
- Ernst, Rolf
- [41] [42] Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5
- Eusse, Juan Fernando
- [125] [126] A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2
- Evans, Adrian
- [65] [66] Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1
- Evans, Adrian
- [9] [10] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5
- Eyole, Mbou
- [71] [72] Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6
F
- Fabrie, Sebastien
- [455] [456] Standard Cell Library Tuning for Variability Tolerant Designs - 08.7_4
- Fahrny, Jim
- [461] [462] ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design - 04.3_1
- Falk, Joachim
- [463] [464] Model-Based Actor Multiplexing with Application to Complex Communication Protocols 08.5_4
- Fan, Deliang
- [465] [466] Brain-Inspired Computing with Spin Torque Devices - 08.8_2
- Fang, B.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
- Farahpour, Nazanin
- [39] [40] Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1
- Farbeh, Hamed
- [467] [468] PSP-Cache: A Low-Cost Fault-Tolerant Cache Memory Architecture - 06.7_5
- Farella, Elisabetta
- [211] [212] Context Aware Power Management for Motion-sensing Body Area Network Nodes - 07.3_3
- Farhady Ghalaty, Nahid
- [139] [140] Analyzing and Eliminating the Causes of Fault Sensitivity Analysis - 08.3_2
- Farmahini-Farahani, Amin
- [33] [34] Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4
- Feng, Philip X.-L.
- [231] [232] Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3
- Feng, Tao
- [167] [168] Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3
- Ferent, Cristian
- [431] [432] Novel Circuit Topology Synthesis Method Using Circuit Feature Mining and Symbolic Comparison - 02.4_8
- Fernández, F.V.
- [293] [294] Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits - 02.4_3
- Fernández, F.V.
- [19] [20] Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5
- Fernández Villena, Jorge
- [469] [470] Efficient Analysis of Variability Impact on Interconnect Lines and Resistor Networks - 03.4_2
- Ferrandi, Fabrizio
- [291] [292] An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems - 07.4_7
- Ferro, Luca
- [93] [94] Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4
- Finn, John B.
- [471] [472] Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems 03.6_6
- Firouzi, Farshad
- [473] [474] P/G TSV Planning for IR-drop Reduction in 3D-ICs - 03.4_4
- Firouzi, Farshad
- [451] [452] Aging-aware Standard Cell Library Design - 09.7_6
- Fischer, Peter
- [475] [476] Thinfilm Printed Ferro-Electric Memories and Integrated Products - 10.1_5
- Fischer, Viktor
- [217] [218] On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models - 03.3_2
- Fischer, Bernhard
- [299] [300] Power Modeling and Analysis in Early Design Phases - 08.1_1
- Fischmeister, Sebastian
- [141] [142] Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications - 10.6_3
- Flores, Paulo
- [51] [52] Optimization of Design Complexity in Time-Multiplexed Constant Multiplications - 10.7_7
- Forte, Domenic
- [461] [462] ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design - 04.3_1
- Fourmigue, Alain
- [201] [202] Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias - 04.4_2
- Fradet, Pascal
- [273] [274] Verification-guided Voter Minimization in Triple-Modular Redundant Circuits - 04.7_2
- Francillon, Aurélien
- [477] [478] A Minimalist Approach to Remote Attestation - 09.3_2
- Friedler, Ophir
- [479] [480] Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3
- Frijns, R.M.W.
- [17] [18] Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2
- Fu, Jian
- [481] [482] A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor - 03.7_4
- Fujiwara, Ikki
- [85] [86] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3
- Fummi, F.
- [251] [252] A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2
- Fummi, Franco
- [483] [484] Moving from Co-Simulation to Simulation for Effective Smart Systems Design - 10.4_5
- Fummi, Franco
- [373] [374] Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8
- Fusella, Edoardo
- [383] [384] Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems - 11.7_5
G
- Gabrielli, Giacomo
- [71] [72] Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6
- Gaillardon, Pierre-Emmanuel
- [87] [88] Advanced System on a Chip Design Based on Controllable-Polarity FETs - 09.1_2
- Gaillardon, Pierre-Emmanuel
- [89] [90] An Efficient Manipulation Package for Biconditional Binary Decision Diagrams - 10.7_3
- Gal, Raviv
- [223] [224] ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1
- Galfano, Salvatore
- [225] [226] SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3
- Gallo, Luca
- [383] [384] Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems - 11.7_5
- Galzur, Ori
- [109] [110] Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2
- Ganapathy, Shrikanth
- [67] [68] INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4
- Gangopadhya, Samantak
- [237] [238] Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3
- Gao, Yue
- [485] [486] An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems - 04.7_4
- García-Ortiz, Alberto
- [275] [276] DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs. - 11.2_4
- Geilen, M.C.W.
- [17] [18] Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2
- Geilen, Marc
- [183] [184] Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming - 11.5_3
- Gemmeke, Tobias
- [133] [134] Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3
- Geraci, James R.
- [487] [488] Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5
- Geng, Hui
- [413] [414] MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2
- Ghasemazar, Amin
- [23] [24] Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions - 08.6_7
- Ghiribaldi, Alberto
- [181] [182] Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3
- Gholipour, Morteza
- [333] [334] Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3
- Giannopoulou, Georgia
- [489] [490] Mapping Mixed-Criticality Applications on Multi-Core Architectures - 05.1_3
- Giannopoulou, Georgia
- [419] [420] Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems - 07.6_2
- Gimmler-Dumont, Christina
- [9] [10] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5
- Gines, Antonio
- [491] [492] Sigma-Delta Testability for Pipeline A/D Converters - 12.7_4
- Girault, Alain
- [273] [274] Verification-guided Voter Minimization in Triple-Modular Redundant Circuits - 04.7_2
- Gladigau, Jens
- [235] [236] A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving - 08.5_5
- Glaβ, Michael
- [493] [494] A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3
- Glaβ, Michael
- [495] [496] Multi-Variant-based Design Space Exploration for Automotive Embedded Systems - 02.3_4
- Glaβ, Michael
- [497] [498] Multi-Objective Distributed Run-time Resource Management for Many-Cores - 08.6_3
- Glaβ, Michael
- [9] [10] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5
- Glaβ, Michael
- [1] [2] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1
- Goens, Andrés
- [123] [124] Optimized Buffer Allocation in Multicore Platforms - 11.5_2
- Gómez Pérez, José Ignacio
- [295] [296] Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3
- Gomony, Manil Dev
- [45] [46] Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems - 03.5_1
- Goncalves, O.
- [421] [422] Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3
- González, Antonio
- [67] [68] INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4
- Goossens, Kees
- [45] [46] Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems - 03.5_1
- Goossens, Kees
- [47] [48] Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1
- Goossens, Kees
- [227] [228] CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4
- Goossens, Sven
- [47] [48] Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1
- Goryachev, Alex
- [373] [374] Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8
- Goswami, Dip
- [103] [104] Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3
- Goyal, Ajay
- [457] [458] The Metamodeling Approach to System Level Synthesis - 11.3_1
- Graf, Sebastian
- [495] [496] Multi-Variant-based Design Space Exploration for Automotive Embedded Systems - 02.3_4
- Grani, Paolo
- [181] [182] Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3
- Gregorek, Daniel
- [275] [276] DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs. - 11.2_4
- Grijnevitch, Inna
- [15] [16] Facilitating Timing Debug by Logic Path Correspondence - 09.7_1
- Grimm, Christoph
- [499] [500] Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1
- Grimm, Christoph
- [501] [502] Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities - 02.4_7
- Grinchtein, Olga
- [157] [158] Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP - 07.6_5
- Grivet-Talocia, S.
- [163] [164] Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications - 03.4_1
- Gross, Kenny
- [135] [136] Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1
- Grube, Matthias
- [503] [504] Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3
- Grünewald, Armin
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Gu, Chuancai
- [415] [416] Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms - 10.6_2
- Guan, Nan
- [505] [506] General and Efficient Response Time Analysis for EDF Scheduling - 09.6_3
- Guan, Nan
- [415] [416] Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms - 10.6_2
- Guarnieri, V.
- [251] [252] A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2
- Guerre, Alexandre
- [11] [12] A Unified Methodology for a Fast Benchmarking of Parallel Architecture - 07.6_7
- Guerre, Alexandre
- [93] [94] Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4
- Guillaume-Sage, Ludovic
- [387] [388] Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1
- Güneysu, Tim
- [507] [508] Lightweight Code-based Cryptography: QC-MDPC McEliece Encryption on Reconfigurable Devices - 03.3_1
- Guo, Hui
- [509] [510] EATBit: Effective Automated Test for Binary Translation with High Code Coverage - 04.6_1
- Gupta, Rajesh K.
- [207] [208] Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs - 05.3_1
- Gupta, Sandeep K.
- [485] [486] An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems - 04.7_4
- Gurumurthi, S.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
H
- Ha, Soonhoi
- [145] [146] Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5
- Ha, Yajun
- [511] [512] Thermal-Aware Frequency Scaling for Adaptive Workloads on Heterogeneous MPSoCs - 10.6_1
- Haase, Joachim
- [513] [514] Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5
- Haddad, Patrick
- [217] [218] On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models - 03.3_2
- Hahn, Kai
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Hairbucher, Jürgen
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Halak, Basel
- [515] [516] A Low-Cost Radiation Hardened Flip-flop - 06.7_4
- Hamdioui, Said
- [25] [26] Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2
- Hamdioui, Said
- [403] [404] Hacking and Protecting IC Hardware - 05.2
- Hamdioui, Said
- [517] [518] Interconnect Test for 3D Stacked Memory-on-Logic - 05.7_2
- Hamdioui, Said
- [395] [396] Testing PUF-Based Secure Key Storage Circuits - 07.7_2
- Han, Gang
- [437] [438] SAFE: Security-Aware FlexRay Scheduling Engine - 02.3_5
- Han, Jaehoon
- [301] [302] Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6
- Han, Jie
- [519] [520] A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery - 04.7_5
- Han, Jie
- [521] [522] A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction - 06.7_6
- Han, Seung-Soo
- [523] [524] A Deep Learning Methodology to Proliferate Golden Signoff Timing - 09.7_4
- Han, Xu
- [355] [356] May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models - 10.5_1
- Han, Yinhe
- [525] [526] SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing - 06.4_2
- Hannig, Frank
- [527] [528] Code Generation for Embedded Heterogeneous Architectures on Android - 04.6_3
- Hao, Kecheng
- [529] [530] Equivalence Checking for Function Pipelining in Behavioral Synthesis - 06.5_3
- Hardt, Wolfram
- [289] [290] Automated System Testing Using Dynamic and Resource Restricted Clients - 11.4_6
- Harrant, Manuel
- [499] [500] Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1
- Harrant, Manuel
- [259] [260] Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3
- Hartmann, Matthias
- [295] [296] Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3
- Haubelt, Christian
- [463] [464] Model-Based Actor Multiplexing with Application to Complex Communication Protocols 08.5_4
- Haubelt, Christian
- [235] [236] A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving - 08.5_5
- Hayes, John P.
- [57] [58] Fast and Accurate Computation Using Stochastic Circuits - 04.4_4
- Hayes, Michael
- [531] [532] Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5
- He, Tina
- [231] [232] Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3
- He, Xin
- [525] [526] SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing - 06.4_2
- He, Ruining
- [509] [510] EATBit: Effective Automated Test for Binary Translation with High Code Coverage - 04.6_1
- He, Yanxiang
- [361] [362] A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6
- Heidmann, Nils
- [533] [534] Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4
- Heinig, Andy
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Heinzig, André
- [503] [504] Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3
- Helfmeier, Clemens
- [245] [246] Physical Vulnerabilities of Physically Unclonable Functions - 12.2_5
- Hellwege, Nico
- [533] [534] Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4
- Hély, David
- [219] [220] A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4
- Henkel, Jörg
- [161] [162] dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2
- Henkel, Jörg
- [535] [536] Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7
- Henkel, Jörg
- [537] [538] Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing - 08.6_1
- Henkel, Jörg
- [97] [98] hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6
- Henkel, Jörg
- [99] [100] mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2
- Henker, S.
- [539] [540] Integrated Circuits Processing Chemical Information: Prospects and Challenges - 12.1_1
- Henrichsen, Arne
- [541] [542] Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems - 04.2_3
- Henriksson, Tomas
- [123] [124] Optimized Buffer Allocation in Multicore Platforms - 11.5_2
- Hensel, Burkhard
- [543] [544] The Energy Benefit of Level-crossing Sampling Including the Actuator's Energy Consumption - 06.3_7
- Heo, Deukhyoun
- [545] [546] Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies - 10.2_2
- Herber, Christian
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Herkersdorf, Andreas
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Herkersdorf, Andreas
- [399] [400] Distributed Cooperative Shared Last-Level Caching in Tiled Multiprocessor System on Chip - 04.5_7
- Herkersdorf, Andreas
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Herkersdorf, Andreas
- [9] [10] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5
- Hess, Christopher
- [111] [112] Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1
- Hill, Stephen
- [73] [74] Clock-Modulation Based Watermark for Protection of Embedded Processors - 03.3_3
- Hiller, Matthias
- [547] [548] Increasing the Efficiency of Syndrome Coding for PUFs with Helper Data Compression - 04.3_3
- Ho, Tsung-Yi
- [427] [428] A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips - 04.4_3
- Ho, Tsung-Yi
- [549] [550] A Thermal Resilient Integration of Many-core Microprocessors and Main Memory by 2.5D TSI I/Os - 07.4_5
- Hochapfel, Erik
- [147] [148] Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL - 08.4_2
- Hoffman, Caio
- [113] [114] Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5
- Höhlein, Tim
- [533] [534] Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4
- Holcomb, Daniel E.
- [551] [552] PUFs at a Glance - 12.2_2
- Homayoun, Houman
- [117] [118] Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design - 11.7_1
- Hon, Wing-Kai
- [325] [326] Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6
- Hong, Seongsoo
- [487] [488] Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5
- Horrein, Pierre-Henri
- [147] [148] Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL - 08.4_2
- Horstmann, Manfred
- [43] [44] Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2
- Horta, Nuno
- [285] [286] Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1
- Hortváth, András
- [553] [554] Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3
- Hoskote, Yatin
- [555] [556] Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism - 12.5_3
- Hsieh, Jen-Wei
- [327] [328] Garbage Collection for Multi-version Index on Flash Memory - 03.6_4
- Hsu, Chang-Hong
- [223] [224] ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1
- Hsu, Chun-Kai
- [369] [370] Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction - 08.7_2
- Hsu, Ruei-Siang
- [323] [324] Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5
- Hu, Alan J.
- [373] [374] Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8
- Hu, X. Sharon
- [557] [558] Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study - 05.6_2
- Hu, X. Sharon
- [553] [554] Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3
- Hu, Yu
- [559] [560] Partial-SET: Write Speedup of PCM Main Memory - 03.5_5
- Huang, Ching-Yi
- [365] [366] Rewiring for Threshold Logic Circuit Minimization - 05.6_4
- Huang, Ching-Yi
- [367] [368] Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5
- Huang, Juinn-Dar
- [341] [342] Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints - 05.6_6
- Huang, Libo
- [561] [562] Leveraging On-Chip Networks for Efficient Prediction on Multicore Coherence - 07.4_6
- Huang, Pengcheng
- [489] [490] Mapping Mixed-Criticality Applications on Multi-Core Architectures - 05.1_3
- Huang, Po-Chun
- [327] [328] Garbage Collection for Multi-version Index on Flash Memory - 03.6_4
- Huang, Shih-Hsu
- [563] [564] Leakage-Power-Aware Clock Period Minimization - 09.7_3
- Huang, Zhengfeng
- [565] [566] A High Performance SEU-Tolerant Latch for Nanoscale CMOS Technology - 06.7_3
- Hum, Robert
- [43] [44] Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2
- Hum, Robert
- [109] [110] Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2
- Hwang, Hyeon I
- [567] [568] A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4
I
- Iannopollo, Antonio
- [471] [472] Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems 03.6_6
- Iannopollo, Antonio
- [569] [570] Library-Based Scalable Refinement Checking for Contract-Based Design - 06.6_1
- Ienne, Paolo
- [191] [192] SKETCHILOG: Sketching Combinational Circuits - 06.5_5
- Ienne, Paolo
- [39] [40] Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1
- Iliasov, Alex
- [63] [64] Design of Safety Critical Systems by Refinement - 04.6_4
- Imhof, Michael E.
- [571] [572] Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test - 07.7_1
- Indaco, Marco
- [225] [226] SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3
- Ivanov, Radoslav
- [573] [574] Attack-Resilient Sensor Fusion - 03.6_1
- Izu, Cruz
- [575] [576] Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs - 09.2_4
J
- Jaber, K.
- [421] [422] Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3
- Jain, Arvind
- [303] [304] Multi-Site Test Optimization for Multi-Vdd SoCs Using Space- and Time-Division Multiplexing - 05.7_4
- Jaksić, Zoran
- [283] [284] DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy - 04.5_5
- Jalle, Javier
- [3] [4] Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2
- Jancke, Roland
- [513] [514] Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5
- Jantsch, Axel
- [577] [578] Parallel Probe Based Dynamic Connection Setup in TDM NoCs - 09.2_2
- Javaid, Haris
- [579] [580] Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs - 10.4_2
- Javaid, Haris
- [429] [430] Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs - 12.3_1
- Jeong, Jae Woong
- [581] [582] Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2
- Jerke, Goeran
- [583] [584] Mission Profile Aware IC Design - A Case Study - 03.8_2
- Jesshope, Chris R.
- [481] [482] A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor - 03.7_4
- Jiang, Yingtao
- [401] [402] Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model - 11.6_5
- Jiang, Nan
- [361] [362] A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6
- Jin, Yier
- [585] [586] Real-Time Trust Evaluation in Integrated Circuits - 04.7_1
- Jin, Yier
- [587] [588] EDA Tools Trust Evaluation through Security Property Proofs - 09.3_5
- Jones, Timothy M.
- [589] [590] ALLARM: Optimizing Sparse Directories for Thread-Local Data - 04.5_2
- Jonna, Gnaneswara Rao
- [591] [592] Minimally Buffered Single-Cycle Deflection Router - 11.2_5
- Joosten, Sebastiaan J.C.
- [593] [594] Scalable Liveness Verification for Communication Fabrics - 05.5_1
- Jose, John
- [591] [592] Minimally Buffered Single-Cycle Deflection Router - 11.2_5
- Joshi, Ajay
- [595] [596] Sub-threshold Logic Circuit Design Using Feedback Equalization - 05.4_2
- Joshi, Ajay
- [5] [6] Thermal Management of Manycore Systems with Silicon-Photonic Networks 11.2_2
- Jovanovic, Natalija
- [243] [244] Resistive Memories: Which Applications? - 10.1_4
- Jung, Matthias
- [213] [214] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh - 10.3_6
- Junsangsri, Pilin
- [521] [522] A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction - 06.7_6
K
- Kabitzsch, Klaus
- [543] [544] The Energy Benefit of Level-crossing Sampling Including the Actuator's Energy Consumption - 06.3_7
- Kaczer, Ben
- [25] [26] Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2
- Kadry, Wisam
- [479] [480] Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3
- Kagami, Takahiro
- [85] [86] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3
- Kahng, Andrew B.
- [583] [584] Mission Profile Aware IC Design - A Case Study - 03.8_2
- Kahng, Andrew B.
- [597] [598] Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement - 07.7_4
- Kahng, Andrew B.
- [523] [524] A Deep Learning Methodology to Proliferate Golden Signoff Timing - 09.7_4
- Kamal, Mehdi
- [23] [24] Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions - 08.6_7
- Kang, Shin-Haeng
- [145] [146] Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5
- Kang, Wang
- [329] [330] Spintronics for Low-Power Computing - 11.1_1
- Kang, Ilgweon
- [597] [598] Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement - 07.7_4
- Karakonstantis, Georgios
- [131] [132] A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4
- Karam, Robert
- [233] [234] Energy-Efficient Hardware Acceleration through Computing in the Memory - 09.8_3
- Karg, S.
- [253] [254] III-V Semiconductor Nanowires for Future Devices - 09.1_1
- Karkar, Ammar
- [61] [62] Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4
- Karlsson, Christer
- [475] [476] Thinfilm Printed Ferro-Electric Memories and Integrated Products - 10.1_5
- Karri, Ramesh
- [313] [314] Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation - 02.7_6
- Karvouniari, Anna
- [599] [600] Spatial Pattern Prediction Based Management of Faulty Data Caches - 03.7_1
- Katzschke, C.
- [171] [172] Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4
- Kauer, Matthias
- [103] [104] Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3
- Kauer, Matthias
- [307] [308] Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3
- Kaule, Dirk
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Kavousianos, Xrysovalantis
- [303] [304] Multi-Site Test Optimization for Multi-Vdd SoCs Using Space- and Time-Division Multiplexing - 05.7_4
- Keramidas, Georgios
- [599] [600] Spatial Pattern Prediction Based Management of Faulty Data Caches - 03.7_1
- Kerkhoff, Hans G.
- [601] [602] An Embedded Offset and Gain Instrument for OpAmp IPs - 02.4_9
- Kerzerho, V.
- [137] [138] New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7
- Khaleghi, Behnam
- [35] [36] A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology - 11.7_2
- Khan, Muhammad Usman Karim
- [537] [538] Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing - 08.6_1
- Khan, Seyab
- [25] [26] Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2
- Khdr, Heba
- [99] [100] mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2
- Kiamehr, Saman
- [451] [452] Aging-aware Standard Cell Library Design - 09.7_6
- Kim, BaekGyu
- [567] [568] A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4
- Kim, Chris H.
- [409] [410] Improving STT-MRAM Density through Multibit Error Correction - 07.5_3
- Kim, Dongyoung
- [603] [604] Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3
- Kim, Geunho
- [605] [606] Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs - 09.7_8
- Kim, Hayoung
- [603] [604] Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3
- Kim, Jae-Joon
- [603] [604] Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3
- Kim, Jay
- [301] [302] Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6
- Kim, John
- [381] [382] Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1
- Kim, Jongyeon
- [409] [410] Improving STT-MRAM Density through Multibit Error Correction - 07.5_3
- Kim, Jungsoo
- [135] [136] Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1
- Kim, Kibeom
- [487] [488] Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5
- Kim, Kitae
- [319] [320] FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4
- Kim, Moon Seok
- [311] [312] Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2
- Kim, Myungsun
- [487] [488] Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5
- Kim, Namdo
- [301] [302] Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6
- Kim, Nam Sung
- [33] [34] Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4
- Kim, Ryan
- [545] [546] Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies - 10.2_2
- Kim, Sungchan
- [145] [146] Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5
- Kim, Taemin
- [555] [556] Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism - 12.5_3
- Kim, Taewhan
- [605] [606] Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs - 09.7_8
- Kirscher, Jérôme
- [499] [500] Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1
- Klauk, Hagen
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Kleeberger, Veit B.
- [9] [10] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5
- Klein, Jacques-Olivier
- [329] [330] Spintronics for Low-Power Computing - 11.1_1
- Kobyashi, Hiroaki
- [83] [84] Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1
- Koedam, Martijn
- [47] [48] Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1
- Koedam, Martijn
- [227] [228] CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4
- Koibuchi, Michihiro
- [85] [86] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3
- Komalan, Manu
- [295] [296] Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3
- Komoda, Toshiya
- [83] [84] Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1
- Kondo, Masaaki
- [83] [84] Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1
- Kong, Pingfan
- [607] [608] Energy Efficient In-Memory AES Encryption Based on Nonvolatile Domain-wall Nanowire - 07.5_4
- König, Markus
- [503] [504] Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3
- Könighofer, Robert
- [609] [610] Partial Witnesses from Preprocessed Quantified Boolean Formulas - 06.5_2
- Kordes, Alexander
- [407] [408] Startup Error Detection and Containment to Improve the Robustness of Hybrid FlexRay Networks - 02.3_2
- Kosmidis, Leonidas
- [3] [4] Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2
- Koundinya, Pranav
- [167] [168] Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3
- Koushanfar, Farinaz
- [611] [612] D2Cyber: A Design Automation Tool for Dependable Cybercars - 03.6_5
- Koushanfar, Farinaz
- [613] [614] Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder Based Security - 12.2_7
- Kraft, Ulrike
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Kress, Rainer
- [109] [110] Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2
- Kreupl, Franz
- [615] [616] Advancing CMOS with Carbon Electronics - 09.1_4
- Kröhnert, Steffen
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Kriebel, Florian
- [535] [536] Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7
- Kuehlmann, Andreas
- [617] [618] Property Directed Invariant Refinement for Program Verification - 05.5_2
- Kudo, Masaru
- [83] [84] Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1
- Kufel, Jedrzej
- [73] [74] Clock-Modulation Based Watermark for Protection of Embedded Processors - 03.3_3
- Kukner, Halil
- [25] [26] Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2
- Kumar, A.
- [247] [248] Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs - 03.7_2
- Kumar, Akash
- [405] [406] Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia MPSoCs - 05.3_3
- Kumar, Pratyush
- [419] [420] Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems - 07.6_2
- Kumar, Pratyush
- [143] [144] COOLIP: Simple yet Effective Job Allocation for Distributed Thermally-Throttled Processors - 10.3_5
- Kuroda, Tadahiro
- [85] [86] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3
- Kwak, Doowhan
- [301] [302] Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6
L
- Lager, Guillaume
- [445] [446] Time-Critical Computing on a Single Chip Massively Parallel Processor - 05.1_2
- Lagraa, Sofiane
- [619] [620] Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces - 07.6_1
- Lai, Kuan-Yu
- [325] [326] Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6
- Lam, Kam-Yiu
- [327] [328] Garbage Collection for Multi-version Index on Flash Memory - 03.6_4
- Lange, André
- [513] [514] Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5
- Larsson-Edefors, Per
- [169] [170] Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD3) - 04.5_6
- Lauer, Christoph
- [495] [496] Multi-Variant-based Design Space Exploration for Automotive Embedded Systems - 02.3_4
- Lauwereins, Rudy
- [621] [622] Interfacing to Living Cells - 12.1_2
- Layer, C.
- [421] [422] Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3
- Le Beux, Sébastien
- [371] [372] CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2
- Le, Hoang M.
- [439] [440] Towards Verifying Determinism of SystemC Designs - 06.5_6
- Le Nours, Sébastien
- [215] [216] A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures 10.5_3
- Lee, Chia-Yi
- [353] [354] Design-for-Debug Routing for FIB Probing - 11.4_4
- Lee, Doowon
- [221] [222] Brisk and Limited-Impact NoC Routing Reconfiguration - 11.2_1
- Lee, Haeseung
- [53] [54] GPU-EvR: Run-time Event Based Real-time Scheduling Framework on GPGPU Platform - 08.6_2
- Lee, Hsun-Cheng
- [7] [8] A Novel Low Power 11-bit Hybrid ADC Using Flash and Delay Line Architectures - 02.4_6
- Lee, Insup
- [573] [574] Attack-Resilient Sensor Fusion - 03.6_1
- Lee, Insup
- [567] [568] A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4
- Lee, Jungseob
- [33] [34] Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4
- Lee, Ming-Chao
- [325] [326] Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6
- Lee, Minseok
- [381] [382] Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1
- Lee, Sunggu
- [623] [624] Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation - 06.6_6
- Lee, Sunggu
- [603] [604] Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3
- Lee, Young-Joon
- [625] [626] On GPU Bus Power Reduction with 3D IC Technologies - 07.4_3
- Lee, Youngtak
- [237] [238] Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3
- Lee, Woojoo
- [627] [628] VRCon: Dynamic Reconfiguration of Voltage Regulators in a Multicore Platform - 12.6_2
- Leeser, Miriam
- [629] [630] Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic - 05.5_5
- Leger, Gildas
- [491] [492] Sigma-Delta Testability for Pipeline A/D Converters - 12.7_4
- Lei, Li
- [389] [390] Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes - 11.4_2
- Leibe, Bastian
- [125] [126] A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2
- Leo, K.
- [631] [632] Organic Electronics - From Lab to Markets - 11.0
- Letzkus, Florian
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Leupers, Rainer
- [633] [634] Technology Transfer towards Horizon 2020 - 02.8
- Leupers, Rainer
- [119] [120] Time-Decoupled Parallel SystemC Simulation - 07.6_6
- Leupers, Rainer
- [121] [122] Automatic Detection of Concurrency Bugs through Event Ordering Constraints - 10.4_1
- Leupers, Rainer
- [123] [124] Optimized Buffer Allocation in Multicore Platforms - 11.5_2
- Leupers, Rainer
- [125] [126] A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2
- Leveugle, Régis
- [219] [220] A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4
- Levitan, Steve
- [297] [298] Video Analytics Using Beyond CMOS Devices - 12.1_3
- Lhuillier, Yves
- [11] [12] A Unified Methodology for a Fast Benchmarking of Parallel Architecture - 07.6_7
- Li, Bing
- [559] [560] Partial-SET: Write Speedup of PCM Main Memory - 03.5_5
- Li, Boxun
- [357] [358] ICE: Inline Calibration for Memristor Crossbar-based Computing Engine - 07.5_5
- Li, Boxun
- [359] [360] Energy Efficient Neural Networks for Big Data Analytics - 12.1_4
- Li, Hai (Helen)
- [357] [358] ICE: Inline Calibration for Memristor Crossbar-based Computing Engine - 07.5_5
- Li, Helen
- [623] [624] Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation - 06.6_6
- Li, Huawei
- [635] [636] Functional Test Generation Guided by Steady-State Probabilities of Abstract Design - 11.4_5
- Li, Hui
- [371] [372] CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2
- Li, Jiayin
- [637] [638] Write-Once-Memory-Code Phase Change Memory - 07.5_2
- Li, Min
- [29] [30] Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5
- Li, Qingan
- [361] [362] A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6
- Li, Tai-Hung
- [353] [354] Design-for-Debug Routing for FIB Probing - 11.4_4
- Li, Xiaowei
- [559] [560] Partial-SET: Write Speedup of PCM Main Memory - 03.5_5
- Li, Xiaowei
- [525] [526] SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing - 06.4_2
- Li, Xiaowei
- [635] [636] Functional Test Generation Guided by Steady-State Probabilities of Abstract Design - 11.4_5
- Li, Yaping
- [437] [438] SAFE: Security-Aware FlexRay Scheduling Engine - 02.3_5
- Li, Yueting
- [149] [150] ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits - 12.5_2
- Li, Zhen
- [639] [640] A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6
- Liang, Yun
- [425] [426] WCET-Centric Dynamic Instruction Cache Locking - 02.6_2
- Lilja, David J.
- [189] [190] IIR Filters Using Stochastic Arithmetic - 04.4_1
- Lim, Sung Kyu
- [625] [626] On GPU Bus Power Reduction with 3D IC Technologies - 07.4_3
- Lin, Chia-Chun
- [365] [366] Rewiring for Threshold Logic Circuit Minimization - 05.6_4
- Lin, Fan
- [369] [370] Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction - 08.7_2
- Lin, Hsin-Chang
- [375] [376] Mask-Cost-Aware ECO Routing - 03.4_8
- Lin, Hsueh-Ju
- [323] [324] Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5
- Lin, Xue
- [315] [316] Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles - 05.4_4
- Lin, Yang
- [515] [516] A Low-Cost Radiation Hardened Flip-flop - 06.7_4
- Lin, Zhiqiang
- [641] [642] Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy - 03.5_3
- Lippmann, Mirko
- [289] [290] Automated System Testing Using Dynamic and Resource Restricted Clients - 11.4_6
- Liu, Bao
- [643] [644] Embedded Reconfigurable Logic for ASIC Design Obfuscation against Supply Chain Attacks - 09.3_1
- Liu, Chian-Wei
- [367] [368] Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5
- Liu, Cong
- [519] [520] A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery - 04.7_5
- Liu, Di
- [335] [336] Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3
- Liu, Jianming
- [413] [414] MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2
- Liu, Jianxiong
- [255] [256] Image Progressive Acquisition for Hardware Systems - 12.3_3
- Liu, Leibo
- [645] [646] Extending Lifetime of Battery-Powered Coarse-Grained Reconfigurable Computing Platforms - 11.7_3
- Liu, Shaoteng
- [577] [578] Parallel Probe Based Dynamic Connection Setup in TDM NoCs - 09.2_2
- Liu, Wen-Hao
- [377] [378] Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost - 12.4_3
- Liu, Xuchen
- [371] [372] CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2
- Liu, Ziyi
- [641] [642] Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy - 03.5_3
- Lo, Paul
- [109] [110] Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2
- Loi, Igor
- [205] [206] A Multi Banked - Multi Ported - non Blocking Shared L2 Cache for MPSoC Platforms 04.5_4
- Lombardi, Fabrizio
- [519] [520] A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery - 04.7_5
- Lombardi, Fabrizio
- [521] [522] A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction - 06.7_6
- Long, Yanchen
- [647] [648] Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models - 09.4_4
- Lora, Michele
- [483] [484] Moving from Co-Simulation to Simulation for Effective Smart Systems Design - 10.4_5
- Lorenz, Ingolf
- [513] [514] Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5
- Lourenço, Nuno
- [285] [286] Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1
- Lu, Tianyue
- [345] [346] Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests - 04.5_1
- Lu, Youyou
- [649] [650] p-OFTL: An Object-based Semantic-aware Parallel Flash Translation Layer - 06.6_4
- Lu, Zhonghai
- [577] [578] Parallel Probe Based Dynamic Connection Setup in TDM NoCs - 09.2_2
- Lu, Zhonghai
- [651] [652] Empowering Study of Delay Bound Tightness with Simulated Annealing - 09.4_3
- Lu, Zhonghai
- [647] [648] Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models - 09.4_4
- Lübbers, Enno
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Lukasiewycz, Martin
- [307] [308] Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3
- Luo, Rong
- [359] [360] Energy Efficient Neural Networks for Big Data Analytics - 12.1_4
- Lv, Tao
- [635] [636] Functional Test Generation Guided by Steady-State Probabilities of Abstract Design - 11.4_5
M
- M, Vijaykumar,
- [653] [654] Statistical Static Timing Analysis Using a Skew-Normal Canonical Delay Model - 09.7_2
- Macii, E.
- [251] [252] A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2
- Macii, Enrico
- [655] [656] Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache - 07.4_2
- Macii, Enrico
- [279] [280] Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits - 09.7_7
- Macii, Enrico
- [657] [658] Thermal Management of Batteries Using a Hybrid Supercapacitor Architecture - 11.6_3
- Macrelli, Enrico
- [531] [532] Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5
- Magarshack, Philippe
- [43] [44] Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2
- Mahmood, Haroon
- [655] [656] Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache - 07.4_2
- Mahmoodi, Hamid
- [117] [118] Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design - 11.7_1
- Mai, Ken
- [229] [230] An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS - 04.3_2
- Maistri, Paolo
- [219] [220] A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4
- Mak, Terrence
- [61] [62] Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4
- Mak, Terrence
- [401] [402] Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model - 11.6_5
- Makris, Yiorgos
- [659] [660] An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions - 12.7_1
- Maliuk, Dzmitry
- [659] [660] An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions - 12.7_1
- Maniatakos, Michail
- [661] [662] HEROIC: Homomorphically EncRypted One Instruction Computer - 09.3_4
- Marculescu, Radu
- [85] [86] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3
- Mariani, Giovanni
- [663] [664] DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling - 08.5_6
- Marinissen, Erik Jan
- [517] [518] Interconnect Test for 3D Stacked Memory-on-Logic - 05.7_2
- Marongiu, Andrea
- [203] [204] A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7
- Marongiu, Andrea
- [209] [210] Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3
- Martins, Ricardo
- [285] [286] Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1
- Masadeh, Mahmoud
- [517] [518] Interconnect Test for 3D Stacked Memory-on-Logic - 05.7_2
- Masrur, Alejandro
- [665] [666] The Schedulability Region of Two-Level Mixed-Criticality Systems Based on EDF-VD - 09.6_4
- Mathew, Jimson
- [639] [640] A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6
- Mathew, Jimson
- [667] [668] Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication - 07.5_6
- Matsunaga, Kensaku
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- Matsunaga, Yusuke
- [669] [670] Synthesis Algorithm of Parallel Index Generation Units - 10.7_4
- Matsutani, Hiroki
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- Maurer, Peter M.
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- Maurine, Philippe
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- Mavropoulos, Michail
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- Mazzeo, Antonino
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- Meeus, Wim
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- Meguerdichian, Saro
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- Meijer, Maurice
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- Membarth, Richard
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- Mena Morales, Valentin
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- Mensch, P.
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- Mera, Maria Isabel
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- Mercati, Pietro
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- Meyer, Brett H.
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- Meyer zu Bexten, V.
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- Michel, Bruno
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- Michel, Hans Ulrich
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- Micheloni, Rino
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- Miele, A.
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- Mikolajick, Thomas
- [503] [504] Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3
- Milder, Peter
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- Miller, Felix
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Minematsu, Kazuhiko
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- Mineo, Andrea,
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- Miremadi, Seyed Ghassem
- [467] [468] PSP-Cache: A Low-Cost Fault-Tolerant Cache Memory Architecture - 06.7_5
- Mitra, Tulika
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- Mohanram, Kartik
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- Mokhov, Andrey
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- Molnos, Anca
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- Monteiro, José
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- Moore, Ryan W.
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- Morad, Ronny
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- Morad, Ronny
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- Moreira, Orlando
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- Moreno, Javier
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- Morgenshtein, Arkadiy
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- Moselund, K.
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- Mottaghi, Mohammad D.
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- Muhr, Hannes
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- Mukherjee, Saoni
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- Mukhopadhyay, Saibal
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- Müller, Dirk
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- Munir, Arslan
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- Murali Krishna, G.
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- Murmann, Boris
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- Nahas, Joseph
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- Nahir, Amir
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- Nakamura, Hiroshi
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- Naqvi, Syed Rameez
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- Narayan, Sanjiv
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- Narayanan, Vijaykrishnan
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- Narayanan, Vijaykrishnan
- [297] [298] Video Analytics Using Beyond CMOS Devices - 12.1_3
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- Natarajan, Vishwanath
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- Nath, Siddhartha
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- Nedospasov, Dmitry
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- Nejat, Mehrzad
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- Nicolescu, Gabriela
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- Nicopoulos, C.
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- Osewold, Christof
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P
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- Paler, Alexandru
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- Palermo, Gianluca
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- Palermo, Gianluca
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- Palesi, Maurizio
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- Palesi, Maurizio
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- Palit, Indranil
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- Panda, Preeti Ranjan
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- Panda, Preeti Ranjan
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- Pande, Partha Pratim
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- Pandey, Sujan
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- Papadimitriou, Athanasios
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- Parameswaran, Sri
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- Parameswaran, Sri
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- Parikh, Ritesh
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- Park, Eunhyek
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- Park, Junhyuck
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- Park, Kitae
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- Park, Taejoon
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- Paterna, Francesco
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- Paterna, Francesco
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- Pattabiraman, K.
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- Paul, Steffen
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- Pedram, Massoud
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- Pedram, Massoud
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- Pedram, Massoud
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- Pedram, Massoud
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- Pedram, Massoud
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- Pedram, Massoud
- [351] [352] Concurrent Placement, Capacity Provisioning, and Request Flow Control for a Distributed Cloud Infrastructure - 10.3_4
- Pedram, Massoud
- [627] [628] VRCon: Dynamic Reconfiguration of Voltage Regulators in a Multicore Platform - 12.6_2
- Pedram, Massoud
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- Pellizzoni, Rodolfo
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- Pellizzoni, Rodolfo
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- Peltier, Nicolas
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- Pelz, Georg
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- Pelz, Georg
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- Peng, Zebo
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- Peng, Zebo
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- Peng, Zhen-Yu
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- Perricone, Robert
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- Perricone, Robert
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- Peters-Drolshagen, Dagmar
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- Petricca, M.
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- Pétrot, Frédéric
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- Pigorsch, Florian
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- Pineda de Gyvez, José
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- Pineda de Gyvez, Jose
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- Polian, Ilia
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- Pomeranz, Irith
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- Pomeranz, Irith
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- Poncino, M.
- [251] [252] A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2
- Poncino, Massimo
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- Poncino, Massimo
- [279] [280] Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits - 09.7_7
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- Pongratz, Werner
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- Pontarelli, Salvatore
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- Poon, Chung Keung
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- Postula, Adam
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- Potkonjak, Miodrag
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- Potkonjak, Miodrag
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- Potter, John
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- Poulhiès, Marc
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- Pradhan, Dhiraj K.
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- Pradhan, Dhiraj K
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- Prakash, Varun
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- Prejbeanu, I.L.
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- Prinetto, Paolo
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- Pu, Yu
- [453] [454] Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling - 11.3_2
- Puri, Ruchir
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Q
- Qi, Ji
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- Qiu, Qinru
- [349] [350] Battery Aware Stochastic QoS Boosting in Mobile Computing Devices - 07.3_5
- Qiu, Qinru
- [701] [702] Contention Aware Frequency Scaling on CMPs with Guaranteed Quality of Service - 10.3_3
- Quer, S.
- [277] [278] Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization - 05.5_4
- Querlioz, Damien
- [329] [330] Spintronics for Low-Power Computing - 11.1_1
- Quiñones, Eduardo
- [3] [4] Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2
R
- Radhakrishnan, Rachana
- [591] [592] Minimally Buffered Single-Cycle Deflection Router - 11.2_5
- Radojicic, Carna
- [501] [502] Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities - 02.4_7
- Raghavan, Praveen
- [295] [296] Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3
- Raghavan, Praveen
- [25] [26] Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2
- Raghavan, Praveen
- [133] [134] Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3
- Raghunathan, Anand
- [703] [704] ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1
- Raha, Arnab
- [703] [704] ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1
- Rahimi, Abbas
- [207] [208] Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs - 05.3_1
- Rahman, Md. Tauhidur
- [461] [462] ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design - 04.3_1
- Rajgopal, Srihari
- [231] [232] Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3
- Rallapalli, Arjun
- [449] [450] RETLab: A Fast Design-automation Framework for Arbitrary RET Networks - 05.6_1
- Ramachandran, Jaideep
- [629] [630] Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic - 05.5_5
- Rambo, Eberle A
- [41] [42] Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5
- Ramini, Luca
- [181] [182] Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3
- Ramos, Luiz
- [113] [114] Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5
- Rana, Manish
- [281] [282] SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis - 02.7_3
- Ranganathan, Vaishnavi
- [231] [232] Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3
- Ranjan, Ashish
- [703] [704] ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1
- Rasmussen, Kasper B.
- [477] [478] A Minimalist Approach to Remote Attestation - 09.3_2
- Ravelosona, Dafiné
- [329] [330] Spintronics for Low-Power Computing - 11.1_1
- Ray, Sandip
- [529] [530] Equivalence Checking for Function Pipelining in Behavioral Synthesis - 06.5_3
- Raychowdhury, Arijit
- [237] [238] Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3
- Rebernak, William
- [433] [434] A Flexible BIST Strategy for SDR Transmitters - 12.7_3
- Rech, P.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
- Reda, Sherief
- [149] [150] ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits - 12.5_2
- Rehman, Semeen
- [535] [536] Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7
- Reiche, Oliver
- [527] [528] Code Generation for Embedded Heterogeneous Architectures on Android - 04.6_3
- Reid Alastair,
- [71] [72] Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6
- Reimann, Felix
- [1] [2] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1
- Reimer, Sven
- [197] [198] Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1
- Reineke, Jan
- [705] [706] Impact of Resource Sharing on Performance and Performance Prediction - 05.1_1
- Reisinger, Jochen
- [261] [262] System Integration - The Bridge between More than Moore and More Moore - 05.8
- Renovell, M.
- [137] [138] New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7
- Richter, A.
- [539] [540] Integrated Circuits Processing Chemical Information: Prospects and Challenges - 12.1_1
- Richter, Andre
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Richter, Harald
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Richter, Jan H.
- [55] [56] Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems - 11.3_5
- Riedel, Marc D.
- [189] [190] IIR Filters Using Stochastic Arithmetic - 04.4_1
- Riefert, Andreas
- [195] [196] An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3
- Riel, H.
- [253] [254] III-V Semiconductor Nanowires for Future Devices - 09.1_1
- Ries, Benjamin
- [123] [124] Optimized Buffer Allocation in Multicore Platforms - 11.5_2
- Robino, Francesco
- [685] [686] From Simulink to NoC-based MPSoC on FPGA - 11.5_6
- Roca, E.
- [293] [294] Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits - 02.4_3
- Rödel, Reinhold
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Rodríguez, M. Andrea
- [101] [102] Signature Indexing of Design Layouts for Hotspot Detection - 12.4_2
- Rodríguez Gómez, Laura
- [1] [2] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1
- Roelofs, Gijs
- [395] [396] Testing PUF-Based Secure Key Storage Circuits - 07.7_2
- Romani, Aldo
- [531] [532] Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5
- Rosenstiel, Wolfgang
- [259] [260] Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3
- Rosing, Tajana
- [49] [50] Providing Regulation Services and Managing Data Center Peak Power Budgets - 06.3_6
- Rosing, Tajana Simunic
- [691] [692] Ambient Variation-tolerant and Inter Components Aware Thermal Management for Mobile System on Chips - 08.4_4
- Rossi, Maurizio
- [263] [264] Real-time Optimization of the Battery Banks Lifetime in Hybrid Residential Electrical Systems - 06.3_2
- Rossi, Davide
- [175] [176] Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2
- Rostami, Masoud
- [613] [614] Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder Based Security - 12.2_7
- Rosvall, Kathrin
- [707] [708] A Constraint-Based Design Space Exploration Framework for Real-Time Applications on MPSoCs - 11.5_4
- Roy, Amitabha
- [589] [590] ALLARM: Optimizing Sparse Directories for Thread-Local Data - 04.5_2
- Roy, Kaushik
- [465] [466] Brain-Inspired Computing with Spin Torque Devices - 08.8_2
- Roy, Kaushik
- [703] [704] ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1
- Roy, Saibal
- [531] [532] Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5
- Roy, Sanghamitra
- [305] [306] DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors - 03.7_3
- Rozeau, Olivier
- [185] [186] 3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4
- Rubio, Antonio
- [67] [68] INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4
- Ruch, Patrick
- [129] [130] Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2
- Rührmair, Ulrich
- [269] [270] Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks - 12.2_1
- Rührmair, Ulrich
- [551] [552] PUFs at a Glance - 12.2_2
- Rührmair, Ulrich
- [709] [710] PUF Modeling Attacks: An Introduction and Overview - 12.2_3
- Rührmair, Ulrich
- [711] [712] Protocol Attacks on Advanced PUF Protocols and Countermeasures - 12.2_6
- Russ, Thomas
- [1] [2] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1
- Ryu, Soojung
- [381] [382] Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1
S
- Sabry, Mohamed M.
- [129] [130] Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2
- Sabry, Mohamed M.
- [131] [132] A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4
- Sabry, Mohamed M.
- [133] [134] Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3
- Sabry, Mohamed M.
- [135] [136] Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1
- Sadasue, Tamon
- [125] [126] A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2
- Sadri, Mohammadsadegh
- [213] [214] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh - 10.3_6
- Sakamoto, Ryuichi
- [83] [84] Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1
- Salunkhe, Hrishikesh
- [677] [678] Mode-Controlled Dataflow Based Modeling & Analysis of a 4G-LTE Receiver - 08.4_6
- Sampaio, Felipe
- [161] [162] dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2
- Sampson, Jack
- [311] [312] Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2
- Sander, Ingo
- [707] [708] A Constraint-Based Design Space Exploration Framework for Real-Time Applications on MPSoCs - 11.5_4
- Sander, Oliver
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Sandionigi, Chiara
- [93] [94] Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4
- Sandmann, Timo
- [13] [14] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4
- Sangai, Amit
- [333] [334] Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3
- Sangiovanni-Vincentelli, Alberto L.
- [471] [472] Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems 03.6_6
- Sangiovanni-Vincentelli, Alberto
- [569] [570] Library-Based Scalable Refinement Checking for Contract-Based Design - 06.6_1
- Sankaranarayanan, Aviinaash
- [131] [132] A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4
- Sapatnekar, Sachin S.
- [409] [410] Improving STT-MRAM Density through Multibit Error Correction - 07.5_3
- Saraf, Naman
- [189] [190] IIR Filters Using Stochastic Arithmetic - 04.4_1
- Sarma, Santanu
- [447] [448] Minimal Sparse Observability of Complex Networks: Application to MPSoC Sensor Placement and Run-time Thermal Estimation & Tracking - 11.6_1
- Sassolas, Tanguy
- [93] [94] Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4
- Sassone, A.
- [251] [252] A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2
- Sauer, Matthias
- [193] [194] Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1
- Sauer, Matthias
- [195] [196] An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3
- Sauer, Matthias
- [197] [198] Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1
- Saxena, Sharad
- [111] [112] Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1
- Schacht, Andreas
- [541] [542] Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems - 04.2_3
- Schaumont, Patrick
- [139] [140] Analyzing and Eliminating the Causes of Fault Sensitivity Analysis - 08.3_2
- Scheibler, Karsten
- [193] [194] Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1
- Schiffelers, R.R.H.
- [17] [18] Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2
- Schilders, Wil. H.A.
- [75] [76] Implicit Index-aware Model Order Reduction for RLC/RC Networks 03.4_3
- Schirner, Gunar
- [713] [714] Automatic Specification Granularity Tuning for Design Space Exploration - 08.5_2
- Schirrmeister, Frank
- [373] [374] Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8
- Schlichtmann, Ulf
- [513] [514] Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5
- Schlichtmann, Ulf
- [9] [10] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5
- Schlichtmann, Ulf
- [269] [270] Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks - 12.2_1
- Schmaltz, Julien
- [593] [594] Scalable Liveness Verification for Communication Fabrics - 05.5_1
- Schmid, H.
- [253] [254] III-V Semiconductor Nanowires for Future Devices - 09.1_1
- Schmidt, V.
- [253] [254] III-V Semiconductor Nanowires for Future Devices - 09.1_1
- Schneider, Klaus
- [153] [154] Isochronous Networks by Construction - 06.6_2
- Schneider, Josef
- [579] [580] Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs - 10.4_2
- Scholl, Stefan
- [715] [716] Hardware Implementation of a Reed-Solomon Soft Decoder Based on Information Set Decoding - 08.4_3
- Scholl, Christoph
- [79] [80] Simple Interpolants for Linear Arithmetic - 05.5_3
- Schubert, Tobias
- [197] [198] Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1
- Schüffny, R.
- [539] [540] Integrated Circuits Processing Chemical Information: Prospects and Challenges - 12.1_1
- Schulte, Michael
- [33] [34] Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4
- Schumacher, Christoph
- [119] [120] Time-Decoupled Parallel SystemC Simulation - 07.6_6
- Schwarzer, Tobias
- [463] [464] Model-Based Actor Multiplexing with Application to Complex Communication Protocols 08.5_4
- Sedighi, Behnam
- [311] [312] Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2
- Sedighi, Behnam
- [553] [554] Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3
- Seidl, Martina
- [609] [610] Partial Witnesses from Preprocessed Quantified Boolean Formulas - 06.5_2
- Seifert, Jean-Pierre
- [245] [246] Physical Vulnerabilities of Physically Unclonable Functions - 12.2_5
- Seitanidis, I.
- [423] [424] ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers - 09.2_3
- Seitanidis, I.
- [393] [394] Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8
- Sen, Shreyas
- [581] [582] Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2
- Seo, Woong
- [381] [382] Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1
- Seyler, Jan R.
- [493] [494] A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3
- Seyyedi, Razi
- [65] [66] Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1
- Shafik, Rishad A.
- [639] [640] A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6
- Shafique, Muhammad
- [161] [162] dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2
- Shafique, Muhammad
- [535] [536] Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7
- Shafique, Muhammad
- [537] [538] Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing - 08.6_1
- Shafique, Muhammad
- [97] [98] hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6
- Shafique, Muhammad
- [99] [100] mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2
- Shahrour, Anas
- [459] [460] Unified, Ultra Compact, Quadratic Power Proxies for Multi-Core Processors - 11.6_6
- Shan, ShuChang
- [559] [560] Partial-SET: Write Speedup of PCM Main Memory - 03.5_5
- Shang, Delong
- [717] [718] Asynchronous Design for New On-Chip Wide Dynamic Range Power Electronics - 06.3_1
- Shankar, Arunprasath
- [385] [386] Cross-correlation of Specification and RTL for Soft IP Analysis - 10.5_4
- Sharad, Mrigank
- [465] [466] Brain-Inspired Computing with Spin Torque Devices - 08.8_2
- Sharma, Namita
- [59] [60] Energy Optimization in Android Applications through Wakelock Placement - 04.6_5
- Sharma, Namita
- [29] [30] Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5
- Shen, Hao
- [349] [350] Battery Aware Stochastic QoS Boosting in Mobile Computing Devices - 07.3_5
- Shen, Hao
- [701] [702] Contention Aware Frequency Scaling on CMPs with Guaranteed Quality of Service - 10.3_3
- Shi, Yiyu
- [325] [326] Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6
- Shi, Yiyu
- [339] [340] Memcomputing: The Cape of Good Hope - 09.8_1
- Shi, Yiyu
- [413] [414] MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2
- Shi, Weidong
- [641] [642] Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy - 03.5_3
- Shi, Weidong
- [167] [168] Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3
- Shin, Donghwa
- [657] [658] Thermal Management of Batteries Using a Hybrid Supercapacitor Architecture - 11.6_3
- Shin, Donghwa
- [319] [320] FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4
- Shrotri, Ulka
- [31] [32] EDT: A Specification Notation for Reactive Systems - 08.5_3
- Shu, Jiwu
- [649] [650] p-OFTL: An Object-based Semantic-aware Parallel Flash Translation Layer - 06.6_4
- Siddique, Umair
- [719] [720] Towards the Formal Analysis of Microresonators Based Photonic Systems - 06.5_4
- Sigl, Georg
- [547] [548] Increasing the Efficiency of Syndrome Coding for PUFs with Helper Data Compression - 04.3_3
- Signorello, G.
- [253] [254] III-V Semiconductor Nanowires for Future Devices - 09.1_1
- Silvano, Cristina
- [687] [688] Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon - 08.2_2
- Silvano, Cristina
- [663] [664] DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling - 08.5_6
- Silveira, L. Miguel
- [469] [470] Efficient Analysis of Variability Impact on Interconnect Lines and Resistor Networks - 03.4_2
- Simunic Rosing, Tajana
- [173] [174] A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5
- Sinanoglu, Ozgur
- [313] [314] Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation - 02.7_6
- Singh, Bhanu
- [385] [386] Cross-correlation of Specification and RTL for Soft IP Analysis - 10.5_4
- Själander, Magnus
- [169] [170] Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD3) - 04.5_6
- Slamani, Mustapha
- [581] [582] Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2
- Smailbegovic, Fethulah
- [403] [404] Hacking and Protecting IC Hardware - 05.2
- Smith, Aaron
- [265] [266] EVX: Vector Execution on Low Power EDGE Cores - 02.5_4
- Sohn, M.-P.
- [171] [172] Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4
- Sohrmann, Christoph
- [513] [514] Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5
- Sokhin, Vitali
- [479] [480] Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3
- Sokolov, Danil
- [63] [64] Design of Safety Critical Systems by Refinement - 04.6_4
- Son, Sang H.
- [567] [568] A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4
- Song, Seokwoo
- [381] [382] Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1
- Song, Yang
- [693] [694] Zonotope-based Nonlinear Model Order Reduction for Fast Performance Bound Analysis of Analog Circuits with Multiple-interval-valued Parameter Variations - 02.4_2
- Sonza Reorda, M.
- [187] [188] GPGPUs: How to Combine High Computational Power with High Reliability - 11.8
- Sonza Reorda, Matteo
- [195] [196] An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3
- Sorin, Daniel J.
- [681] [682] Nostradamus: Low-Cost Hardware-Only Error Detection for Processor Cores - 06.7_1
- Sölter, Jan
- [709] [710] PUF Modeling Attacks: An Introduction and Overview - 12.2_3
- Soudbakhsh, Damoon
- [103] [104] Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3
- Sousa, R.
- [421] [422] Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3
- Spägele, Matthias
- [493] [494] A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3
- Spasic, Jelena
- [335] [336] Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3
- Sridhar, Arvind
- [129] [130] Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2
- Stamelakos, Ioannis
- [687] [688] Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon - 08.2_2
- Stefanni, Francesco
- [483] [484] Moving from Co-Simulation to Simulation for Effective Smart Systems Design - 10.4_5
- Stefanov, Todor
- [335] [336] Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3
- Stefanov, Todor
- [159] [160] System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach - 12.5_4
- Steinhorst, Sebastian
- [307] [308] Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3
- Steininger, Andreas
- [679] [680] A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments - 10.7_2
- Stenström, Per
- [721] [722] Effective Resource Management towards Efficient Computinga - 06.1_3
- Stoimenov, Nikolay
- [489] [490] Mapping Mixed-Criticality Applications on Multi-Core Architectures - 05.1_3
- Streichert, Thilo
- [493] [494] A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3
- Stroobandt, Dirk
- [151] [152] Improving Hamiltonian-based Routing Methods for On-chip Networks: A Turn Model Approach - 09.2_5
- Stroobandt, Dirk
- [673] [674] Automating Data Reuse in High-Level Synthesis - 10.7_5
- Stuijk, S.
- [17] [18] Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2
- Stuijk, Sander
- [183] [184] Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming - 11.5_3
- Stuijt, Jan
- [133] [134] Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3
- Su, Yongtao
- [723] [724] System-level Design Methodology Enabling Fast Development of Baseband MP-SoC for 4G Small Cell Base Station - 08.1_2
- Suárez, Darío
- [575] [576] Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs - 09.2_4
- Subramanyan, Pramod
- [115] [116] Formal Verification of Taint-propagation Security Properties in a Commercial SoC Design - 11.3_3
- Sudowe, Patrick
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- Sullivan, Dean
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- Sun, Haiyan
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- Sun, Luo
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- Susin, Altamiro
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- Swaminathan, Karthik
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- Syed, Rizwan
- [511] [512] Thermal-Aware Frequency Scaling for Adaptive Workloads on Heterogeneous MPSoCs - 10.6_1
- Sylvester, Dennis
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T
- Tagliavini, Giuseppe
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- Tahar, Sofiène
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- Tahoori, Mehdi B.
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- Tahoori, Mehdi B.
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- Tahoori, Mehdi B.
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- Tahoori, Mehdi B.
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- Takimiya, Kazuo
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- Tartagni, Marco
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- Taylor, Michael B.
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- Tecchiolli, Giampietro
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- Teich, Jürgen
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- Teich, Jürgen
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- Teich, Jürgen
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- Teich, Jürgen
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- Teich, Jürgen
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- Thanner, Manfred
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- Theocharides, Theocharis
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- Thiele, Lothar
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- Thomas, Olivier
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- Tosoratto, Laura
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- Trachanis, Dimitrios
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- Wang, Ningning
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- Wang, Ting-Hsiung
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- Wang, Xuan
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- Wang, Yanzhi
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- Wang, Yanzhi
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- Wang, Yanzhi
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- Wang, Yanzhi
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- Wang, Yanzhi
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- Wang, Yanzhi
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- Wang, Yu
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- Wang, Yu
- [359] [360] Energy Efficient Neural Networks for Big Data Analytics - 12.1_4
- Wang, Yuhao
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- Wang, Zhe
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- Wang, Zhehui
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- Wang, Zhenjiang
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- Weber, Walter M.
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- Wehn, Norbert
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- Wehn, Norbert
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- Wehn, Norbert
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- Wehn, Norbert
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- Wei, Shaojun
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- Weinstock, Jan Henrik
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- Weis, Christian
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- Weis, Christian
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- Wendt, James B.
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- Weyer, Daniel
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- Whalley, David
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- Wildermann, Stefan
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- Wilhelm, Reinhard
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- Wilson, Peter
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- Wolff, Francis
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- Wong, Martin D. F.
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- Wong, Philip
- [297] [298] Video Analytics Using Beyond CMOS Devices - 12.1_3
- Wu, Chenggang
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- Wu, Chi-Feng
- [375] [376] Mask-Cost-Aware ECO Routing - 03.4_8
- Wu, Hui
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- Wu, Sih-Sian
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- Wu, Xiaowen
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- Wu, Yun-Ru
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- Wunderlich, Hans-Joachim
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- Wunderlich, Hans-Joachim
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- Wuttig, Matthias
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X
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- Xie, Fei
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- Xie, Fei
- [389] [390] Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes - 11.4_2
- Xie, Qing
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- Xie, Qing
- [319] [320] FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4
- Xiong, Jinjun
- [413] [414] MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2
- Xiong, Wei
- [267] [268] Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3
- Xu, Chao
- [361] [362] A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6
- Xu, Jiang
- [343] [344] Characterizing Power Delivery Systems with On/Off-Chip Voltage Regulators for Many-Core Processors - 03.4_7
- Xu, Ningyi
- [359] [360] Energy Efficient Neural Networks for Big Data Analytics - 12.1_4
- Xu, Shouhuai
- [641] [642] Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy - 03.5_3
- Xu, Xiaolin
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- Xue, Chun Jason
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- Xue, Jingling
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- Xydis, Sotirios
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Y
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- Yakovlev, Alex
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- Yamashita, Noritaka
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- Yamashita, Shigeru
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- Yan, Guihai
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- Yan, Xiaolang
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- Yang, Hoeseok
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- Yang, Hoeseok
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- Yang, Huazhong
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- Yang, Huazhong
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- Yang, Mei
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- Yang, Qiang
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- Yang, Rui
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- Yang, Seiyang
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- Yang, Yuanfan
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- Yang, Zhenkun
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- Ye, Zuochang
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- Yeh, Hua-Hsin
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- Yi, Wang
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- Yin, Shouyi
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- Yogendra, Karthik
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- Yu, Hao
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- Yu, Hao
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- Yu, Hao
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- Yu, Heng
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- Yu, Li
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- Yu, Mingbin
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- Yu, Xinmin
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- Yue, Siyu
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Z
- Zaccaria, Vittorio
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- Zafari, Leily
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- Zaki, Tarek
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- Zambelli, Cristian
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- Zangeneh, Mahmoud
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- Zanotelli, Joe
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- Zatt, Bruno
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- Zebelein, Christian
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- Zeng, Haibo
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- Zeng, Haibo
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- Zeng, Xuan
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- Zhai, Jiali Teddy
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- Zhang, Chun
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- Zhang, Chunyuan
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- Zhang, Guowei
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- Zhang, Jian
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- Zhang, Jiaxing
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- Zhang, Moning
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- Zhang, Shuangyue
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- Zhang, Tiansheng
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- Zhang, Xuefu
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- Zhang, Xuemeng
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- Zhang, Youguang
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- Zhang, Yue
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- Zhao, Baoxin
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- Zhao, Weisheng
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- Zhao, Xueqian
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- Zhou, Hai
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- Zhu, Chun Jiang
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- Zhu, Di
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- Zhu, Di
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- Zhu, Qi
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- Zhu, Xue-Yang
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- Zhu, Ziyuan
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- Zschieschang, Ute
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- Zuolo, Lorenzo
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- Zussa, Loic
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- Zwolinski, Mark
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- Zwolinski, Mark
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- Zygmontowicz, Adam
- [397] [398] Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network - 07.7_3