Sessions: [Keynotes] [2.2] [2.3] [2.4] [2.5] [2.6] [2.7] [2.8] [3.2] [3.3] [3.4] [3.5] [3.6] [3.7] [3.8] [4.2] [4.3] [4.4] [4.5] [4.6] [4.7] [5.1] [5.2] [5.3] [5.4] [5.5] [5.6] [5.7] [5.8] [6.1] [6.2] [6.3] [6.4] [6.5] [6.6] [6.7] [7.0] [7.2] [7.3] [7.4] [7.5] [7.6] [7.7] [8.1] [8.2] [8.3] [8.4] [8.5] [8.6] [8.7] [8.8] [9.1] [9.2] [9.3] [9.4] [9.5] [9.6] [9.7] [9.8] [10.1] [10.2] [10.3] [10.4] [10.5] [10.6] [10.7] [11.0] [11.1] [11.2] [11.3] [11.4] [11.5] [11.6] [11.7] [11.8] [12.1] [12.2] [12.3] [12.4] [12.5] [12.6] [12.7] [12.8]

DATE 14 Sponsors
DATE Executive Committee
DATE Sponsors Committee
Technical Program Topic Chairs
Technical Program Committee
Reviewers
Foreword
Best Paper Awards
ACM SIGDA/EDAA PH.D. Forum
Call for Papers: DATE 2015

1.1.1 Keynote: System Design Challenges for Next Generation Wireless and Embedded Systems

David Fuller - National Instruments, US

1.1.2 Keynote: The Growing Importance of Microelectronics from a Foundry Perspective

Gerd Teepe - GLOBALFOUNDRIES, DE

2.2 Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads?

Organizer: Marco Casale-Rossi, Synopsys, Inc., US
Chair: Giovanni De Micheli, EPFL, CH

Panelists: Rob Aitken, Antun Domic, Manfred Horstmann, Robert Hum, Philippe Magarshack

2.3 Making Automotive Systems Safer and More Energy Efficient

Chairs: Bart Vermeulen, NXP Semiconductors, NL; Martin Lukasiewycz, TUM CREATE, SG

Emulation-Based Robustness Assessment for Automotive Smart-Power ICs

Manuel Harrant, Thomas Nirmaier, Jérôme Kirscher, Christoph Grimm, Georg Pelz

Startup Error Detection and Containment to Improve the Robustness of Hybrid FlexRay Networks

Alexander Kordes, Bart Vermeulen, Abhijit Deb, Michael G. Wahl

A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support

Jan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spägele, Michael Glaβ, Jürgen Teich

Multi-Variant-based Design Space Exploration for Automotive Embedded Systems

Sebastian Graf, Michael Glaβ, Jürgen Teich, Christoph Lauer

SAFE: Security-Aware FlexRay Scheduling Engine

Gang Han, Haibo Zeng, Yaping Li, Wenhua Dou

Transient Errors Resiliency Analysis Technique for Automotive Safety Critical Applications

Sujan Pandey and Bart Vermeulen

2.4 Modern Challenges in Analog and Mixed-Signal Design

Chairs: Georges Gielen, KU Leuven, BE; Günhan Dündar, Bogazici University, TR

Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures

Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta

Zonotope-based Nonlinear Model Order Reduction for Fast Performance Bound Analysis of Analog Circuits with Multiple-interval-valued Parameter Variations

Yang Song, Sai Manoj P.D., Hao Yu

Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits

M. Velasco-Jiménez, R. Castro-López, E. Roca, F.V. Fernández

Modeling of an Analog Recording System Design for ECoG and AP Signals

Nils Heidmann, Nico Hellwege, Tim Höhlein, Thomas Westphal, Dagmar Peters-Drolshagen, Steffen Paul

Model Based Hierarchical Optimization Strategies for Analog Design Automation

Engin Afacan, Simge Ay, F.V. Fernández, Günhan Dündar, Faik Baskaya

A Novel Low Power 11-bit Hybrid ADC Using Flash and Delay Line Architectures

Hsun-Cheng Lee and Jacob A. Abraham

Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities

Carna Radojicic, Christoph Grimm, Javier Moreno, Xiao Pan

Novel Circuit Topology Synthesis Method Using Circuit Feature Mining and Symbolic Comparison

Cristian Ferent and Alex Doboli

An Embedded Offset and Gain Instrument for OpAmp IPs

Jinbo Wan and Hans G. Kerkhoff

2.5 Low-Power and Efficient Architectures

Chairs: Cristina Silvano, Politecnico di Milano, IT; Todd Austin, University of Michigan, US

Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads

Seokwoo Song, Minseok Lee, John Kim, Woong Seo, Yeongon Cho, Soojung Ryu

dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding

Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel

Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements

Manu Komalan, José Ignacio Gómez Pérez, Christian Tenllado, Praveen Raghavan, Matthias Hartmann, Francky Catthoor

EVX: Vector Execution on Low Power EDGE Cores

Milovan Duric, Oscar Palomar, Aaron Smith, Osman Unsal, Adrian Cristal, Mateo Valero, Doug Burger

Program Affinity Performance Models for Performance and Utilization

Ryan W. Moore and Bruce R. Childers

Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures

Matthias Boettcher, Bashir M. Al-Hashimi, Mbou Eyole, Giacomo Gabrielli, Alastair Reid

A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters

Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini

2.6 Real-Time Memory Hierarchies

Chairs: Benny Akesson, CTU Prague, CZ; Giuseppe Lipari, ENS - Cachan, FR

On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis

Sebastian Altmeyer, Robert I. Davis

WCET-Centric Dynamic Instruction Cache Locking

Huping Ding, Yun Liang, Tulika Mitra

Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms

Chuansheng Dong, Haibo Zeng

Time-predictable Execution of Multithreaded Applications on Multicore Systems

Ahmed Alhammad, Rodolfo Pellizzoni

2.7 Yield and Reliability for Robust Systems

Chairs: Joan Figueras, UPC, ES; Jose Pineda de Gyvez, NXP, NL

Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales

Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu

Bias Temperature Instability Analysis of FinFET Based SRAM Cells

Seyab Khan, Innocent Agbo, Said Hamdioui, Halil Kukner, Ben Kaczer, Praveen Raghavan, Francky Catthoor

SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis

Manish Rana, Ramon Canal

INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis

Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio

Wear-out Analysis of Error Correction Techniques in Phase-change Memory

Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araújo

Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation

Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri

2.8 Hot Topic: Technology Transfer towards Horizon 2020

Organizer: Rainer Leupers, RWTH Aachen, Germany
Chair: Norbert Wehn, TU Kaiserslautern, Germany

Technology Transfer towards Horizon 2020

Rainer Leupers

3.2 Panel: The World Is Going... Analog & Mixed-Signal! What about EDA?

Organizer: Marco Casale-Rossi, Synopsys, Inc., US.
Chair: Pietro Palella, STMicroelectronics, IT

Panelists: Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo

3.3 Secure Hardware Primitives and Implementations

Chairs: Paolo Maistri, TIMA, FR; Patrick Schaumont, Virginia Tech, US

Lightweight Code-based Cryptography: QC-MDPC McEliece Encryption on Reconfigurable Devices

Ingo von Maurich, Tim Güneysu

On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models

Patrick Haddad, Yannick Teglia, Florent Bernard, Viktor Fischer

Clock-Modulation Based Watermark for Protection of Embedded Processors

Jedrzej Kufel, Peter Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough, James Myers

3.4 Modeling and Optimization of Power Distribution Networks

Chairs: Luca Daniel, MIT, US; Stefano Grivet-Talocia, Politecnico di Torino, IT

Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications

A. Ubolli, S. Grivet-Talocia, M. Bandinu, A. Chinea

Efficient Analysis of Variability Impact on Interconnect Lines and Resistor Networks

Jorge Fernández Villena, L. Miguel Silveira

Implicit Index-aware Model Order Reduction for RLC/RC Networks

Nicodemus Banagaaya, Giuseppe Alì, Wil. H.A. Schilders, Caren Tischendorf

P/G TSV Planning for IR-drop Reduction in 3D-ICs

Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori

Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images

Jui-Hung Chien, Hao Yu, Ruei-Siang Hsu, Hsueh-Ju Lin, Shih-Chieh Chang

Cost-Effective Decap Selection for Beyond Die Power Integrity

Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen

Characterizing Power Delivery Systems with On/Off-Chip Voltage Regulators for Many-Core Processors

Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang

Mask-Cost-Aware ECO Routing

Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang

3.5 Robust Architectures

Chairs: Todd Austin, University of Michigan, US; Muhammad Shafique, Karlsruhe Institute of Technology, DE

Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems

Manil Dev Gomony, Benny Akesson, Kees Goossens

Bus Designs for Time-Probabilistic Multicore Processors

Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla

Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy

Ziyi Liu, Weidong Shi, Shouhuai Xu, Zhiqiang Lin

Exploiting Narrow-Width Values for Improving Non-Volatile Cache Lifetime

Guangshan Duan, Shuai Wang

Partial-SET: Write Speedup of PCM Main Memory

Bing Li, ShuChang Shan, Yu Hu, Xiaowei Li

3.6 Cyber Physical Systems: Security and Co-design

Chairs: Rolf Ernst, Technische Universitaet Braunschweig, DE; Anuradha Annaswamy, MIT, US

Attack-Resilient Sensor Fusion

Radoslav Ivanov, Miroslav Pajic, Insup Lee

Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees

Amir Aminifar, Enrico Bini, Petru Eles, Zebo Peng

Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems

Matthias Kauer, Damoon Soudbakhsh, Dip Goswami, Samarjit Chakraborty, Anuradha M. Annaswamy

Garbage Collection for Multi-version Index on Flash Memory

Kam-Yiu Lam, Jiantao Wang, Yuan-Hao Chang, Jen-Wei Hsieh, Po-Chun Huang, Chung Keung Poon, Chun Jiang Zhu

D2Cyber: A Design Automation Tool for Dependable Cybercars

Arslan Munir, Farinaz Koushanfar

Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems

Pierluigi Nuzzo, John B. Finn, Antonio Iannopollo, Alberto L. Sangiovanni-Vincentelli

3.7 On line Strategies for Reliability

Chairs: Fabrizio Lombardi, Northwestern University, US; JIe Han, University of Alberta, CA

Spatial Pattern Prediction Based Management of Faulty Data Caches

Georgios Keramidas, Michail Mavropoulos, Anna Karvouniari, Dimitris Nikolos

Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs

A. Das, A. Kumar, B. Veeravalli, C. Bolchini, A. Miele

DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors

Hu Chen, Sanghamitra Roy, Koushik Chakraborty

A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor

Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang

3.8 Hot Topic: Mission Profile Aware Design - The Solution for Successful Design of Tomorrows Automotive Electronics

Organizers: Goeran Jerke, Robert Bosch GmbH, DE; Oliver Bringmann, University of Tuebingen, DE
Chairs: Goeran Jerke, Robert Bosch GmbH, DE; Oliver Bringmann, University of Tuebingen, DE

Mission Profile Aware IC Design - A Case Study

Goeran Jerke, Andrew B. Kahng

Mission Profile Aware Robustness Assessment of Automotive Power Devices

Thomas Nirmaier, Andreas Burger, Manuel Harrant, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel, Georg Pelz

Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design

C. Katzschke, M.-P. Sohn, M. Olbrich, V. Meyer zu Bexten, M. Tristl, E. Barke

4.2 Hot Topic: Multicore Systems in Safety Critical Electronic Control Units for Automotive and Avionics

Organizers and Chairs: Jürgen Becker, KIT, DE; Oliver Sander, KIT, DE

Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems

Jan Nowotsch, Michael Paulitsch, Arne Henrichsen, Werner Pongratz, Andreas Schacht

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems

Oliver Sander, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Falco Bapp, Jürgen Becker, Hans Ulrich Michel, Dirk Kaule, Daniel Adam, Enno Lübbers, Jürgen Hairbucher, Andre Richter, Christian Herber, Andreas Herkersdorf

4.3 Secure Device Identification

Chairs: Tim Gueneysu, RUB, DE; Guido Bertoni, TMicroelectronics, IT

ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design

Md. Tauhidur Rahman, Domenic Forte, Jim Fahrny, Mohammad Tehranipoor

An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS

Mudit Bhargava, Ken Mai

Increasing the Efficiency of Syndrome Coding for PUFs with Helper Data Compression

Matthias Hiller, Georg Sigl

Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation

Jeroen Delvaux, Ingrid Verbauwhede

4.4 "Almost There" Emerging Technologies

Chairs: Ian O'Connor, University of Lyon, FR; Michael Niemier, University of Notre Dame, US

IIR Filters Using Stochastic Arithmetic

Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel

Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias

Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu

A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips

Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho

Fast and Accurate Computation Using Stochastic Circuits

Armin Alaghi, John P. Hayes

4.5 Memory System Architectures

Chairs: Muhammad Shafique, Karlsruhe Institute of Technology, DE; Cristina Silvano, Politecnico di Milano, IT

Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests

Tianyue Lu, Licheng Chen, Mingyu Chen

ALLARM: Optimizing Sparse Directories for Thread-Local Data

Amitabha Roy, Timothy M. Jones

Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control

Biswabandan Panda, Shankar Balachandran

A Multi Banked - Multi Ported - non Blocking Shared L2 Cache for MPSoC Platforms

Igor Loi, Luca Benini

DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy

Zoran Jaksić, Ramon Canal

Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD³)

Alen Bardizbanyan, Magnus Själander, David Whalley, Per Larsson-Edefors

Distributed Cooperative Shared Last-Level Caching in Tiled Multiprocessor System on Chip

Preethi P. Damodaran, Stefan Wallentowitz, Andreas Herkersdorf

4.6 Code Generation and Optimization for Embedded Platforms

Chairs: Heiko Falk, Ulm University, DE; Florence Maraninchi, Grenoble IMP/VERIMAG, FR

EATBit: Effective Automated Test for Binary Translation with High Code Coverage

Hui Guo, Zhenjiang Wang, Chenggang Wu, Ruining He

On-Device Objective-C Application Optimization Framework for High-Performance Mobile Processors

Garo Bournoutian, Alex Orailoglu

Code Generation for Embedded Heterogeneous Architectures on Android

Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich

Design of Safety Critical Systems by Refinement

Alex Iliasov, Arseniy Alekseyev, Danil Sokolov, Andrey Mokhov

Energy Optimization in Android Applications through Wakelock Placement

Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan

A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems

Qingan Li, Yanxiang He, Yong Chen, Chun Jason Xue, Nan Jiang, Chao Xu

Lifetime Holes Aware Register Allocation for Clustered VLIW Processors

Xuemeng Zhang, Hui Wu, Haiyan Sun, Jingling Xue

4.7 Dependable System Design

Chairs: Yiorgos Makris, University of Texas at Dallas, US; Michael Nicolaidis, TIMA, FR

Real-Time Trust Evaluation in Integrated Circuits

Yier Jin, Dean Sullivan

Verification-guided Voter Minimization in Triple-Modular Redundant Circuits

Dmitry Burlyaev, Pascal Fradet, Alain Girault

Trade-offs in Execution Signature Compression for Reliable Processor Systems

Jonah Caplan, Maria Isabel Mera, Peter Milder, Brett H. Meyer

An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems

Yue Gao, Sandeep K. Gupta, Yanzhi Wang, Massoud Pedram

A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery

Cong Liu, Jie Han, Fabrizio Lombardi

5.1 Hot Topic: Predictable Multi-Core Computing

Organizer: Jürgen Teich, Erlangen-Nuremberg U, DE
Chairs: Petru Eles, Linkoping U, SE; Jürgen Teich, Erlangen-Nuremberg U, DE

Impact of Resource Sharing on Performance and Performance Prediction

Jan Reineke, Reinhard Wilhelm

Time-Critical Computing on a Single Chip Massively Parallel Processor

Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager

Mapping Mixed-Criticality Applications on Multi-Core Architectures

Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele

5.2 Hot Topic: Hacking and Protecting Hardware: Threats and Challenges

Organizers: Said Hamdioui, TU Delft, NL; Giorgio Di Natale, LIRMM, FR
Chairs: Said Hamdioui, TU Delft, NL; Giorgio Di Natale, LIRMM, FR

Hacking and Protecting IC Hardware

Said Hamdioui, Giorgio Di Natale, Gerard van Battum, Jean-Luc Danger, Fethulah Smailbegovic, Mark Tehranipoor

5.3 Reliable Systems in the Age of Variability

Chairs: Antonio Miele, Politecnico di Milano, IT; José L. Ayala, Complutense University of Madrid, ES

Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs

Abbas Rahimi, Luca Benini, Rajesh K. Gupta

Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W

Waleed Dweik, Murali Annavaram, Michel Dubois

Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia MPSoCs

Anup Das, Akash Kumar, Bharadwaj Veeravalli

Recovery-Based Resilient Latency-Insensitive Systems

Yuankai Chen, Xuan Zeng, Hai Zhou

A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices

Pietro Mercati, Andrea Bartolini, Francesco Paterna, Tajana Simunic Rosing, Luca Benini

Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits

Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang

Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities

Semeen Rehman, Florian Kriebel, Muhammad Shafique, Jörg Henkel

5.4 Prediction and Optimization of Timing Variations

Chairs: Antonio Rubio, UPC Barcelona, ES; Marisa López Vallejo, UPM Madrid,ES

Efficient High-Sigma Yield Analysis for High Dimensional Problems

Moning Zhang, Zuochang Ye, Yan Wang

Sub-threshold Logic Circuit Design Using Feedback Equalization

Mahmoud Zangeneh, Ajay Joshi

Stochastic Analysis of Bubble Razor

Guowei Zhang, Peter Beerel

Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles

Yanzhi Wang, Xue Lin, Qing Xie, Naehyuck Chang, Massoud Pedram

Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits

Mehrzad Nejat, Bijan Alizadeh, Ali Afzali Kusha

A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance

Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan, Zhen Li

5.5 Boosting the Scalability of Formal Verification Technologies

Chairs: Fahim Rahim, Atrenta, FR; Bernd Becker, University of Freiburg, DE

Scalable Liveness Verification for Communication Fabrics

Sebastiaan J.C. Joosten, Julien Schmaltz

Property Directed Invariant Refinement for Program Verification

Tobias Welp, Andreas Kuehlmann

Simple Interpolants for Linear Arithmetic

Christoph Scholl, Florian Pigorsch, Stefan Disch, Ernst Althaus

Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization

G. Cabodi, P. Pasini, S. Quer, D. Vendraminetto

Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic

Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl

5.6 Emerging Logic Technologies

Chairs: Mehdi Tahoori, KIT, DE; Marco Ottavi, University of Rome "Tor Vergata", IT

RETLab: A Fast Design-automation Framework for Arbitrary RET Networks

Mohammad D. Mottaghi, Arjun Rallapalli, Chris Dwyer

Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study

Robert Perricone, X. Sharon Hu, Joseph Nahas, Michael Niemier

Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling

Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Deming Chen

Rewiring for Threshold Logic Circuit Minimization

Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang

Width Minimization in the Single-Electron Transistor Array Synthesis

Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan

Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints

Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang

Software-based Pauli Tracking in Fault-tolerant Quantum Circuits

Alexandru Paler, Simon Devitt, Kae Nemoto, Ilia Polian

5.7 Test generation and optimization

Chairs: Xiaoqing Wen, Kyushu Institute of Technology, JP; Grzegorz Mrugalski, Mentor Graphics, PL

Efficient SMT-based ATPG for Interconnect Open Defects

Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker

Interconnect Test for 3D Stacked Memory-on-Logic

Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen

An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults

Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker

Multi-Site Test Optimization for Multi-V_dd SoCs Using Space- and Time-Division Multiplexing

Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin Parekhji, Arvind Jain

An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs

Nima Aghaee, Zebo Peng, Petru Eles

Test and Non-Test Cubes for Diagnostic Test Generation Based on Merging of Test Cubes

Irith Pomeranz

New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy

H. Ayari, F. Azais, S. Bernard, M. Comte, V. Kerzerho, M. Renovell

5.8 System Integration - The Bridge between More than Moore and More Moore

Organizers: Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE; Kai Hahn, University Siegen,DE
Chairs: Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE; Kai Hahn, University Siegen, DE

System Integration - The Bridge between More than Moore and More Moore

Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grünewald, Rainer Brück, Steffen Kröhnert, Jochen Reisinger

6.1 Hot Topic: The Fight against Dark Silicon

Organizer: Jörg Henkel, Karlsruhe Institute of Technology, DE
Chairs: Jörg Henkel, Karlsruhe Institute of Technology, DE Jürgen Teich, Erlangen-Nuremberg U, DE

A Landscape of the New Dark Silicon Design Regime

Michael B. Taylor

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs

Mohamed M. Sabry, Arvind Sridhar, David Atienza, Patrick Ruch, Bruno Michel

Effective Resource Management towards Efficient Computing

Per Stenström

6.2 Embedded Tutorial: Emerging Transistor Technologies: From Devices to Architectures

Organizers: Michael Niemier, University of Notre Dame, US; X. Sharon Hu, University of Notre Dame, US
Chair: Michael Niemier, University of Notre Dame, US

Modeling Steep Slope Devices: From Circuits to Architectures

Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, Jack Sampson, Vijaykrishnan Narayanan

Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study

Indranil Palit, Behnam Sedighi, András Hortváth, X. Sharon Hu, Joseph Nahas, Michael Niemier

6.3 Management of Micro/Macro Renewable Energy Storage Systems

Chairs: Geoff Merrett, University of Southampton,UK Davide Brunelli, University of Trento, IT

Asynchronous Design for New On-Chip Wide Dynamic Range Power Electronics

Delong Shang, Xuefu Zhang, Fei Xia, Alex Yakovlev

Real-time Optimization of the Battery Banks Lifetime in Hybrid Residential Electrical Systems

Maurizio Rossi, Alessandro Toppano, Davide Brunelli

Optimal Dimensioning of Active Cell Balancing Architectures

Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz, Matthias Kauer, Samarjit Chakraborty

Optimal Design and Management of a Smart Residential PV and Energy Storage System

Di Zhu, Yanzhi Wang, Naehyuck Chang, Massoud Pedram

Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting

Enrico Macrelli, Ningning Wang, Saibal Roy, Michael Hayes, Rudi Paolo Paganelli, Marco Tartagni, Aldo Romani

Providing Regulation Services and Managing Data Center Peak Power Budgets

Baris Aksanli, Tajana Rosing

The Energy Benefit of Level-crossing Sampling Including the Actuator's Energy Consumption

Burkhard Hensel, Klaus Kabitzsch

6.4 Power Delivery and Distribution

Chairs: Edith Beigné, CEA LETI Grenoble, FR; Domenik Helms, OFFIS Oldenburg, DE

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors

Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura

SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing

Xin He, Guihai Yan, Yinhe Han, Xiaowei Li

Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads

Samantak Gangopadhyay, Youngtak Lee, Saad Bin Nasir, Arijit Raychowdhury

6.5 Beyond EDA: Extending the Application Domain of Formal Methods

Chair: Christoph Scholl, University of Freiburg, DE; Gianpiero Cabodi, Politecnico di Torino, IT

Using MaxBMC for Pareto-Optimal Circuit Initialization

Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker

Partial Witnesses from Preprocessed Quantified Boolean Formulas

Martina Seidl, Robert Könighofer

Equivalence Checking for Function Pipelining in Behavioral Synthesis

Kecheng Hao, Sandip Ray, Fei Xie

Towards the Formal Analysis of Microresonators Based Photonic Systems

Umair Siddique, Sofiène Tahar

SKETCHILOG: Sketching Combinational Circuits

Andrew Becker, David Novo, Paolo Ienne

Towards Verifying Determinism of SystemC Designs

Hoang M. Le, Rolf Drechsler

6.6 Model-Based Design and Hardware/Software Interfaces

Chairs: Wang Wang Yi, Uppsala University, SE; Oliver Bringmann, University of Tübingen, DE

Library-Based Scalable Refinement Checking for Contract-Based Design

Antonio Iannopollo, Pierluigi Nuzzo, Stavros Tripakis, Alberto Sangiovanni-Vincentelli

Isochronous Networks by Construction

Yu Bai, Klaus Schneider

Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters

Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini

p-OFTL: An Object-based Semantic-aware Parallel Flash Translation Layer

Wei Wang, Youyou Lu, Jiwu Shu

Using Guided Local Search for Adaptive Resource Reservation in Large-scale Embedded Systems

Timon D. ter Braak

Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation

Eunhyek Park, Sungjoo Yoo, Sunggu Lee, Helen Li

6.7 Hardening Approaches at Different Design Levels

Chairs: Lorena Anghel, TIMA, FR; Jaume Abella, BSC, ES

Nostradamus: Low-Cost Hardware-Only Error Detection for Processor Cores

Ralph Nathan, Daniel J. Sorin

Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications

B. Alorda, C. Carmona, S. Bota

A High Performance SEU-Tolerant Latch for Nanoscale CMOS Technology

Zhengfeng Huang

A Low-Cost Radiation Hardened Flip-flop

Yang Lin, Mark Zwolinski, Basel Halak

PSP-Cache: A Low-Cost Fault-Tolerant Cache Memory Architecture

Hamed Farbeh, Seyed Ghassem Miremadi

A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction

Pilin Junsangsri, Fabrizio Lombardi, Jie Han

7.0 Special Day Keynote

The Connected Car and Its Implication to the Automotive Chip Roadmap

Michael Bolle, Robert Bosch GmbH, DE

7.2 Embedded Tutorial: Cross Layer Resiliency in Real World

Organizer: Vikas Chandra, ARM, US
Chairs: Yanjing Li, Intel, US; Ulf Schlichtmann, TUM, DE

Cross Layer Resiliency in Real World

Vikas Chandra

7.3 Low Power Methods and Multicore Architectures for Mobile Health Applications

Chairs: Ashoka Sathanur, Philips, NL; Giovanni Ansaloni, EPFL, CH

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes

Rubén Braojos, Ahmed Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza

Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors

Daniele Bortolotti, Andrea Bartolini, Christian Weis, Davide Rossi, Luca Benini

Context Aware Power Management for Motion-sensing Body Area Network Nodes

Filippo Casamassima, Elisabetta Farella, Luca Benini

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability

Georgios Karakonstantis, Aviinaash Sankaranarayanan, Mohamed M. Sabry, David Atienza, Andreas Burg

Battery Aware Stochastic QoS Boosting in Mobile Computing Devices

Hao Shen, Qiuwen Chen, Qinru Qiu

7.4 Runtime Memory Optimization and GPU/Manycore Architectures

Chairs: Alberto Nannarelli, DTU Copenhagen, DK; Alberto Macii, PoliTo Torino, IT

Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization

Karthik Chandrasekar, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, Kees Goossens

Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache

Haroon Mahmood, Massimo Poncino, Enrico Macii

On GPU Bus Power Reduction with 3D IC Technologies

Young-Joon Lee and Sung Kyu Lim

Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking

Paula Aguilera, Jungseob Lee, Amin Farmahini-Farahani, Katherine Morrow, Michael Schulte, Nam Sung Kim

A Thermal Resilient Integration of Many-core Microprocessors and Main Memory by 2.5D TSI I/Os

Sih-Sian Wu, Kanwen Wang, Sai Manoj P. D., Tsung-Yi Ho, Mingbin Yu, Hao Yu

Leveraging On-Chip Networks for Efficient Prediction on Multicore Coherence

Libo Huang

An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems

Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi

7.5 Emerging Memory Technologies

Chairs: Aida Todri, CNRS .FR; Lars Bauer, KIT, DE

Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM

Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi B. Tahoori

Write-Once-Memory-Code Phase Change Memory

Jiayin Li, Kartik Mohanram

Improving STT-MRAM Density through Multibit Error Correction

Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar

Energy Efficient In-Memory AES Encryption Based on Nonvolatile Domain-wall Nanowire

Yuhao Wang, Hao Yu, Dennis Sylvester, Pingfan Kong

ICE: Inline Calibration for Memristor Crossbar-based Computing Engine

Boxun Li, Yu Wang, Yiran Chen, Hai (Helen) Li, Huazhong Yang

Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication

Yuanfan Yang, Jimson Mathew, Dhiraj K Pradhan, Marco Ottavi, Salvatore Pontarelli

7.6 Performance and Timing Analysis

Chairs: Wang Wang Yi, Uppsala University, SE Petru Petru Eles, Linköping University, SE

Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces

Sofiane Lagraa, Alexandre Termier, Frédéric Pétrot

Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems

Neil Dhruva, Pratyush Kumar, Georgia Giannopoulou, Lothar Thiele

Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints

Di Liu, Jelena Spasic, Jiali Teddy Zhai, Todor Stefanov, Gang Chen

A Layered Approach for Testing Timing in the Model-Based Implementation

BaekGyu Kim, Hyeon I Hwang, Taejoon Park, Sang H. Son, Insup Lee

Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP

Kenneth Balck, Olga Grinchtein, Justin Pearson

Time-Decoupled Parallel SystemC Simulation

Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto

A Unified Methodology for a Fast Benchmarking of Parallel Architecture

Alexandre Guerre, Jean-Thomas Acquaviva, Yves Lhuillier

7.7 Design-for-Test and Test Access

Chairs: Erik Jan Marinissen, IMEC, BE; Hans-Joachim Wunderlich, Univ. of Stuttgart, DE

Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test

Michael E. Imhof, Hans-Joachim Wunderlich

Testing PUF-Based Secure Key Storage Circuits

Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale

Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network

Adam Zygmontowicz, Jennifer Dworak, Al Crouch, John Potter

Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement

Andrew B. Kahng, Ilgweon Kang

8.1 System Simulation and Virtual Prototyping

Organizer: Johannes Stahl, Synopsys, US; Chair: Johannes Stahl, Synopsys, US

Power Modeling and Analysis in Early Design Phases

Bernhard Fischer, Christian Cech, Hannes Muhr

System-level Design Methodology Enabling Fast Development of Baseband MP-SoC for 4G Small Cell Base Station

Shan Tang, Ziyuan Zhu, Yongtao Su

Virtual Prototype Life Cycle in Automotive Applications

Manfred Thanner

8.2 Hot Topic: Near Threshold Computing (NTC)

Organizer: Michael Huebner, Ruhr-University Bochum, DE
Chair: Michael Huebner, Ruhr-University Bochum, DE

Extreme-Scale Computer Architecture: Energy Efficiency from the Ground up

Josep Torrellas

Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon

Cristina Silvano, Gianluca Palermo, Sotirios Xydis, Ioannis Stamelakos

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing

Tobias Gemmeke, Mohamed M. Sabry, Jan Stuijt, Praveen Raghavan, Francky Catthoor, David Atienza

8.3 Physical Attacks and Countermeasures

Chairs: Francesco Regazzoni, Alari, CH ;Shivam Bhasin, Telecom Paristech, FR

Efficiency of a Glitch Detector against Electromagnetic Fault Injection

Loic Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, Ludovic Guillaume-Sage, Jessy Clediere, Assia Tria

Analyzing and Eliminating the Causes of Fault Sensitivity Analysis

Nahid Farhady Ghalaty, Aydin Aysu, Patrick Schaumont

A Smaller and Faster Variant of RSM

Noritaka Yamashita, Kazuhiko Minematsu, Toshihiko Okamura, Yukiyasu Tsunoo

A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks

Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle

8.4 Efficient Designs for Telecom and Financial Applications

Chair: Sergio Saponara, University of Pisa, IT; Amer Baghdadi, Telecom Bretagne, FR

Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations

David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor

Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL

Valentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton

Hardware Implementation of a Reed-Solomon Soft Decoder Based on Information Set Decoding

Stefan Scholl, Norbert Wehn

Ambient Variation-tolerant and Inter Components Aware Thermal Management for Mobile System on Chips

Francesco Paterna, Joe Zanotelli, Tajana Simunic Rosing

Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition

Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor

Mode-Controlled Dataflow Based Modeling & Analysis of a 4G-LTE Receiver

Hrishikesh Salunkhe, Orlando Moreira, Kees van Berkel

8.5 Modeling & Specification

Chairs: Wolfgang Mueller, University of Paderborn, DE; Francois PECHEUX, UPMC, FR

An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations

Shu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay

Automatic Specification Granularity Tuning for Design Space Exploration

Jiaxing Zhang, Gunar Schirner

EDT: A Specification Notation for Reactive Systems

R. Venkatesh, Ulka Shrotri, G. Murali Krishna, Supriya Agrawal

Model-Based Actor Multiplexing with Application to Complex Communication Protocols

Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich

A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving

Alexander Biewer, Jens Gladigau, Christian Haubelt

DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling

Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano

8.6 Mapping and Scheduling for Many-Core Embedded Systems

Chairs: Marc Geilen, Eindhoven University of Technology, NL; Sébastien Le Beux, Ecole Centrale de Lyon, FR

Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing

Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel

GPU-EvR: Run-time Event Based Real-time Scheduling Framework on GPGPU Platform

Haeseung Lee, Mohammad Abdullah Al Faruque

Multi-Objective Distributed Run-time Resource Management for Many-Cores

Stefan Wildermann, Michael Glaβ, Jürgen Teich

CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel

Andrew Nelson, Ashkan Beyranvand Nejad, Anca Molnos, Martijn Koedam, Kees Goossens

Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor

Myungsun Kim, Kibeom Kim, James R. Geraci, Seongsoo Hong

hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding

Daniel Palomino, Muhammad Shafique, Hussam Amrouch, Altamiro Susin, Jörg Henkel

Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions

Mehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram

8.7 Performance Modeling and Delay Test

Chairs: Robert Aitken, ARM, US Mehdi Tahoori, KIT, DE

Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation

Li Yu, Sharad Saxena, Christopher Hess, Ibrahim (Abe) M. Elfadel, Dimitri Antoniadis, Duane Boning

Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction

Shuangyue Zhang, Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng, Hong Wang

Substituting Transition Faults with Path Delay Faults as a Basic Delay Fault Model

Irith Pomeranz

Standard Cell Library Tuning for Variability Tolerant Designs

Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations

André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann

8.8 Hot Topic: Beyond CMOS Ultra-low-power Computing

Organizer: Saibal Mukhopadhyay, Georgia Institute of Technology, US
Chairs: Arijit Raychowdhury, Georgia Institute of Technology, US; Saibal Mukhopadhyay, Georgia Institute of Technology, US

Ultra-low Power Electronics with Si/Ge Tunnel FET

Amit Ranjan Trivedi, Mohammad Faisal Amir, Saibal Mukhopadhyay

Brain-Inspired Computing with Spin Torque Devices

Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra

Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic

Swarup Bhunia, Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Rui Yang, Mehran Mehregany, Philip X.-L. Feng

9.1 Hot Topic: CMOS Scaling - from Evolutionary to Revolutionary Computing

Organizers: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR
Chairs: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR

III-V Semiconductor Nanowires for Future Devices

H. Schmid, B.M. Borg, K. Moselund, P. Das Kunungo, G. Signorello, S. Karg, P. Mensch, V. Schmidt, H. Riel

Advanced System on a Chip Design Based on Controllable-Polarity FETs

Pierre-Emmanuel Gaillardon, Luca Amaru, Jian Zhang, Giovanni De Micheli

Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges

Walter M. Weber, Jens Trommer, Matthias Grube, André Heinzig, Markus König, Thomas Mikolajick

Advancing CMOS with Carbon Electronics

Franz Kreupl

9.2 Low-Cost, High-Performance NoCs

Chairs: Kees Goossens, Eindhoven University, NL; Luca Ramini, University of Ferrara, IT

Application Mapping for Express Channel-Based Networks-on-Chip

Di Zhu, Lizhong Chen, Siyu Yue, Massoud Pedram

Parallel Probe Based Dynamic Connection Setup in TDM NoCs

Shaoteng Liu, Axel Jantsch, Zhonghai Lu

ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers

I. Seitanidis, A. Psarras, G. Dimitrakopoulos, C. Nicopoulos

Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs

Marta Ortín, Darío Suárez, María Villarroya, Cruz Izu, Víctor Viñals

Improving Hamiltonian-based Routing Methods for On-chip Networks: A Turn Model Approach

Poona Bahrebar, Dirk Stroobandt

9.3 Hardware Implementations for Data Security

Chairs: Viktor Fischer, St Etienne, FR; Filippo Melzani, STMicroelectronics, IT

Embedded Reconfigurable Logic for ASIC Design Obfuscation against Supply Chain Attacks

Bao Liu, Brandon Wang

A Minimalist Approach to Remote Attestation

Aurélien Francillon, Quan Nguyen, Kasper B. Rasmussen, Gene Tsudik

Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support

Pranav Koundinya, Sandhya Theril, Tao Feng, Varun Prakash, Jiming Bao, Weidong Shi

HEROIC: Homomorphically EncRypted One Instruction Computer

Nektarios Georgios Tsoutsos, Michail Maniatakos

EDA Tools Trust Evaluation through Security Property Proofs

Yier Jin

9.4 Timing challenges in validation

Chairs: Elena Ioana Vatajelu, Politecnico di Torino, IT; Mark Zwolinski, University of Southampton, UK

Fast STA Prediction-based Gate-level Timing Simulation

Tariq B. Ahmad, Maciej J. Ciesielski

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

V. Guarnieri, M. Petricca, A. Sassone, S. Vinco, N. Bombieri, F. Fummi, E. Macii, M. Poncino

Empowering Study of Delay Bound Tightness with Simulated Annealing

Xueqian Zhao, Zhonghai Lu

Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models

Yanchen Long, Zhonghai Lu, Xiaolang Yan

9.5 Hot Topic: Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test

Organizers: Ulf Schlichtmann, Technische Universität München, DE; Andreas Herkersdorf, Technische Universität München, DE
Chairs: Nikil Dutt, University of California, Irvine, US; Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test

Ulf Schlichtmann, Veit B. Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaβ, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn

9.6 Schedulability Analysis

Chair: Rob Davis, University of York, UK; Giuseppe Lipari, ENS - Cachan, FR

Rate-Adaptive Tasks: Model, Analysis, and Design Issues

Giorgio C. Buttazzo, Enrico Bini, Darren Buttle

Acceptance and Random Generation of Event Sequences under Real Time Calculus Constraints

Kajori Banerjee, Pallab Dasgupta

General and Efficient Response Time Analysis for EDF Scheduling

Nan Guan, Wang Yi

The Schedulability Region of Two-Level Mixed-Criticality Systems Based on EDF-VD

Dirk Müller, Alejandro Masrur

9.7 Timing Analysis and Cell Design

Chairs: Jose Monteiro, INESC-ID / Tecnico, ULisboa, PT; Elena Dubrova, Royal Institute of Technology, SE

Facilitating Timing Debug by Logic Path Correspondence

Oshri Adler, Eli Arbel, Ilia Averbouch, Ilan Beer, Inna Grijnevitch

Statistical Static Timing Analysis Using a Skew-Normal Canonical Delay Model

Vijaykumar M, V Vasudevan

Leakage-Power-Aware Clock Period Minimization

Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh

A Deep Learning Methodology to Proliferate Golden Signoff Timing

Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan

Aging-aware Standard Cell Library Design

Saman Kiamehr, Farshad Firouzi, Mojtaba Ebrahimi, Mehdi B. Tahoori

Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs

Kitae Park, Geunho Kim, Taewhan Kim

9.8 Embedded Tutorial: Memcomputing: The Cape of Good Hope

Organizers: Yiyu Shi, Missouri University of Science & Technology, US; Hung-Ming Chen, National Chiao Tung University,Taiwan
Chairs: Yiyu Shi, Missouri University of Science & Technology, US; Hung-Ming Chen, National Chiao Tung University,Taiwan, Taiwan

Memcomputing: The Cape of Good Hope

Yiyu Shi, Hung-Ming Chen

MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies

Chun Zhang, Peng Deng, Hui Geng, Jianming Liu, Qi Zhu, Jinjun Xiong, Yiyu Shi

Energy-Efficient Hardware Acceleration through Computing in the Memory

Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri

10.1 Hot Topic: Memories Today and Tomorrow

Organizers: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR
Chairs: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE

Exploring the Limits of Phase Change Memories

Matthias Wuttig

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips

G. Prenat, G. Di Pendina, C. Layer, O. Goncalves, K. Jaber, B. Dieny, R. Sousa, I.L. Prejbeanu, J.P. Nozieres

Resistive Memories: Which Applications?

Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean-Michel Portal, Marc Bocquet

Thinfilm Printed Ferro-Electric Memories and Integrated Products

Christer Karlsson, Peter Fischer

10.2 Wireless NoCs

Chairs: Giorgos Dimitrakopoulos, Democritus University of Thrace, GR; Valeria Bertacco, University of Michigan, US

An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs

Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania

Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies

Paul Wettin, Jacob Murray, Ryan Kim, Xinmin Yu, Partha Pratim Pande, Deukhyoun Heo

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips

Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano

Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip

Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, Kenneth Tong, Terrence Mak, Alex Yakovlev

Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems

Eberle A Rambo, Alexander Tschiene, Jonas Diemer, Leonie Ahrendts, Rolf Ernst

10.3 Green Computing Systems

Chairs: Ayse Coskun, Boston University, US; Martino Ruggiero, University of Bologna, IT

Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers

Jungsoo Kim, Mohamed M. Sabry, David Atienza, Kalyan Vaidyanathan, Kenny Gross

Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World

Andrea Bartolini, Matteo Cacciari, Carlo Cavazzoni, Giampietro Tecchiolli, Luca Benini

Contention Aware Frequency Scaling on CMPs with Guaranteed Quality of Service

Hao Shen, Qinru Qiu

Concurrent Placement, Capacity Provisioning, and Request Flow Control for a Distributed Cloud Infrastructure

Shuang Chen, Yanzhi Wang, Massoud Pedram

COOLIP: Simple yet Effective Job Allocation for Distributed Thermally-Throttled Processors

Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh

Mohammadsadegh Sadri, Matthias Jung, Christian Weis, Norbert Wehn, Luca Benini

10.4 System-level Evaluation

Chairs: Pablo Sanchez, University of Cantabria, ES Florian Letombe, Synopsys, FR

Automatic Detection of Concurrency Bugs through Event Ordering Constraints

Luis Gabriel Murillo, Simon Wawroschek, Jeronimo Castrillon, Rainer Leupers, Gerd Ascheid

Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs

Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives

Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Salvatore Galfano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Pirero Olivo, Davide Bertozzi

Efficient Simulation and Modelling of Non-rectangular NoC Topologies

Ji Qi, Mark Zwolinski

Moving from Co-Simulation to Simulation for Effective Smart Systems Design

Franco Fummi, Michele Lora, Francesco Stefanni, Dimitrios Trachanis, Jan Vanhese, Sara Vinco

10.5 Analysis of Components and Systems

Chairs: Frank Oppenheimer, OFFIS, DE; Todor Stefanov, Leiden University, NL

May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models

Weiwei Chen, Xu Han, Rainer Dömer

Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs

R.M.W.Frijns, S.Adyanthaya, S.Stuijk, J.P.M.Voeten, M.C.W.Geilen, R.R.H.Schiffelers, H.Corporaal

A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures

Sébastien Le Nours, Adam Postula, Neil W. Bergmann

Cross-correlation of Specification and RTL for Soft IP Analysis

Bhanu Singh, Arunprasath Shankar, Francis Wolff, Christos Papachristou, Daniel Weyer, Steve Clay

10.6 Multi-processor and Distributed Systems

Chairs: Orlando Moreira, Ericsson, NL; Benny Akesson, CTU, CZ

Thermal-Aware Frequency Scaling for Adaptive Workloads on Heterogeneous MPSoCs

Heng Yu, Rizwan Syed, Yajun Ha

Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms

Chuancai Gu, Nan Guan, Qingxu Deng, Wang Yi

Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications

Akramul Azim, Gonzalo Carvajal, Rodolfo Pellizzoni, Sebastian Fischmeister

10.7 Advances in Synthesis

Chairs: John Hayes, University of Michigan, US; Kim Taemin, Intel Labs, US

Provably Minimal Energy Using Coordinated DVS and Power Gating

Nathaniel A. Conos, Saro Meguerdichian, Foad Dabiri, Miodrag Potkonjak

A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments

Syed Rameez Naqvi, Andreas Steininger

An Efficient Manipulation Package for Biconditional Binary Decision Diagrams

Luca Amarú, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Synthesis Algorithm of Parallel Index Generation Units

Yusuke Matsunaga

Automating Data Reuse in High-Level Synthesis

Wim Meeus, Dirk Stroobandt

A Universal Symmetry Detection Algorithm

Peter M. Maurer

Optimization of Design Complexity in Time-Multiplexed Constant Multiplications

Levent Aksoy, Paulo Flores, José Monteiro

Hardware Primitives for the Synthesis of Multithreaded Elastic Systems

G. Dimitrakopoulos, I. Seitanidis, A. Psarras, K. Tsiouris, P. Mattheakis, J. Cortadella

11.0 Special Day Keynote: Organic Electronics - From Lab to Markets

Karl Leo - Technische Universität Dresden, DE

Organizers: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE
Chairs: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE

Chairs: Masoud Daneshtalab, University of Turku, FI; Hiroki Matsutani, Keio University, JP

Chairs: Emil Matus, Technische Universität Dresden, DE; Norbert Wehn, TU Kaiserslautern. DE

Chairs: Ronny Morad, IBM, IL; Franco Fummi, Universita' di Verona, IT

Chairs: Andreas Herkersdorf, Technische Universität Munchen, DE; Donatella Sciuto, Politecnico di Milano,IT

Chairs: Coskun Ayse, Boston University, US; Wolfgang Nebel, OFFIS, DE

Chairs: Diana Goehringer, Ruhr-University Bochum (RUB), DE; Fabrizio Ferrandi, Politecnico di Milano, IT

Organizesr: Matteo Sonza Reorda, Politecnico di Torino, IT
Chairs: Dimitris Gizopoulos, University of Athens, GR; Rob Aitken, ARM, US

Organizers: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE
Chairs: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR

Organizer: Ulrich Rührmair, TU München, DE
Chair: Ulf Schlichtmann, TU München, DE

Chairs: Theocharides Theocharis, University of Cyprus, CY; Cristiana Bolchini, Politecnico di Milano, IT

Chair: Carl Sechen, University of Texas at Dallas, US; Jens Lienig, TU Dresden, DE

Chairs: Frederic Petrot, TIMA, FR; Luciano Lavagno, Politecnico di Torino, IT

Chairs: William Fornaciari, Politecnico di Milano - DEIB, IT; Kim Gruettner, OFFIS, DE

Chairs: Jacob A. Abraham, University of Texas at Austin, US; Marian Verhelst, KU Leuven, BE

Organizer: Alex Goryachev, IBM Research - Haifa, IL
Chair: Rolf Drechsler, University of Bremen/DFKI,DE