Chair: Ingo Sander, KTH Royal Institute of Technology, SE, Contact

Co-Chair: Frederic Mallet, University of Nice Sophia Antipolis, FR, Contact

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Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; performance modeling; timing analysis; predictive and learning-based models; system-level platform and architecture models and simulation ; heterogeneous systems and models.

Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact

Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact

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High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; multi-objective optimization techniques (e.g., performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.

Chair: Graziano Pravadelli, Università di Verona, IT, Contact

Co-Chair: Avi Ziv, IBM Research - Haifa, IL, Contact

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Simulation-based and semi-formal validation and verification of: SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including digital, analog, interconnect and mixed-signal components. In addition: testbench and assertion generation and qualification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon diagnosis and debugging solutions, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities; with or without the employment of artificial intelligence or machine learning techniques.

Chair: Armin Biere, Johannes Kepler Universität Linz, AT, Contact

Co-Chair: Alessandro Cimatti, Fondazione Bruno Kessler, IT, Contact

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Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, decomposition techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis.

Chair: Georges Gielen, KU Leuven, BE, Contact

Co-Chair: Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact

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Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

Chair: Ilia Polian, Universität Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

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Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; machine learning for hardware security evaluation .

Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact

Co-Chair: Masoud Daneshtalab, KTH Royal Institute of Technology, SE, Contact

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Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, NoC and communication-centric design, including: topology, switching, routing and flow control; communication-aware frameworks for Quality-of-Service, security, robustness, power, variability and thermal management; design space exploration frameworks and programming models for communication-centric design; interconnects for domain-specific applications (high performance computing, approximate computing, machine learning, 5G, etc.); design of interconnects using alternative/emerging technologies (photonics/optics, wireless, 3D stacking etc.)

Chair: Francisco Cazorla, Barcelona Supercomputing Center and IIIA-CSIC, ES, Contact

Co-Chair: Olivier Sentieys, INRIA, FR, Contact

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Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, safety, and timing predictability.

Chair: Naehyuck Chang, KAIST, KR, Contact

Co-Chair: Andrea Calimera, Politecnico di Torino, IT, Contact

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Theories, tools and methodologies for power modeling, estimation and optimization for electronics systems, applicable to at all layers of design (hardware, software, systems and cross-layers) with a strong emphasis on "power" as the primary optimization target, ranging from ultra-low power systems to high-performance systems also including energy harvesting, cyber-physical systems, large-scale battery applications (electric vehicles, energy storage systems, etc.), Internet of Things, and Artificial Intelligence.

Chair: Jose L. Ayala, Complutense University of Madrid, ES, Contact

Co-Chair: Qinru Qiu, Syracuse University, US, Contact

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Theories, tools and methodologies for power modeling, estimation and optimization for electronics systems, applicable to at all layers of design (hardware, software, systems and cross-layers) with a strong emphasis on "power" and "energy" as the primary optimization target, ranging from ultra-low power systems to high-performance systems also including energy harvesting, cyber-physical systems, large-scale battery applications (electric vehicles, energy storage systems, etc.), Internet of Things, and artificial intelligence.

Chair: Philip Brisk, University of California, Riverside, US, Contact

Co-Chair: Suhaib A. Fahmy, University of Warwick, GB, Contact

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Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data center and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

Chair: Tiziano Villa, Università di Verona, IT, Contact

Co-Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact

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Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

Chair: Aida Todri-Sanial, CNRS-LIRMM/University of Montpellier, FR, Contact

Co-Chair: Subhasish Mitra, Stanford University, US, Contact

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Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).

Chair: Jean-Michel Portal, Aix-Marseille University, FR, Contact

Co-Chair: Pierre-Emmanuel Gaillardon, University of Utah, US, Contact

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Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.

Chair: Muhammad Shafique, Technische Universität Wien, AT, Contact

Co-Chair: Baris Aksanli, San Diego State University, US, Contact

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Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.

Chair: Paolo Fiorini, University of Verona, IT, Contact

Co-Chair: Torsten Kroeger, Karlsruhe Institute of Technology, DE, Contact

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Bringing together robotics and machine learning concepts requires research and development efforts in interdisciplinary domains. With Industry 4.0 and its goal of adding utility value through data analytics and optimiztion, the Topic "Robotics and Industry 4.0" will remain at the core of the value creation chain during the next decade. The topic covers the field of robotics on topics from sensors and sensory interpretations to kinematics in motion planning, from distributed software concepts for data collection and analysis to large-scale machine learning algorithms, and sensor-based robot and machine control to safe human-robot interaction concepts.

Chair: Davide brunelli, University of Trento, IT, Contact

Co-Chair: Sebastian Steinhorst, Technische Universität München, DE, Contact

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Design experiences for automotive systems, energy-neutral embedded systems, smart energy systems (from uW to microgrid), and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits; MEMS; integrated sensors and transducers; RF architectures; in-vehicle networks; systems for electric vehicles; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; hardware solutions for runtime system management such as self-diagnostics and repair; energy generation; battery management, and renewable energy subsystems; optimization of system energy efficiency in the context of automotive or smart energy applications.

Chair: Theocharis Theocharides, University of Cyprus, CY, Contact

Co-Chair: Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT, Contact

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Design experiences covering the use of body area networks, assistive and wearable technologies, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management ; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness ; embedded and edge-based machine learning for augmented living.

Chair: Ingrid Verbauwhede, IMEC / KU Leuven, BE, Contact

Co-Chair: Lionel Torres, Université de Montpellier, FR, Contact

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Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; emerging technologies for secure circuits and architectures, novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

Chair: Antonio Miele, Politecnico di Milano, IT, Contact

Co-Chair: Gilles Sassatelli, LIRMM CNRS / University of Montpellier 2, FR, Contact

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Self-adaptive systems, algorithms and techniques for run-time decision-making targeting various optimization goals such as compute performance, energy/power-efficiency or reliability and considering various architectural platforms, such as high-performance compute nodes, power-constrained edge computing technologies and reconfigurable systems. Topics of interests include: adaptive strategies for runtime resource management; application, design and tuning of machine learning techniques for offline and/or online modeling, prediction/forecasting and control of self-adaptive systems; hybrid offline/online techniques for online decision-making; context-aware adaptation strategies and mechanisms; application of diverse data mining, modeling and optimization techniques (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive and learning systems.

Chair: Andy Tyrrell, University of York, GB, Contact

Co-Chair: Yu Wang, Nanjing University of Posts and Telecommunications, CN, Contact

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Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

Chair: Fabien Clermidy, CEA-Leti, FR, Contact

Co-Chair: Norbert Wehn, University of Kaiserslautern, DE, Contact

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Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.

Chair: Said Hamdioui, Delft University of Technology, NL, Contact

Co-Chair: Jose Pineda, NXP Semiconductors, NL, Contact

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Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

Chair: Patrick Girard, LIRMM, FR, Contact

Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

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Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, debug and post silicon validation; machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

Chair: Jaume Abella, Barcelona Supercomputing Center (BSC-CNS), ES, Contact

Co-Chair: Ramon Canal, Universitat Politècnica de Catalunya, ES, Contact

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Micro/architectures for fault-tolerant systems against permanent, transient and soft errors, including (but not limited to) processors, memories and accelerators; micro/architectural solutions for safety- and mission-critical systems; analysis and evaluation of reliability, availability and maintainability; hardware/software micro/architectural solutions for fault detection, recovery and aging mitigation.

Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY, Contact

Co-Chair: Georgios Karakonstantis, Queen's University Belfast, GB, Contact

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HW and SW solutions for availability, reliability and maintainability against permanent, intermittent, transient, and aging phenomena; system level error/fault modeling; dependability analysis and evaluation; beyond worst-case design solutions, reliable and fail-safe system design; on-line test and functional safety; runtime system management for self-diagnostics and repair; system/runtime orchestration of cross-layer solutions, application resilience, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability including fault prediction, tolerance, detection, isolation, and mitigation; solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

Chair: Georges Gielen, KU Leuven, BE, Contact

Co-Chair: Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact

Topic Members (click to open)

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

Chair: Ilia Polian, Universität Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

Topic Members (click to open)

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; machine learning for hardware security evaluation .

Topic Members (click to open)

Topic Members (click to open)

Topic Members (click to open)

Chair: Kai Lampka, Electrobit Automotive GmbH, DE, Contact

Co-Chair: Dionisio de Niz, Carnegie Mellon University, US, Contact

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Real-time performance modeling, analysis and empirical evaluation; Worst-case performance analysis techniques; Worst-case execution time analysis; Real-time schedulability of multicore systems; Mixed-Criticality scheduling; Real-time operating systems, microkernels and software; Use of hardware virtualization techniques in time critical applications, Power-aware real-time systems; Industrial case studies of real-time, networked and dependable systems; Adaptive real-time systems; Dependable systems including safety and criticality; Network control and QoS for embedded applications;

Chair: Akash Kumar, Technische Universität Dresden, DE, Contact

Co-Chair: Sander Stuijk, Eindhoven University of Technology, NL, Contact

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Hardware and architectures, software and algorithmic approaches for artifical intelligence, machine learning and deep learning; resource-efficient and/or low-power embedded architectures for deep learning - specialized compute architectures for machine learning systems - approximate architectures for machine learning applications - learning from limited data sets - novel neural networks architectures and concepts - frameworks for probabilistic and deep learning programming - implementation of DNN applications on embedded systems

Chair: Yliès Falcone, Univ. Grenoble Alpes, Inria, FR, Contact

Co-Chair: Todd Austin, University of Michigan, US, Contact

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Verification techniques for embedded ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as security, timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems. Security attacks, protection and analysis of embedded systems' hardware and software.

Chair: Borzoo Bonakdarpour, Iowa State University, US, Contact

Co-Chair: Eli Bozorgzadeh, Univ. of California, Irvine, US, Contact

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Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, WCET, etc.; Real-time software, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

Chair: Shiyan Hu, Michigan Technological University, US, Contact

Co-Chair: Davide Quaglia, Università di Verona, IT, Contact

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Modeling, design, analysis, and optimization of Cyber-Physical Systems (CPS) also in case of large-scale cyber physical systems; verification and validation in CPS; safety and security in CPS; modeling, design, and analysis of internet-of-things as CPS; software-intensive CPS; data-mining and CPS; autonomous and semi-autonomous CPS and related issues; socio-technical systems (e.g., empowered consumer and organizational behavior in smart grids) and CPS; cognitive control for CPS; modeling, design and analysis of networked control, switched control, and distributed control systems: control/architecture co-design and architecture-aware controller synthesis.