DATE 2006 DESIGNERS' FORUM, TABLE OF CONTENTS

Designers' Forum Committee

4D: Secure and Security Systems

Architectures for Efficient Face Authentication in Embedded Systems [p. 1]

N. Aaraj, S. Ravi, A. Raghunathan and N. K. Jha

Software Implementation of Tate Pairing over GF(2^m) [p. 7]

G. Bertoni, L. Breveglieri, P. Fragneto, G. Pelosi and L. Sportiello

Optimization of Regular Expression Pattern Matching Circuits on FPGA [p. 12]

C.-H. Lin, C.-T. Huang, C.-P. Jiang and S. C. Chang

Satisfiability-Based Framework for Enabling Side-Channel Attacks on Cryptographic Software [p. 18]

N. R. Potlapally, A. Raghunathan, S. Ravi, N. K. Jha and R. B. Lee

An 830mW, 586kbps 1024-Bit RSA Chip Design [p. 24]

C. Yeh, E.-F. Hsu, K.-W. Cheng, J.-S. Wang and N.-J. Chang

Platform Independent Debug Port Controller Architecture with Security Protection for Multi-Processor System-on-Chip ICs [p. 30]

D. Akselrod, A. Ashkenazi and Y. Amon

5D: Reconfigurable Computing

Automated Conversion from LUT-Based FPGA to a LUT-Based MPGA with Fast Turnaround Time [p. 36]

F.-J. Veredas, M. Scheppler and H.-J. Pfleiderer

Energy-Efficient FPGA Interconnect Design [p. 42]

M. Meijer, R. Krishnan and M. Bennebroek

A New Approach to Compress the Configuration Information of Programmable Devices [p. 48]

M. Martina, G. Masera, A. Molino, F. Vacca, L. Sterpone and M. Violante

Design and Implementation of a Rendering Algorithm in a SIMD Reconfigurable Architecture (MorphoSys) [p. 52]

J. Davila, A. de Torres, J. M. Sanchez, M. Sanchez-Elez, N. Bagherzadeh and F. Rivera

Application Specific Instruction Processor Based Implementation of a GNSS Receiver on an FPGA [p. 58]

G. Kappen and T. G. Noll

A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]

M. Hutton, R. Yuan, J. Schleicher, G. Baeckler, S. Cheung, K. K. Chua and H. K. Phoon

6D: Specification and Verification

Synthesis of System Verilog Assertions [p. 70]

S. Das, R. Mohanty, P. Dasgupta and P. P. Chakrabarti

Generating Finite State Machines from SystemC [p. 76]

A. Habibi, H. Moinudeen and S. Tahar

Flexible Specification and Application of Rule-Based Transformations in an Automotive Design Flow [p. 82]

J. H. Oetjens, J. Gerlach and W. Rosenstiel

A Mixed-Signal Verification Kit for Verification of Analogue-Digital Circuits [p. 88]

G. Bonfini, M. Chiavacci, R. Mariani and E. Pescari

A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories [p. 94]

P. Daglio

Software-Friendly HW/SW Co-Simulation: An Industrial Case Study [p. 100]

J. Noguera, L. Baldez, N. Simon and L. Abello

7D: Wireless Communication and Networking

Modeling and Simulation of Mobile Gateways Interacting with Wireless Sensor Networks [p. 106]

F. Fummi, D. Quaglia, F. Ricciato and M. Turolla

A Hardware-Engine for Layer-2 Classification in Low-Storage, Ultra-High Bandwidth Environments [p. 112]

V. Papaefstathiou and I. Papaefstathiou

ASIP Architecture for Multi-Standard Wireless Terminals [p. 118]

D. Lo Iacono, J. Zory, E. Messina, N. Piazzese, G. Saia and A. Bettinelli

Interconnection Framework for High-Throughput, Flexible LDPC Decoders [p. 124]

F. Quaglio, F. Vacca, C. Castellano, A. Tarable and G. Masera

Low Cost LDPC Decoder for DVB-S2 [p. 130]

J. Dielissen, A. Hekstra and V. Berg

3dID: A Low-Power, Low-Cost Hand Motion Capture Device [p. 136]

M. Sama, V. Pacella, E. Farella, L. Benini and B. Riccó

8D: HOT TOPIC - Industrially Proving SPIRIT Consortium Standards for Design Chain Integration

Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]

V. Berman, S. Fazzari, M. Indovina, C. Ussery, M. Strik, J. Wilson, O. Florent, F. Rémond, P. Bricaud

9D: On Chip Communication Networks

Networks on Chips for High-End Consumer-Electronics TV System Architectures [p. 148]

F. Steenhof, H. Duque, B. Nilsson, K. Goossens and R. Peset Llopis

Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh [p. 154]

L. Bononi and N. Concer

GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links [p. 160]

G. Campobello, M. Castano, C. Ciofi and D. Mangano

Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance for a Specific Application [p. 166]

F. Dumitrascu, I. Bacivarov, L. Pieralisi, M. Bonaciu and A.A. Jerraya

STAX: Statistical Crosstalk Target Set Compaction [p. 172]

S. Nazarian, M. Pedram, S.K. Gupta and M.A. Breuer

A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs [p. 178]

K.-H. Cheung and Y.-L. Lo

10D: Automotive

How OEMs and Suppliers Can Face the Network Integration Challenges [p. 183]

K. Richter and R. Ernst

A Practical Implementation of the Fault-Tolerant Daisy-Chain Clock Synchronization Algorithm on CAN [p. 189]

F. C. Carvalho, C. E. Pereira, E. T. Silva, Jr. and E. P. Freitas

On the Verification of Automotive Protocols [p. 195]

G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pasquariello, G. Risaliti and C. Tibaldi

FlexRay Transceiver in a 0.35 µm CMOS High-Voltage Technology [p. 201]

F. Baronti, P. D'Abramo, M. Knaipp, R. Minixhofer, R. Roncella, R. Saletti, M. Schrems, R. Serventi, and V. Vescoli

Space-Efficient FPGA-Accelerated Collision Detection for Virtual Reality [p. 206]

A. Raabe, S. Hochguertel, J. Anlauf and G. Zachmann

Mixed-Signal Design of a Digital Input Power Amplifier for Automotive Audio Applications [p. 212]

S. Saponara and P. Terreni

Interactive Presentations

Automatic SystemC Design Configuration for a Faster Evaluation of Different Partitioning Alternatives [p. 217]

N. Bannow, K. Haug and W. Rosenstiel

Multi-Sensor Configurable Platform for Automotive Applications [p. 219]

L. Serafini, F. Carrai, T. Ramacciotti and V. Zolesi

11D: Media and Signal Processing

Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit [p. 221]

K. Karuri, R. Leupers, G. Ascheid, H. Meyr and M. Kedia

A Novel FPGA-Based Implementation of Time Adaptive Clustering for Logical Story Unit Segmentation [p. 227]

S. Arifin and P. Y. K. Cheung

ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]

L. Fanucci, M. Cassiano, S. Saponara, D. Kammler, E. M. Witte, O. Schleibusch, G. Ascheid, R. Leupers and H. Meyr

A 124.8Msps, 15.6mW Field-Programmable Variable-Length Codec for Multimedia Applications [p. 239]

C. Yeh, C.-C. Wang, L.-C. Lee and J.-S. Wang

The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]

N. Maeding, J. Leenstra, J. Pille, R. Sautter, S. Buettner, S. Ehrenreich and W. Haller

Design and Test of Fixed-Point Multimedia Co-Processor for Mobile Applications [p. 249]

J.-H. Sohn, J. H.-Woo, J. Yoo and H.-J. Yoo