SIGDA, DATE 2006, Designers' Forum, Author Index

DATE 2006 DESIGNERS' FORUM, AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [Y] [Z]

Aaraj, N.: Architectures for Efficient Face Authentication in Embedded Systems [p. 1]
Abello, L.: Software-Friendly HW/SW Co-Simulation: An Industrial Case Study [p. 100]
Akselrod, D.: Platform Independent Debug Port Controller Architecture with Security Protection for Multi-Processor System-on-Chip ICs [p. 30]
Amon, Y.: Platform Independent Debug Port Controller Architecture with Security Protection for Multi-Processor System-on-Chip ICs [p. 30]
Anlauf, J.: Space-Efficient FPGA-Accelerated Collision Detection for Virtual Reality [p. 206]
Arifin, S.: A Novel FPGA-Based Implementation of Time Adaptive Clustering for Logical Story Unit Segmentation [p. 227]
Ascheid, G.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit [p. 221]; ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Ashkenazi, A.: Platform Independent Debug Port Controller Architecture with Security Protection for Multi-Processor System-on-Chip ICs [p. 30]

Bacivarov, I.: Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance for a Specific Application [p. 166]
Baeckler, G.: A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]
Bagherzadeh, N.: Design and Implementation of a Rendering Algorithm in a SIMD Reconfigurable Architecture (MorphoSys) [p. 52]
Baldez, L.: Software-Friendly HW/SW Co-Simulation: An Industrial Case Study [p. 100]
Bannow, N.: Automatic SystemC Design Configuration for a Faster Evaluation of Different Partitioning Alternatives [p. 217]
Baronti, F.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Benini, L.: 3dID: A Low-Power, Low-Cost Hand Motion Capture Device [p. 136]
Bennebroek, M.: Energy-Efficient FPGA Interconnect Design [p. 42]
Berg, V.: Low Cost LDPC Decoder for DVB-S2 [p. 130]
Berman, V.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]
Bertoni, G.: Software Implementation of Tate Pairing over GF(2^m) [p. 7]
Bettinelli, A.: ASIP Architecture for Multi-Standard Wireless Terminals [p. 118]
Bonaciu, M.: Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance for a Specific Application [p. 166]
Bonfini, G.: A Mixed-Signal Verification Kit for Verification of Analogue-Digital Circuits [p. 88]
Bononi, L.: Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh [p. 154]
Breuer, M.A.: STAX: Statistical Crosstalk Target Set Compaction [p. 172]
Breveglieri, L.: Software Implementation of Tate Pairing over GF(2^m) [p. 7]
Bricaud, P.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]
Buettner, S.: The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]

Campobello, G.: GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links [p. 160]
Carrai, F.: Multi-Sensor Configurable Platform for Automotive Applications [p. 219]
Carvalho, F. C.: A Practical Implementation of the Fault-Tolerant Daisy-Chain Clock Synchronization Algorithm on CAN [p. 189]
Cassiano, M.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Castano, M.: GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links [p. 160]
Castellano, C.: Interconnection Framework for High-Throughput, Flexible LDPC Decoders [p. 124]
Chakrabarti, P. P.: Synthesis of System Verilog Assertions [p. 70]
Chang, N.-J.: An 830mW, 586kbps 1024-Bit RSA Chip Design [p. 24]
Chang, S. C.: Optimization of Regular Expression Pattern Matching Circuits on FPGA [p. 12]
Cheng, K.-W.: An 830mW, 586kbps 1024-Bit RSA Chip Design [p. 24]
Cheung, K.-H.: A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs [p. 178]
Cheung, P. Y. K.: A Novel FPGA-Based Implementation of Time Adaptive Clustering for Logical Story Unit Segmentation [p. 227]
Cheung, S.: A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]
Chiavacci, M.: A Mixed-Signal Verification Kit for Verification of Analogue-Digital Circuits [p. 88]
Chua, K. K.: A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]
Ciofi, C.: GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links [p. 160]
Colucci, F.: On the Verification of Automotive Protocols [p. 195]
Concer, N.: Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh [p. 154]

D'Abramo, P.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Daglio, P.: A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories [p. 94]
Das, S.: Synthesis of System Verilog Assertions [p. 70]
Dasgupta, P.: Synthesis of System Verilog Assertions [p. 70]
Davila, J.: Design and Implementation of a Rendering Algorithm in a SIMD Reconfigurable Architecture (MorphoSys) [p. 52]
de Torres, A.: Design and Implementation of a Rendering Algorithm in a SIMD Reconfigurable Architecture (MorphoSys) [p. 52]
Dielissen, J.: Low Cost LDPC Decoder for DVB-S2 [p. 130]
Dumitrascu, F.: Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance for a Specific Application [p. 166]
Dupuis, F.: On the Verification of Automotive Protocols [p. 195]
Duque, H.: Networks on Chips for High-End Consumer-Electronics TV System Architectures [p. 148]

Ehrenreich, S.: The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]
Ernst, R.: How OEMs and Suppliers Can Face the Network Integration Challenges [p. 183]

Fanucci, L.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Farella, E.: 3dID: A Low-Power, Low-Cost Hand Motion Capture Device [p. 136]
Fazzari, S.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]
Florent, O.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]
Fragneto, P.: Software Implementation of Tate Pairing over GF(2^m) [p. 7]
Freitas, E. P.: A Practical Implementation of the Fault-Tolerant Daisy-Chain Clock Synchronization Algorithm on CAN [p. 189]
Fummi, F.: Modeling and Simulation of Mobile Gateways Interacting with Wireless Sensor Networks [p. 106]

Gerlach, J.: Flexible Specification and Application of Rule-Based Transformations in an Automotive Design Flow [p. 82]
Goossens, K.: Networks on Chips for High-End Consumer-Electronics TV System Architectures [p. 148]
Gupta, S.K.: STAX: Statistical Crosstalk Target Set Compaction [p. 172]

Habibi, A.: Generating Finite State Machines from SystemC [p. 76]
Haller, W.: The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]
Haug, K.: Automatic SystemC Design Configuration for a Faster Evaluation of Different Partitioning Alternatives [p. 217]
Hekstra, A.: Low Cost LDPC Decoder for DVB-S2 [p. 130]
Hochguertel, S.: Space-Efficient FPGA-Accelerated Collision Detection for Virtual Reality [p. 206]
Hsu, E.-F.: An 830mW, 586kbps 1024-Bit RSA Chip Design [p. 24]
Huang, C.-T.: Optimization of Regular Expression Pattern Matching Circuits on FPGA [p. 12]
Hutton, M.: A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]

Indovina, M.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]

Jerraya, A.A.: Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance for a Specific Application [p. 166]
Jha, N. K.: Architectures for Efficient Face Authentication in Embedded Systems [p. 1]; Satisfiability-Based Framework for Enabling Side-Channel Attacks on Cryptographic Software [p. 18]
Jiang, C.-P.: Optimization of Regular Expression Pattern Matching Circuits on FPGA [p. 12]

Kammler, D.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Kappen, G.: Application Specific Instruction Processor Based Implementation of a GNSS Receiver on an FPGA [p. 58]
Karuri, K.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit [p. 221]
Kedia, M.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit [p. 221]
Knaipp, M.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Krishnan, R.: Energy-Efficient FPGA Interconnect Design [p. 42]

Lee, L.-C.: A 124.8Msps, 15.6mW Field-Programmable Variable-Length Codec for Multimedia Applications [p. 239]
Lee, R. B.: Satisfiability-Based Framework for Enabling Side-Channel Attacks on Cryptographic Software [p. 18]
Leenstra, J.: The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]
Leupers, R.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit [p. 221]; ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Lin, C.-H.: Optimization of Regular Expression Pattern Matching Circuits on FPGA [p. 12]
Lo, Y.-L.: A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs [p. 178]
Lo, Iacono, D.: ASIP Architecture for Multi-Standard Wireless Terminals [p. 118]

Maeding, N.: The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]
Mangano, D.: GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links [p. 160]
Mariani, R.: A Mixed-Signal Verification Kit for Verification of Analogue-Digital Circuits [p. 88]
Mariani, R.: On the Verification of Automotive Protocols [p. 195]
Martina, M.: A New Approach to Compress the Configuration Information of Programmable Devices [p. 48]
Masera, G.: A New Approach to Compress the Configuration Information of Programmable Devices [p. 48]; Interconnection Framework for High-Throughput, Flexible LDPC Decoders [p. 124]
Meijer, M.: Energy-Efficient FPGA Interconnect Design [p. 42]
Messina, E.: ASIP Architecture for Multi-Standard Wireless Terminals [p. 118]
Meyr, H.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit [p. 221]; ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Minixhofer, R.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Mohanty, R.: Synthesis of System Verilog Assertions [p. 70]
Moinudeen, H.: Generating Finite State Machines from SystemC [p. 76]
Molino, A.: A New Approach to Compress the Configuration Information of Programmable Devices [p. 48]

Nazarian, S.: STAX: Statistical Crosstalk Target Set Compaction [p. 172]
Nilsson, B.: Networks on Chips for High-End Consumer-Electronics TV System Architectures [p. 148]
Noguera, J.: Software-Friendly HW/SW Co-Simulation: An Industrial Case Study [p. 100]
Noll, T. G.: Application Specific Instruction Processor Based Implementation of a GNSS Receiver on an FPGA [p. 58]

Oetjens, J. H.: Flexible Specification and Application of Rule-Based Transformations in an Automotive Design Flow [p. 82]

Pacella, V.: 3dID: A Low-Power, Low-Cost Hand Motion Capture Device [p. 136]
Papaefstathiou, I.: A Hardware-Engine for Layer-2 Classification in Low-Storage, Ultra-High Bandwidth Environments [p. 112]
Papaefstathiou, V.: A Hardware-Engine for Layer-2 Classification in Low-Storage, Ultra-High Bandwidth Environments [p. 112]
Pasquariello, M.: On the Verification of Automotive Protocols [p. 195]
Pedram, M.: STAX: Statistical Crosstalk Target Set Compaction [p. 172]
Pelosi, G.: Software Implementation of Tate Pairing over GF(2^m) [p. 7]
Pereira, C. E.: A Practical Implementation of the Fault-Tolerant Daisy-Chain Clock Synchronization Algorithm on CAN [p. 189]
Pescari, E.: A Mixed-Signal Verification Kit for Verification of Analogue-Digital Circuits [p. 88]
Peset Llopis, R.: Networks on Chips for High-End Consumer-Electronics TV System Architectures [p. 148]
Pfleiderer, H.-J.: Automated Conversion from LUT-Based FPGA to a LUT-Based MPGA with Fast Turnaround Time [p. 36]
Phoon, H. K.: A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]
Piazzese, N.: ASIP Architecture for Multi-Standard Wireless Terminals [p. 118]
Pieralisi, L.: Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance for a Specific Application [p. 166]
Pille, J.: The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]
Potlapally, N. R.: Satisfiability-Based Framework for Enabling Side-Channel Attacks on Cryptographic Software [p. 18]

Quaglia, D.: Modeling and Simulation of Mobile Gateways Interacting with Wireless Sensor Networks [p. 106]
Quaglio, F.: Interconnection Framework for High-Throughput, Flexible LDPC Decoders [p. 124]

Raabe, A.: Space-Efficient FPGA-Accelerated Collision Detection for Virtual Reality [p. 206]
Raghunathan, A.: Architectures for Efficient Face Authentication in Embedded Systems [p. 1]; Satisfiability-Based Framework for Enabling Side-Channel Attacks on Cryptographic Software [p. 18]
Ramacciotti, T.: Multi-Sensor Configurable Platform for Automotive Applications [p. 219]
Ravi, S.: Architectures for Efficient Face Authentication in Embedded Systems [p. 1]; Satisfiability-Based Framework for Enabling Side-Channel Attacks on Cryptographic Software [p. 18]
Rémond, F.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]
Ricciato, F.: Modeling and Simulation of Mobile Gateways Interacting with Wireless Sensor Networks [p. 106]
Riccó, B.: 3dID: A Low-Power, Low-Cost Hand Motion Capture Device [p. 136]
Richter, K.: How OEMs and Suppliers Can Face the Network Integration Challenges [p. 183]
Risaliti, G.: On the Verification of Automotive Protocols [p. 195]
Rivera, F.: Design and Implementation of a Rendering Algorithm in a SIMD Reconfigurable Architecture (MorphoSys) [p. 52]
Roncella, R.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Rosenstiel, W.: Flexible Specification and Application of Rule-Based Transformations in an Automotive Design Flow [p. 82]; Automatic SystemC Design Configuration for a Faster Evaluation of Different Partitioning Alternatives [p. 217]

Saia, G.: ASIP Architecture for Multi-Standard Wireless Terminals [p. 118]
Saletti, R.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Sama, M.: 3dID: A Low-Power, Low-Cost Hand Motion Capture Device [p. 136]
Sanchez, J. M.: Design and Implementation of a Rendering Algorithm in a SIMD Reconfigurable Architecture (MorphoSys) [p. 52]
Sanchez-Elez, M.: Design and Implementation of a Rendering Algorithm in a SIMD Reconfigurable Architecture (MorphoSys) [p. 52]
Saponara, S.: Mixed-Signal Design of a Digital Input Power Amplifier for Automotive Audio Applications [p. 212]; ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Sautter, R.: The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor [p. 244]
Scheppler, M.: Automated Conversion from LUT-Based FPGA to a LUT-Based MPGA with Fast Turnaround Time [p. 36]
Schleibusch, O.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Schleicher, J.: A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]
Schrems, M.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Serafini, L.: Multi-Sensor Configurable Platform for Automotive Applications [p. 219] Serventi, R.; FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Silva, Jr., E. T.: A Practical Implementation of the Fault-Tolerant Daisy-Chain Clock Synchronization Algorithm on CAN [p. 189]
Simon, N.: Software-Friendly HW/SW Co-Simulation: An Industrial Case Study [p. 100]
Sohn, J.-H.: Design and Test of Fixed-Point Multimedia Co-Processor for Mobile Applications [p. 249]
Sportiello, L.: Software Implementation of Tate Pairing over GF(2^m) [p. 7]
Steenhof, F.: Networks on Chips for High-End Consumer-Electronics TV System Architectures [p. 148]
Sterpone, L.: A New Approach to Compress the Configuration Information of Programmable Devices [p. 48]
Strik, M.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]

Tahar, S.: Generating Finite State Machines from SystemC [p. 76]
Tarable, A.: Interconnection Framework for High-Throughput, Flexible LDPC Decoders [p. 124]
Terreni, P.: Mixed-Signal Design of a Digital Input Power Amplifier for Automotive Audio Applications [p. 212]
Tibaldi, C.: On the Verification of Automotive Protocols [p. 195]
Turolla, M.: Modeling and Simulation of Mobile Gateways Interacting with Wireless Sensor Networks [p. 106]

Ussery, C.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]

Vacca, F.: A New Approach to Compress the Configuration Information of Programmable Devices [p. 48]; Interconnection Framework for High-Throughput, Flexible LDPC Decoders [p. 124]
Veredas, F.-J.: Automated Conversion from LUT-Based FPGA to a LUT-Based MPGA with Fast Turnaround Time [p. 36]
Vescoli, V.: FlexRay Transceiver in a 0.35 μm CMOS High-Voltage Technology [p. 201]
Violante, M.: A New Approach to Compress the Configuration Information of Programmable Devices [p. 48]

Wang, C.-C.: A 124.8Msps, 15.6mW Field-Programmable Variable-Length Codec for Multimedia Applications [p. 239]
Wang, J.-S.: An 830mW, 586kbps 1024-Bit RSA Chip Design [p. 24]; A 124.8Msps, 15.6mW Field-Programmable Variable-Length Codec for Multimedia Applications [p. 239]
Wilson, J.: Industrially Proving SPIRIT Consortium Standards for Design Chain Integration [p. 142]
Witte, E. M.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing [p. 233]
Woo, J. H.: Design and Test of Fixed-Point Multimedia Co-Processor for Mobile Applications [p. 249]

Yeh, C.: An 830mW, 586kbps 1024-Bit RSA Chip Design [p. 24]; A 124.8Msps, 15.6mW Field-Programmable Variable-Length Codec for Multimedia Applications [p. 239]
Yoo, H.-J.: Design and Test of Fixed-Point Multimedia Co-Processor for Mobile Applications [p. 249]
Yoo, J.: Design and Test of Fixed-Point Multimedia Co-Processor for Mobile Applications [p. 249]
Yuan, R.: A Methodology for FPGA to Structured-ASIC Synthesis and Verification [p. 64]

Zachmann, G.: Space-Efficient FPGA-Accelerated Collision Detection for Virtual Reality [p. 206]
Zarri, G.: On the Verification of Automotive Protocols [p. 195]
Zolesi, V.: Multi-Sensor Configurable Platform for Automotive Applications [p. 219]
Zory, J.: ASIP Architecture for Multi-Standard Wireless Terminals [p. 118]