DATE 2002 TABLE OF CONTENTS

DATE Executive Committee
Technical Program Chairs
Vendors Committee
DATE Sponsors Committee
Technical Program Committee
Reviewers
Welcome to DATE 2002
Best Paper Awards
Tutorials
Master Courses
Call for Papers DATE 2003

Plenary -- Keynote Session

On Nanoscale Integration and Gigascale Complexity in the Post .Com World [p. 12]

Hugo De Man, Professor, KU Leuven, Senior Research Fellow, IMEC, BE

Global Responsibilities in SOC Design [p. 12]

Taylor Scanlon, President & CEO, Virtual Silicon Technology, US

1A: Hot Topic -- How to Choose Semiconductor IP?

How to Choose Semiconductor IP? -- Embedded Processors [p. 14]

I. Phillips

Make Your SOC Design a Winner: Select the Right Memory IP [p. 15]

V. Ratford

How to Choose Semiconductor IP: Embedded Software [p. 16]

G. Martin

IP Day: How to Choose Semiconductor IP? [p. 17]

P. Bricaud

1B: Formal Verification of Complex Designs

Formal Verification of the Pentium 4 Floating-Point Multiplier [p. 20]

R. Kaivola and N. Narasimhan

Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer [p. 28]

M. Velev

Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units [p. 36]

P. Mishra, N. Dutt, A. Nicolau, and H. Tomiyama

A Case Study for the Verification of Complex Timed Circuits: IPCMOS [p. 44]

M. Peña, J. Cortadella, E. Pastor, and A. Smirnov

1C: Cooling Layout Arrangements

FPGA Placement by Thermodynamic Combinatorial Optimization [p. 54]

J. De Vicente, J. Lanchares, and R. Hermida

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees [p. 61]

C. Zhuang, Y. Kajitani, K. Sakanushi, and L. Jin

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG [p. 69]

J. Lin, H. Chen, and Y. Chang

1D: Defect Oriented Test

A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits [p. 78]

M. Pronath, H. Graeb, and K. Antreich

Exact Grading of Multiple Path Delay Faults [p. 84]

S. Padmanaban and S. Tragoudas

Modeling Techniques and Tests for Partial Faults in Memory Devices [p. 89]

Z. Al-Ars and A. van de Goor

A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults [p. 94]

S. Lee, B. Cobb, J. Dworak, M. Grimaila, and M. Mercer

1E: Power Analysis and Management in Networks and Processors

Low Power Error Resilient Encoding for On-Chip Data Buses [p. 102]

D. Bertozzi, L. Benini, and G. De Micheli

Managing Power Consumption in Networks on Chip [p. 110]

T. Simunic and S. Boyd

Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States [p. 117]

S. Irani, R. Gupta, and S. Shukla

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors [p. 124]

D. Ponomarev, G. Kucuk, and K. Ghose

2A: Panel -- What is the Right IP Business Model?

IP is All About Implementation and Customer Satisfaction [p. 132]

V. Essi, Jr.

2B: SAT and BDD Techniques

Using Problem Symmetry in Search Based Satisfiability Algorithms [p. 134]

E. Goldberg, M. Prasad, and R. Brayton

BerkMin: A Fast and Robust Sat-Solver [p. 142]

E. Goldberg and Y. Novikov

Dynamic Scheduling and Clustering in Symbolic Image Computation [p. 150]

G. Cabodi, P. Camurati, and S. Quer

2C: Technology and Interconnect Issues in Low Power Design

Wire Placement for Crosstalk Energy Minimization in Address Buses [p. 158]

L. Macchiarulo, E. Macii, and M. Poncino

Dynamic VTH Scaling Scheme for Active Leakage Power Reduction [p. 163]

C. Kim and K. Roy

Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]

A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau

Sizing Power/Ground Meshes for Clocking and Computing Circuit Components [p. 176]

A. Mukherjee, K. Wang, L. Chen, and M. Marek-Sadowska

2D: Advanced Mixed Signal Test

A Signature Test Framework for Rapid Production Testing of RF Circuits [p. 186]

R. Voorakaranam, S. Cherubal, and A. Chatterjee

Analog IP Testing: Diagnosis and Optimization [p. 192]

C. Guardiani, P. McNamara, L. Daldoss, S. Saxena, S. Zanella, W. Xiang, and S. Liu

A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits [p. 197]

C. Hoffmann

Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal ICs [p. 205]

Y. Lechuga, R. Mozuelos, M. Martínez, and S. Bracho

2E: Collaborative Design -- Web-Services, Infrastructure, Applications

E-Design Based on the Reuse Paradigm [p. 214]

L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, and G. Saucier

Internet-Based Collaborative Test Generation with MOSCITO [p. 221]

A. Schneider, K. Diener, E. Ivask, J. Raik, R. Ubar, P. Miklos, T. Cibáková, and E. Gramatová

A Two-Tier Distributed Electronic Design Framework [p. 227]

T. Kazmierski and N. Clayton

Embedded System Design Based On Webservices [p. 232]

A. Rettberg and W. Thronicke

2F: Panel -- Who Owns the Platform?

Who Owns the Platform? [p. 238]

3A: Embedded Tutorial -- The Need for Infrastructure IP in SoCs

IP for Embedded Robustness [p. 240]

M. Nicolaidis

Embedded Diagnosis IP [p. 242]

S. Pateras

Embedded Robustness IPs [p. 244]

E. Dupont, M. Nicolaidis, and P. Rohr

3B: Advances in Logic Synthesis

CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines [p. 248]

S. Gören and F. Ferguson

Generalized Early Evaluation in Self-Timed Circuits [p. 255]

M. Thornton, K. Fazel, R. Reese, and C. Traver

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint [p. 260]

S. Jung, K. Kim, and S. Kang

3C: Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design

A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics [p. 268]

W. Daems, G. Gielen, and W. Sansen

Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits [p. 274]

R. Popp, J. Oehmen, L. Hedrich, and E. Barke

Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices [p. 279]

P. Vanassche, G. Gielen, and W. Sansen

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification [p. 285]

M. Ciesielski, P. Kalla, Z. Zeng, and B. Rouzeyre

3D: Hot Topic -- EDA Tools for RF: Myth or Reality?

EDA Tools for RF: Myth or Reality? [p. 292]

3E: Platform-Based Design and Virtual-Component Reuse

Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs [p. 296]

T. Lee, W. Wolf, and J. Henkel

Techniques to Evolve a C++ Based System Design Language [p. 302]

R. Pasko, S. Vernalde, and P. Schaumont

A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects [p. 310]

A. Ginés, E. Peralías, A. Rueda, N. Madrid, and R. Seepold

3F2: Analogue Circuit Characterisation and Simulation

Test Structure for I_C(V_BE) Parameter Determination of Low Voltage Applications [p. 316]

W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, and V. Chowdhury

Global Optimization Applied to the Oscillator Problem [p. 322]

S. Lampe and S. Laur

4A: Panel -- MEDEA+ and ITRS Roadmaps

MEDEA+ and ITRS Roadmaps [p. 328]

4B: Asynchronous Circuits and Clock Scheduling

A Burst-Mode Oriented Back-End for the Balsa Synthesis System [p. 330]

T. Chelcea, S. Nowick, A. Bardsley, and D. Edwards

Detecting State Coding Conflicts in STGs Using Integer Programming [p. 338]

V. Khomenko, M. Koutny, and A. Yakovlev

Verifying Clock Schedules in the Presence of Cross Talk [p. 346]

S. Hassoun, E. Calvillo-Gámez, and C. Cromer

4C: Analogue and Mixed-Signal Systems

Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach [p. 352]

M. Goffioul, P. Wambacq, G. Vandersteen, and S. Donnay

Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter [p. 357]

J. Vandenbussche, E. Lauwers, K. Uyttenhove, M. Steyaert, and G. Gielen

Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip [p. 362]

R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo, and A. Rodríguez-Vázquez

4D: BIST Diagnosis and DFT

An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs [p. 368]

A. Pandey and J. Patel

Gate Level Fault Diagnosis in Scan-Based BIST [p. 376]

I. Bayraktaroglu and A. Orailoglu

An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment [p. 382]

C. Liu, K. Chakrabarty, and M. Goessel

Reducing Test Application Time Through Test Data Mutation Encoding [p. 387]

S. Reda and A. Orailoglu

4E: Code and Memory Optimization in Co-Design

Hardware/Software Trade-Offs for Advanced 3G Channel Coding [p. 396]

H. Michel, A. Worm, N. Wehn, and M. Münch

An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs [p. 402]

A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau

Assigning Program and Data Objects to Scratchpad for Energy Reduction [p. 409]

S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel

5A: Hot Topic -- Network on a Chip

Networks on Chip: A New Paradigm for Systems on Chip Design [p. 418]

G. De Micheli and L. Benini

Communication Mechanisms for Parallel DSP Systems on a Chip [p. 420]

J. Williams, N. Heintze, and B. Ackland

Networks on Silicon: Combining Best-Effort and Guaranteed Services [p. 423]

K. Goossens, P. Wielage, A. Peeters, and J. van Meerbergen

5B: Low Power Architectures and Software

Data Reuse Exploration Techniques for Loop-Dominated Applications [p. 428]

T. Van Achteren, G. Deconinck, F. Catthoor, and R. Lauwereins

EAC: A Compiler Framework for High-Level Energy Estimation and Optimization [p. 436]

I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. Irwin, and A. Sivasubramaniam

Power Savings in Embedded Processors through Decode Filer Cache [p. 443]

W. Tang, R. Gupta, and A. Nicolau

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors [p. 449]

L. Benini, D. Bruni, A. Macii, and E. Macii

5C: Nitty Gritty Details of Layout Design

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model [p. 456]

M. Becer, V. Zolotov, D. Blaauw, R. Panda, and I. Hajj

Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits [p. 464]

G. Jerke and J. Lienig

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem [p. 470]

L. Huang, X. Tang, H. Xiang, D. Wong, and I. Liu

5D: SoC and System Test

Test Planning and Design Space Exploration in a Core-Based Environment [p. 478]

E. Cota, L. Carro, M. Lubaszewski, and A. Orailoglu

A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]

J. Li, H. Huang, J. Chen, C. Su, C. Wu, C. Cheng, S. Chen, C. Hwang, and H. Lin

Efficient Wrapper/TAM Co-Optimization for Large SOCs [p. 491]

V. Iyengar, K. Chakrabarty, E. Marinissen

Beyond UML to an End-of-Line Functional Test Engine [p. 499]

A. Baldini, A. Benso, P. Prinetto, S. Mo, and A. Taddei

5E: Modelling and Synthesis of Embedded Systems

Event Model Interfaces for Heterogeneous System Analysis [p. 506]

K. Richter and R. Ernst

Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems [p. 514]

M. Schmitz, B. Al-Hashimi, and P. Eles

A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems [p. 522]

J. Paul and D. Thomas

Automatic Evaluation of the Accuracy of Fixed-Point Algorithms [p. 529]

D. Menard and O. Sentieys

6A: Panel -- Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs

Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs [p. 538]

6B: Reconfigurable Architectures

A Video Compression Case Study on a Reconfigurable VLIW Architecture [p. 540]

D. Rizzo and O. Colavin

A Complete Data Scheduler for Multi-Context Reconfigurable Architectures [p. 547]

M. Sánchez-Élez, M. FŽrnandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. Kurdahi

Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]

G. Sassatelli, L. Torres, P. Benoit, T. Gil, C. Diou, G. Cambon, and J. Galy

(Self-)reconfigurable Finite State Machines: Theory and Implementation [p. 559]

J. Teich and M. Köster

6C: Analogue Modelling, Layout and Sizing

A Linear-Centric Simulation Framework for Parametric Fluctuations [p. 568]

E. Acar, S. Nassif, and L. Pileggi

Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio [p. 576]

M. Dessouky and D. Sayed

Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets [p. 581]

R. Schwencker, F. Schenkel, M. Pronath, and H. Graeb

High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions [p. 586]

G. Vandersteen, P. Wambacq, S. Donnay, and F. Verbeyst

6D: Test Resource Partitioning for Embedded Cores

Effective Software Self-Test Methodology for Processor Cores [p. 592]

N. Kranitis, A. Paschalis, D. Gizopoulos, and Y. Zorian

Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression [p. 598]

A. Chandra and K. Chakrabarty

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression [p. 604]

P. Gonciari, B. Al-Hashimi, and N. Nicolici

Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths [p. 612]

M. Favalli and C. Metra

6E: System Level Simulation and Modelling

Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design [p. 620]

S. Yoo, G. Nicolescu, L. Gauthier, and A. Jerraya

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses [p. 628]

Z. Zheng, L. Pileggi, M. Beattie, and B. Krauter

A Linear-Centric Modeling Approach to Harmonic Balance Analysis [p. 634]

P. Li and L. Pileggi

An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor [p. 640]

P. Pénzes and A. Martin

6F: Hot Topic -- Deep Submicron Design and Timing Closure

Design Automation for Deepsubmicron: Present and Future [p. 650]

7A: Panel -- Reconfigurable SoC -- What Will it Look Like?

Reconfigurable SoC . What Will it Look Like? [p. 660]

7B: Layout Aware Logic Synthesis

Congestion-Aware Logic Synthesis [p. 664]

D. Pandini, L. Pileggi, and A. Strojwas

Layout Driven Decomposition with Congestion Consideration [p. 672]

T. Kutzschebauch and L. Stok

Improving Placement under the Constant Delay Model [p. 677]

K. Sulimma, W. Kunz, I. Neumann, and L. van Ginneken

Crosstalk Alleviation for Dynamic PLAs [p. 683]

T. Tien, T. Tsai, and S. Chang

7C: Buffering and Tapering

Flip-Flop and Repeater Insertion for Early Interconnect Planning [p. 690]

R. Lu, G. Zhong, C. Koh, and K. Chao

Congestion Estimation with Buffer Planning in Floorplan Design [p. 696]

W. Wong, C. Sham, and F. Young

Maze Routing with Buffer Insertion under Transition Time Constraints [p. 702]

L. Huang, M. Lai, D. Wong, and Y. Gao

Optimal Transistor Tapering for High-Speed CMOS Circuits [p. 708]

L. Ding and P. Mazumder

7D: Automatic Design Debug and TPG

Incremental Diagnosis and Correction of Multiple Faults and Errors [p. 716]

A. Veneris, J. Liu, M. Amiri, and M. Abadir

Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults [p. 722]

I. Pomeranz and S. Reddy

FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis [p. 730]

V. Vedula and J. Abraham

7E: Object Oriented System Specification and Design

An Environment for Dynamic Component Composition for Efficient Co-Design [p. 736]

F. Doucet, S. Shukla, R. Gupta, and M. Otsuka

Functional Verification for SystemC Descriptions Using Constraint Solving [p. 744]

F. Ferrandi, M. Rendine, and D. Sciuto

The Modelling of Embedded Systems Using HASoC [p. 752]

M. Edwards and P. Green

A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems [p. 760]

A. Dobol and R. Vemuri

8A: Hot Topic -- UML: Using the Unified Modeling Language for Embedded System Specification

The Real-Time UML Standard: Definition and Application [p. 770]

B. Selic

UML for Embedded Systems Specification and Design: Motivation and Overview [p. 773]

G. Martin

A UML-Based Design Methodology for Real-Time and Embedded Systems [p. 776]

G. de Jong

8B: Real-Time Embedded Systems

Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor [p. 782]

G. Quan and X. Hu

A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis [p. 788]

W. Kim, J. Kim, and S. Min

Extending Synchronous Languages for Generating Abstract Real-Time Models [p. 795]

G. Logothetis and K. Schneider

8C: Interconnect Modelling

An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]

D. Goren, M. Zelikson, T. Galambos, R. Gordin, B. Livshitz, A. Amir, A. Sherman, and I. Wagner

Closed-Form Crosstalk Noise Metrics for Physical Design Applications [p. 812]

L. Chen and M. Marek-Sadowska

Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects [p. 820]

Q. Xu and P. Mazumder

Library Compatible Ceff for Gate-Level Timing [p. 826]

B. Sheehan

8D: On-Line Testing and Fault Tolerance

Self-Checking Scheme for the On-Line Testing of Power Supply Noise [p. 832]

C. Metra, L. Schiano, B. Riccò, and M. Favalli

Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance [p. 837]

R. Leveugle

Exploiting Idle Cycles for Algorithm Level Re-Computing [p. 842]

K. Wu and R. Karri

New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]

L. Berrojo, I. Gónzález, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, and C. López

8E: Design Space Evaluation

System Design for Flexibility [p. 854]

C. Haubelt, J. Teich, K. Richter, and R. Ernst

Accurate Area and Delay Estimators for FPGAs [p. 862]

A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee

A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering [p. 870]

K. Buchenrieder, A. Pyttel, and A. Sedlmeier

Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation [p. 875]

N. Savoiu, S. Shukla, and R. Gupta

9A: Hot Topic -- From System Specification to Layout: Seamless Top-Down Design Methods for Analogue and Mixed Signal Applications

From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]

R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Maloberti, K. Einwich, C. Clauss, P. Schwarz, and G. Noessing

9B: Architectural Level Synthesis

Memory System Connectivity Exploration [p. 894]

P. Grun, N. Dutt, and A. Nicolau

Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory [p. 902]

S. Hettiaratchi, P. Cheung, and T. Clarke

Multiple-Precision Circuits Allocation Independent of Data-Objects Length [p. 909]

M. Molina, J. Mendias, and R. Hermida

9C: Advanced Linear Modelling Techniques

Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function [p. 916]

E. Gad and M. Nakhla

Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation [p. 923]

C. Coelho, L. Silveira, and J. Phillips

Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods [p. 931]

Y. Chen, V. Balakrishnan, C. Koh, and K. Roy

9D: Memory Testing and ATPG Issues

An Optimal Algorithm for the Automatic Generation of March Tests [p. 938]

A. Benso, S. Di Carlo, G. Di Natale, and P. Prinetto

Minimal Test for Coupling Faults in Word-Oriented Memories [p. 944]

A. van de Goor, M. Abadir, and A. Carlin

Maximizing Impossibilities for Untestable Fault Identification [p. 949]

M. Hsiao

Automated Modeling of Custom Digital Circuits for Test [p. 954]

S. Bose

9E: Embedded Software Performance Analysis and Optimization

False Path Elimination in Quasi-Static Scheduling [p. 964]

G. Arrigoni, L. Duchini, C. Passerone, L. Lavagno, and Y. Watanabe

A Data Analysis Method for Software Performance Prediction [p. 971]

G. Bontempi and W. Kruijtzer

A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications [p. 977]

N. Liveris, N. Zervas, D. Soudris, and C. Goutis

A Compiler-Based Approach for Improving Intra-Iteration Data Reuse [p. 984]

M. Kandemir

9G: Technical Plenary -- 40 Years of EDA

European CAD from the 60's to the New Millenium [p. 992]

Joseph Borel, J.B.-R&D Consulting, FR

10A: Hot Topic -- Design Technology for Networked Reconfigurable FPGA Platforms

Design Technology for Networked Reconfigurable FPGA Platforms [p. 994]

S. Guccione, D. Verkest, and I. Bolsens

10B: High-Level Synthesis and Asynchronous Pipelines

High-Speed Non-Linear Asynchronous Pipelines [p. 1000]

R. Ozdag, P. Beerel, M. Singh, and S. Nowick

Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding [p. 1008]

M. Ferretti and P. Beerel

Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis [p. 1016]

C. Chen and M. Sarrafzadeh

Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models [p. 1021]

Q. Zhao, B. Mesman, and T. Basten

10C: Coupling and Switching Noise Modelling within Integrated Circuits

Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network [p. 1028]

T. Brandtner and R. Weigel

Fast Method to Include Parasitic Coupling in Circuit Simulations [p. 1033]

B. Van Thielen and G. Vandenbosch

Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling [p. 1038]

L. Ding and P. Mazumder

Macromodeling of Digital I/O Ports for System EMC Assessment [p. 1044]

I. Stievano, F. Canavero, I. Maio, Z. Chen, D. Becker, and G. Katopis

10D: Panel -- Formal Verification Techniques: Industrial Status and Perspectives

Formal Verification Techniques: Industrial Status and Perspectives [p. 1050]

10E: Power Optimization for Embedded Processors

Low Power Embedded Software Optimization Using Symbolic Algebra [p. 1052]

A. Peymandoust, T. Simunic, and G. De Micheli

An Adaptive Dictionary Encoding Scheme for SOC Data Buses [p. 1059]

T. Lv, W. Wolf, J. Henkel, and H. Lekatsas

Power Efficient Embedded Processor IP's through Application-Specific Tag Compression in Data Caches [p. 1065]

P. Petrov and A. Orailoglu

Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities [p. 1072]

M. Palkovic, M. Miranda, and F. Catthoor

Poster Sessions

An Approach to Model Checking for Nonlinear Analog Systems [p. 1080]

W. Hartong, L. Hedrich, and E. Barke

Speeding up SAT for EDA [p. 1081]

S. Pilarski and G. Hu

Search-Based SAT Using Zero-Suppressed BDDs [p. 1082]

F. Aloul, M. Mneimneh, and K. Sakallah

An Encoding Technique for Low Power CMOS Implementations of Controllers [p. 1083]

M. Martínez, M. Avedillo, J. Quintana, M. Koegst, S. Rülke, and H. Süße

Composition Trees in Finding Best Variable Orderings for ROBDDs [p. 1084]

E. Dubrova

A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs [p. 1085]

J. Abke and E. Barke

Concurrent and Selective Logic Extraction with Timing Consideration [p. 1086]

P. Rezvani and M. Pedram

Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions [p. 1087]

D. Kania

Efficient and Effective Redundancy Removal for Million-Gate Circuits [p. 1088]

M. Berkelaar and K. van Eijk

Visualization of Partial Order Models in VLSI Design Flow [p. 1089]

A. Bystrov, M. Koutny, and A. Yakovlev

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems [p. 1090]

J. Rigaud, L. Fesquet, M. Renaudin, and J. Quartana

Power-Efficient Trace Caches [p. 1091]

J. Hu, N. Vijaykrishnan, M. Kandemir, and M. Irwin

Reducing Cache Access Energy in Array-Intensive Applications [p. 1092]

M. Kandemir and I. Kolcu

The Use of Runtime Configuration Capabilities for Networked Embedded Systems [p. 1093]

C. Nitsch and U. Kebschull

A SAT Solver Using Software and Reconfigurable Hardware [p. 1094]

I. Skliarova and A. Ferrari

A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems [p. 1095]

R. Münzenberger, M. Dörfel, F. Slomka, and R. Hofmann

Improved Constraints for Multiprocessor System Scheduling [p. 1096]

M. Grajcar and W. Grass

A Fast Johnson-Mobius Encoding Scheme for Fault Secure Binary Counters

K.S. Papadomanolakis, A.P. Kakarountas, N. Sklavos and C.E. Goutis

Maximizing Conditional Reuse by Pre-Synthesis Transformations [p. 1097]

O. Penalba, J. Mendias, and R. Hermida

Control Circuit Templates for Asynchronous Bundled-Data Pipelines [p. 1098]

S. Tugsinavisut and P. Beerel

Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures [p. 1099]

O. Peyran and W. Zhuang

A New Formulation for SOC Floorplan Area Minimization Problem [p. 1100]

C. Lee, Y. Lin, W. Fu, C. Chang, and T. Hsieh

Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design [p. 1101]

C. Chu and F. Young

EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses [p. 1102]

Y. Aghaghiri, M. Pedram, and F. Fallah

Estimation of Power Consumption in Encoded Data Buses [p. 1103]

A. Garcia, L. Kabulepa, and M. Glesner

Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis [p. 1104]

T. Hieu

Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques [p. 1105]

A. Luchetta, S. Manetti, and M. Piccirilli

The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits [p. 1106]

M. Stan and A. Panigrahi

Substrate Parasitic Extraction for RF Integrated Circuits [p. 1107]

A. Cathelin, D. Saias, D. Belot, Y. Leclercq, and F. Clement

A Complete Phase-Locked Loop Power Consumption Model [p. 1108]

D. Duarte, N. Vijaykrishnan, and M. Irwin

Statistical Timing Driven Partitioning for VLSI Circuits [p. 1109]

C. Ababei and K. Bazargan

DAISY-CT: A High-Level Simulation Tool for Continuous-Time DeltaSigma Modulators [p. 1110]

K. Francken, M. Vogels, E. Martens, and G. Gielen

Automated Optimal Design of Switched-Capacitor Filters [p. 1111]

A. Hassibi and M. Hershenson

On-Chip Inductance Models: 3D or Not 3D? [p. 1112]

T. Lin, M. Beattie, and L. Pileggi

Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate [p. 1113]

H. Ymeri, B. Nauwelaers, K. Maex, D. De Roest, M. Stucchi, and S. Vandenbergheo

Compact Macromodel for Lossy Coupled Transmission Lines [p. 1114]

R. Khazaka and M. Nakhla

An EMC-Compliant Design Method of High-Density Integrated Circuits [p. 1115]

J. Levant and M. Ramdani

Finding a Common Fault Response for Diagnosis during Silicon Debug [p. 1116]

I. Pomeranz, J. Rajski, and S. Reddy

I_DDT Testing of Embedded CMOS SRAMs [p. 1117]

S. Kumar, R. Makki, and D. Binkley

Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis [p. 1118]

S. Bhunia and K. Roy

An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits [p. 1119]

J. Lin, C. Lee, and J. Chen

On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems [p. 1120]

V. Beroulle, Y. Bertrand, L. Latorre, and P. Nouet

Directed-Binary Search in Logic BIST Diagnostics [p. 1121]

R. Kapur, T. Williams, M. Mercer

An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators [p. 1122]

M. Favalli and M. Dalpasso

Fault Isolation Using Tests for Non-Isolated Blocks [p. 1123]

I. Pomeranz and Y. Zorian

A Heuristic for Test Scheduling at System Level [p. 1124]

M. Flottes, J. Pouget, and B. Rouzeyre

Formulation of SOC Test Scheduling as a Network Transportation Problem [p. 1125]

S. Koranne and V. Choudhary

A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs [p. 1126]

M. Gericota, G. Alves, M. Silva, and J. Ferreira

Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider [p. 1127]

A. Drozd, M. Lobachev, and J. Drozd

An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores [p. 1128]

A. Bona, M. Sami, D. Sciuto, V. Zaccaria, C. Silvano, and R. Zafalon

The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines [p. 1129]

A. Sauer, G. Elst, L. Krahn, and W. John

Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments [p. 1130]

L. Indrusiak, M. Glesner, and R. Reis

FlexBench: Reuse of Verification IP to Increase Productivity [p. 1131]

S. Stöhr, M. Simmons, and J. Geishauser

Mappability Estimation of Architecture and Algorithm [p. 1132]

J. Soininen, J. Kreku, and Y. Qu

Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS [p. 1133]

P. Wilson, J. Ross, M. Zwolinski, A. Brown, and Y. Kiliç

A Parallel LCC Simulation System [p. 1134]

K. Hering

Error Simulation Based on the SystemC Design Description Language [p. 1135]

F. Bruschi, M. Chiamenti, F. Ferrandi, and D. Sciuto

Towards a Kernel Language for Heterogeneous Computing [p. 1136]

D. Björklund and J. Lilius

Top-Down System Level Design Methodology Using SpecC, VCC and SystemC [p. 1137]

L. Cai, D. Gajski, P. Kritzinger, and M. Olivares

Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors [p. 1138]

L. Pozzi, M. Vuletic, and P. Ienne

Steady State Calculation of Oscillators Using Continuation Methods [p. 1139]

H. Brachtendorf, S. Lampe, R. Laur, R. Melville, and P. Feldmann