DATE 2004 DESIGNERS' FORUM, TABLE OF CONTENTS

Designers' Forum Committee
Call for Papers DATE 2005

2D: Hot Topic -- From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions

Systems on Chips Design: System Manufacturer Point of View [p. 3]

V. Loukusa, H. Pohjonen, A. Ruha, T. Ruotsalainen, and O. Varkki

Package Design for High Performance ICs [p. 5]

S. Dandia

IP Testing -- The Future Differentiator? [p. 6]

B. Eklow

3D: Analogue and RF Design

Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs [p. 10]

A. Júnior and L. Carro

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems' Application to High-Speed CMOS Photoreceiver Front-Ends [p. 16]

F. Tissafi-Drissi, I. O'Connor, and F. Gaffiot

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]

Y. Chen, X. Yuan, D. Scagnelli, J. Mecke, J. Gross, and D. Harame

Low Power Analogue 90 Degree Phase Shifter [p. 28]

P. Saul

A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications [p. 34]

P. Horský

An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain [p. 39]

S. Bantas, Y. Koutsoyannopoulos, and A. Liapis

4D: Platform and IP Design

A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core [p. 46]

A. Wortmann, M. Müller, and S. Simon

Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]

A. Panato, S. Silva, F. Wagner, M. Johann, R. Reis, and S. Bampi

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding [p. 58]

P. Paulin, C. Pilkington, E. Bensoudane, M. Langevin, and D. Lyonnard

Islands of Synchronicity, A Design Methodology for SoC Design [p. 64]

A. Niranjan and P. Wiscombe

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) [p. 70]

L. Dadda, M, Macchetti, and J. Owen

LZW-Based Code Compression for VLIW Embedded Systems [p. 76]

C. Lin, W. Wolf, and Y. Xie

A Generic RTOS Model for Real-Time Systems Simulation with SystemC [p. 82]

R. Le Moigne, O. Pasquier, and J. Calvez

A Scalable Architecture for LDPC Decoding [p. 88]

M. Cocco, J. Huisken, J. Dielissen, M. Heijligers, and A. Hekstra

5D: Design Verification and Test

Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments [p. 96]

S. Schmitt and W. Rosenstiel

Formal Refinement and Model Checking of an Echo Cancellation Unit [p. 102]

A. Krupp, W. Mueller, and I. Oliver

Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip [p. 108]

S. Goel, E. Marinissen, K. Chiu, T. Nguyen, and S. Oostdijk

Have I Really Met Timing? Validating Primetime Timing Reports with SPICE [p. 114]

T. Thiel

At Speed Testing of SOC ICs [p. 120]

V. Vorisek, T. Koch, and H. Fischer

Utilizing Formal Assertions for System Design of Network Processors [p. 126]

X Chen, Y. Luo, H. Hsieh, L. Bhuyan, and F. Balarin

6D: Design Methodology

Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit [p. 134]

J. Diaz and M. Saburit

Expert System Perimeter Block Placement Floorplanning [p. 140]

R. Auletta

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses [p. 144]

I. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, and H. Smith

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

J. Ruiz-Amaya, J. De La Rosa, F. Medeiro, F. Fernández, R. Del Río, B. Pérez-Verd&uacte;, and A. Rodríguez-Vázquez

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

O. Schliebusch, A. Chattopadhyay, R. Leupers, G. Ascheid, H. Meyr, M. Steinert, G. Braun, and A. Nohl

Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems [p. 161]

A. Varma and S. Bhattacharyya

7D: Network Design

Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]

F. Fummi, S. Martini, G. Perbellini, M. Poncino, F. Ricciato, and M. Turolla

OCCN A Network-on-Chip Modeling and Simulation Framework [p. 174]

M. Coppola, S. Curaba, G. Maruccia, F. Papariello, and M. Grammatikakis

A Design Methodology for the Exploitation of High Level Communication Synthesis [p. 180]

F. Bruschi and M. Bombana

Software Processing Performance in Network Processors [p. 186]

I. Papaefstathiou, G. Kornaros, and N. Zervos

Channel Decoder Architecture for 3G Mobile Wireless Terminals [p. 192]

F. Berens, G. Kreiselmaier, and N. Wehn

RASoC: A Router Soft-Core for Networks-on-Chip [p. 198]

C. Zeferino, E. Kreutz, and A. Susin

8D: Reconfigurable Architecture

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware [p. 206]

A. Cilardo, A. Mazzeo, L. Romano, and G. Saggese

Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA [p. 212]

M. Saeb and H. Farouk

NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices [p. 218]

D. Ferrer, R. González, R. Fleitas, R. Canetti, and J. Pérez

Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation [p. 224]

R. Porto and L. Agostini

A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver [p. 230]

M. Quax, J. Huisken, and J. van Meerbergen

Customisable EPIC Processor: Architecture and Tools [p. 236]

W. Chu, R. Dimond, S. Perrott, S. Seng, and W. Luk

A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications [p. 242]

M. Boschetti, I. Silva, and S. Bampi

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks [p. 248]

D. Lettnin, A. Braun, M. Bodgan, J. Gerlach, and W. Rosenstiel

9D: Constrained and Domain Specific Architectures

Experiences during the Experimental Validation of the Time-Triggered Architecture [p. 256]

S. Blanc, J. Gracia, and P. Gil

Evaluation of a Refinement-Driven SystemC™-Based Design Flow [p. 262]

T. Schubert, J. Appell, W. Nebel, J. Hanisch, and J. Gerlach

Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications [p. 268]

N. Bannow and K. Haug

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip [p. 274]

W. Bainbridge, L. Plana, and S. Furber

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]

B. Ren, A. Wang, J. Bakshi, K. Liu, W. Li, and W. Dai

Qualification and Integration of Complex I/O in SoC Design Flows [p. 286]

J. Abraham and G. Rao

10D: Low Power Design

A Power Optimized Display Memory Organization for Handheld User Terminals [p. 294]

L. Hollevoet, A. Dewilde, K. Denolf, F. Catthoor, and F. Louagie

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]

U. Neffe, K. Rothbart, C. Steger, R. Weiss, E. Rieger, and A. Mühlberger

Analysis and Modeling of Energy Reducing Source Code Transformations [p. 306]

C. Brandolese, W. Fornaciari, F. Salice, and D. Sciuto

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design [p. 312]

L. Benini, L. Bisdounis, G. Donno, F. Menichelli, and M. Olivieri

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip [p. 318]

A. Bona, V. Zaccaria, and R. Zafalon

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling [p. 324]

K. Flautner, D. Flynn, D. Roberts, and D. Patel

Interactive Presentations

Can IP Quality be Objectively Measured? [p. 330]

K. Werner

Improving Design and Verification Productivity with VHDL-200x [p. 332]

S. Bailey, E. Marschner, J. Lewis, J. Bhasker, and P. Ashenden

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components [p. 336]

P. Daglio, D. Iezzi, D. Rimondi, C. Roma, and S. Santapa

VHDL-AMS Library Development for Pacemaker Applications [p. 338]

B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, and J. Oudinot

Modeling and Analysis of Heterogeneous Industrial Networks Architectures [p. 342]

F. Fummi, M. Poncino, S. Martini, G. Perbellini, and M. Monguzzi