Sessions: [2D] [3D] [4D] [5D] [6D] [7D] [8D] [9D] [10D] [Interactive Presentations]

Designers' Forum Committee
Call for Papers DATE 2005

2D: Hot Topic -- From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions

Organizers/Moderators: F. Muradali, Agilent Technologies, US; R. Aitken, Artisan Components, US [p. 2]

PDF icon Systems on Chips Design: System Manufacturer Point of View [p. 3]
V. Loukusa, H. Pohjonen, A. Ruha, T. Ruotsalainen, and O. Varkki

PDF icon Package Design for High Performance ICs [p. 5]
S. Dandia

PDF icon IP Testing -- The Future Differentiator? [p. 6]
B. Eklow

3D: Analogue and RF Design

Moderators: D. Appello, STM Test Solutions Group, IT; C. Das, IMEC, BE
PDF icon Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs [p. 10]
A. Júnior and L. Carro

PDF icon RUNE: Platform for Automated Design of Integrated Multi-Domain Systems' Application to High-Speed CMOS Photoreceiver Front-Ends [p. 16]
F. Tissafi-Drissi, I. O'Connor, and F. Gaffiot

PDF icon Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]
Y. Chen, X. Yuan, D. Scagnelli, J. Mecke, J. Gross, and D. Harame

PDF icon Low Power Analogue 90 Degree Phase Shifter [p. 28]
P. Saul

PDF icon A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications [p. 34]
P. Horský

PDF icon An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain [p. 39]
S. Bantas, Y. Koutsoyannopoulos, and A. Liapis

4D: Platform and IP Design

Moderators: K. Currie, Philips Semiconductors, NL; L. Torres, LIRMM, FR
PDF icon A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core [p. 46]
A. Wortmann, M. Müller, and S. Simon

PDF icon Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]
A. Panato, S. Silva, F. Wagner, M. Johann, R. Reis, and S. Bampi

PDF icon Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding [p. 58]
P. Paulin, C. Pilkington, E. Bensoudane, M. Langevin, and D. Lyonnard

PDF icon Islands of Synchronicity, A Design Methodology for SoC Design [p. 64]
A. Niranjan and P. Wiscombe

PDF icon The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) [p. 70]
L. Dadda, M, Macchetti, and J. Owen

PDF icon LZW-Based Code Compression for VLIW Embedded Systems [p. 76]
C. Lin, W. Wolf, and Y. Xie

PDF icon A Generic RTOS Model for Real-Time Systems Simulation with SystemC [p. 82]
R. Le Moigne, O. Pasquier, and J. Calvez

PDF icon A Scalable Architecture for LDPC Decoding [p. 88]
M. Cocco, J. Huisken, J. Dielissen, M. Heijligers, and A. Hekstra

5D: Design Verification and Test

Moderators: F. Fummi, Verona U, IT; A. Fedeli, STMicroelectronics, IT
PDF icon Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments [p. 96]
S. Schmitt and W. Rosenstiel

PDF icon Formal Refinement and Model Checking of an Echo Cancellation Unit [p. 102]
A. Krupp, W. Mueller, and I. Oliver

PDF icon Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip [p. 108]
S. Goel, E. Marinissen, K. Chiu, T. Nguyen, and S. Oostdijk

PDF icon Have I Really Met Timing? Validating Primetime Timing Reports with SPICE [p. 114]
T. Thiel

PDF icon At Speed Testing of SOC ICs [p. 120]
V. Vorisek, T. Koch, and H. Fischer

PDF icon Utilizing Formal Assertions for System Design of Network Processors [p. 126]
X Chen, Y. Luo, H. Hsieh, L. Bhuyan, and F. Balarin

6D: Design Methodology

Moderators: V. Gerousis, Infineon Technologies, DE; D. Bailey, Mentor Graphics, US
PDF icon Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit [p. 134]
J. Diaz and M. Saburit

PDF icon Expert System Perimeter Block Placement Floorplanning [p. 140]
R. Auletta

PDF icon A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses [p. 144]
I. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, and H. Smith

PDF icon MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]
J. Ruiz-Amaya, J. De La Rosa, F. Medeiro, F. Fernández, R. Del Río, B. Pérez-Verd&uacte;, and A. Rodríguez-Vázquez

PDF icon RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]
O. Schliebusch, A. Chattopadhyay, R. Leupers, G. Ascheid, H. Meyr, M. Steinert, G. Braun, and A. Nohl

PDF icon Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems [p. 161]
A. Varma and S. Bhattacharyya

7D: Network Design

Moderators: M. Turolla, Telecom Italia, IT; K. Goossens, Philips Research, NL
PDF icon Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]
F. Fummi, S. Martini, G. Perbellini, M. Poncino, F. Ricciato, and M. Turolla

PDF icon OCCN A Network-on-Chip Modeling and Simulation Framework [p. 174]
M. Coppola, S. Curaba, G. Maruccia, F. Papariello, and M. Grammatikakis

PDF icon A Design Methodology for the Exploitation of High Level Communication Synthesis [p. 180]
F. Bruschi and M. Bombana

PDF icon Software Processing Performance in Network Processors [p. 186]
I. Papaefstathiou, G. Kornaros, and N. Zervos

PDF icon Channel Decoder Architecture for 3G Mobile Wireless Terminals [p. 192]
F. Berens, G. Kreiselmaier, and N. Wehn

PDF icon RASoC: A Router Soft-Core for Networks-on-Chip [p. 198]
C. Zeferino, E. Kreutz, and A. Susin

8D: Reconfigurable Architecture

Moderators: M. Lindwer, Philips Silicon Hive, NL; P. Pezzati, Cadence, FR
PDF icon Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware [p. 206]
A. Cilardo, A. Mazzeo, L. Romano, and G. Saggese

PDF icon Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA [p. 212]
M. Saeb and H. Farouk

PDF icon NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices [p. 218]
D. Ferrer, R. González, R. Fleitas, R. Canetti, and J. Pérez

PDF icon Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation [p. 224]
R. Porto and L. Agostini

PDF icon A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver [p. 230]
M. Quax, J. Huisken, and J. van Meerbergen

PDF icon Customisable EPIC Processor: Architecture and Tools [p. 236]
W. Chu, R. Dimond, S. Perrott, S. Seng, and W. Luk

PDF icon A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications [p. 242]
M. Boschetti, I. Silva, and S. Bampi

PDF icon Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks [p. 248]
D. Lettnin, A. Braun, M. Bodgan, J. Gerlach, and W. Rosenstiel

9D: Constrained and Domain Specific Architectures

Moderators: J. Gerlach, Robert Bosch GmbH, DE; M. Lindwer, Philips Silicon Hive, NL
PDF icon Experiences during the Experimental Validation of the Time-Triggered Architecture [p. 256]
S. Blanc, J. Gracia, and P. Gil

PDF icon Evaluation of a Refinement-Driven SystemC™-Based Design Flow [p. 262]
T. Schubert, J. Appell, W. Nebel, J. Hanisch, and J. Gerlach

PDF icon Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications [p. 268]
N. Bannow and K. Haug

PDF icon The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip [p. 274]
W. Bainbridge, L. Plana, and S. Furber

PDF icon A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]
B. Ren, A. Wang, J. Bakshi, K. Liu, W. Li, and W. Dai

PDF icon Qualification and Integration of Complex I/O in SoC Design Flows [p. 286]
J. Abraham and G. Rao

10D: Low Power Design

Moderators: W. Luk, Imperial College, UK; V. Gerousis, Infineon Technologies, DE
PDF icon A Power Optimized Display Memory Organization for Handheld User Terminals [p. 294]
L. Hollevoet, A. Dewilde, K. Denolf, F. Catthoor, and F. Louagie

PDF icon Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]
U. Neffe, K. Rothbart, C. Steger, R. Weiss, E. Rieger, and A. Mühlberger

PDF icon Analysis and Modeling of Energy Reducing Source Code Transformations [p. 306]
C. Brandolese, W. Fornaciari, F. Salice, and D. Sciuto

PDF icon A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design [p. 312]
L. Benini, L. Bisdounis, G. Donno, F. Menichelli, and M. Olivieri

PDF icon System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip [p. 318]
A. Bona, V. Zaccaria, and R. Zafalon

PDF icon IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling [p. 324]
K. Flautner, D. Flynn, D. Roberts, and D. Patel

Interactive Presentations

PDF icon Can IP Quality be Objectively Measured? [p. 330]
K. Werner

PDF icon Improving Design and Verification Productivity with VHDL-200x [p. 332]
S. Bailey, E. Marschner, J. Lewis, J. Bhasker, and P. Ashenden

PDF icon Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components [p. 336]
P. Daglio, D. Iezzi, D. Rimondi, C. Roma, and S. Santapa

PDF icon VHDL-AMS Library Development for Pacemaker Applications [p. 338]
B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, and J. Oudinot

PDF icon Modeling and Analysis of Heterogeneous Industrial Networks Architectures [p. 342]
F. Fummi, M. Poncino, S. Martini, G. Perbellini, and M. Monguzzi