DATE 2002 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Ababei, C.
Statistical Timing Driven Partitioning for VLSI Circuits [p. 1109]
Abadir, M.
Incremental Diagnosis and Correction of Multiple Faults and Errors [p. 716]
Abadir, M.
Minimal Test for Coupling Faults in Word-Oriented Memories [p. 944]
Abke, J.
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs [p. 1085]
Abraham, J.
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis [p. 730]
Acar, E.
A Linear-Centric Simulation Framework for Parametric Fluctuations [p. 568]
Ackland, B.
Communication Mechanisms for Parallel DSP Systems on a Chip [p. 420]
Aghaghiri, Y.
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses [p. 1102]
Al-Ars, Z.
Modeling Techniques and Tests for Partial Faults in Memory Devices [p. 89]
Al-Hashimi, B.
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems [p. 514]
Aloul, F.
Search-Based SAT Using Zero-Suppressed BDDs [p. 1082]
Alves, G.
A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs [p. 1126]
Amir, A.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Amiri, M.
Incremental Diagnosis and Correction of Multiple Faults and Errors [p. 716]
Antreich, K.
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits [p. 78]
Arrigoni, G.
False Path Elimination in Quasi-Static Scheduling [p. 964]
Auvergne, D.
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications [p. 316]
Avedillo, M.
An Encoding Technique for Low Power CMOS Implementations of Controllers [p. 1083]
Azevedo, A.
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]

B

Bagherzadeh, N.
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures [p. 547]
Balakrishnan, V.
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods [p. 931]
Baldini, A.
Beyond UML to an End-of-Line Functional Test Engine [p. 499]
Banerjee, P.
Accurate Area and Delay Estimators for FPGAs [p. 862]
Bardsley, A.
A Burst-Mode Oriented Back-End for the Balsa Synthesis System [p. 330]
Barke, E.
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits [p. 274]
Barke, E.
An Approach to Model Checking for Nonlinear Analog Systems [p. 1080]
Barke, E.
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs [p. 1085]
Basten, T.
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models [p. 1021]
Bayraktaroglu, I.
Gate Level Fault Diagnosis in Scan-Based BIST [p. 376]
Bazargan, K.
Statistical Timing Driven Partitioning for VLSI Circuits [p. 1109]
Beattie, M.
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses [p. 628]
Beattie, M.
On-Chip Inductance Models: 3D or Not 3D? [p. 1112]
Becer, M.
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model [p. 456]
Becker, D.
Macromodeling of Digital I/O Ports for System EMC Assessment [p. 1044]
Beerel, P.
High-Speed Non-Linear Asynchronous Pipelines [p. 1000]
Beerel, P.
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding [p. 1008]
Beerel, P.
Control Circuit Templates for Asynchronous Bundled-Data Pipelines [p. 1098]
Belot, D.
Substrate Parasitic Extraction for RF Integrated Circuits [p. 1107]
Benini, L.
Low Power Error Resilient Encoding for On-Chip Data Buses [p. 102]
Benini, L.
Networks on Chip: A New Paradigm for Systems on Chip Design [p. 418]
Benoit, P.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]
Benso, A.
Beyond UML to an End-of-Line Functional Test Engine [p. 499]
Benso, A.
An Optimal Algorithm for the Automatic Generation of March Tests [p. 938]
Berkelaar, M.
Efficient and Effective Redundancy Removal for Million-Gate Circuits [p. 1088]
Beroulle, V.
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems [p. 1120]
Berrojo, L.
New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]
Bertozzi, D.
Low Power Error Resilient Encoding for On-Chip Data Buses [p. 102]
Bertrand, Y.
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems [p. 1120]
Bhunia, S.
Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis [p. 1118]
Binkley, D.
IDDT Testing of Embedded CMOS SRAMs [p. 1117]
Biswas, P.
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs [p. 402]
Björklund, D.
Towards a Kernel Language for Heterogeneous Computing [p. 1136]
Blaauw, D.
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model [p. 456]
Bolsens, I.
Design Technology for Networked Reconfigurable FPGA Platforms [p. 994]
Bona, A.
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores [p. 1128]
Bontempi, G.
A Data Analysis Method for Software Performance Prediction [p. 971]
Bose, S.
Automated Modeling of Custom Digital Circuits for Test [p. 954]
Boyd, S.
Managing Power Consumption in Networks on Chip [p. 110]
Bracho, S.
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal ICs [p. 205]
Brachtendorf, H.
Steady State Calculation of Oscillators Using Continuation Methods [p. 1139]
Brandtner, T.
Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network [p. 1028]
Brayton, R.
Using Problem Symmetry in Search Based Satisfiability Algorithms [p. 134]
Bricaud, P.
IP Day: How to Choose Semiconductor IP? [p. 17]
Brown, A.
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS [p. 1133]
Bruni, D.
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors [p. 449]
Bruschi, F.
Error Simulation Based on the SystemC Design Description Language [p. 1135]
Buchenrieder, K.
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering [p. 870]
Bystrov, A.
Visualization of Partial Order Models in VLSI Design Flow [p. 1089]

C

Cabodi, G.
Dynamic Scheduling and Clustering in Symbolic Image Computation [p. 150]
Cai, L.
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC [p. 1137]
Calvillo-Gámez, E.
Verifying Clock Schedules in the Presence of Cross Talk [p. 346]
Cambon, G.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]
Camurati, P.
Dynamic Scheduling and Clustering in Symbolic Image Computation [p. 150]
Canavero, F.
Macromodeling of Digital I/O Ports for System EMC Assessment [p. 1044]
Carlin, A.
Minimal Test for Coupling Faults in Word-Oriented Memories [p. 944]
Carmona, R.
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip [p. 362]
Carro, L.
Test Planning and Design Space Exploration in a Core-Based Environment [p. 478]
Cathelin, A.
Substrate Parasitic Extraction for RF Integrated Circuits [p. 1107]
Catthoor, F.
Data Reuse Exploration Techniques for Loop-Dominated Applications [p. 428]
Catthoor, F.
Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities [p. 1072]
Chakrabarty, K.
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment [p. 382]
Chakrabarty, K.
Efficient Wrapper/TAM Co-Optimization for Large SOCs [p. 491]
Chakrabarty, K.
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression [p. 598]
Chandra, A.
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression [p. 598]
Chang, C.
A New Formulation for SOC Floorplan Area Minimization Problem [p. 1100]
Chang, S.
Crosstalk Alleviation for Dynamic PLAs [p. 683]
Chang, Y.
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG [p. 69]
Chao, K.
Flip-Flop and Repeater Insertion for Early Interconnect Planning [p. 690]
Chatterjee, A.
A Signature Test Framework for Rapid Production Testing of RF Circuits [p. 186]
Chelcea, T.
A Burst-Mode Oriented Back-End for the Balsa Synthesis System [p. 330]
Chen, C.
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis [p. 1016]
Chen, H.
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG [p. 69]
Chen, J.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Chen, J.
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits [p. 1119]
Chen, L.
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components [p. 176]
Chen, L.
Closed-Form Crosstalk Noise Metrics for Physical Design Applications [p. 812]
Chen, S.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Chen, Y.
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods [p. 931]
Chen, Z.
Macromodeling of Digital I/O Ports for System EMC Assessment [p. 1044]
Cheng, C.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Cherubal, S.
A Signature Test Framework for Rapid Production Testing of RF Circuits [p. 186]
Cheung, P.
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory [p. 902]
Chiamenti, M.
Error Simulation Based on the SystemC Design Description Language [p. 1135]
Choudhary, A.
Accurate Area and Delay Estimators for FPGAs [p. 862]
Chowdhury, V.
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications [p. 316]
Choudhary, V.
Formulation of SOC Test Scheduling as a Network Transportation Problem [p. 1125]
Chu, C.
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design [p. 1101]
Cialdella, B.
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications [p. 316]
Cibáková, T.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Ciesielski, M.
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification [p. 285]
Clarke, T.
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory [p. 902]
Clauss, C.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Clayton, N.
A Two-Tier Distributed Electronic Design Framework [p. 227]
Clement, F.
Substrate Parasitic Extraction for RF Integrated Circuits [p. 1107]
Cobb, B.
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults [p. 94]
Coelho, C.
Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation [p. 923]
Colavin, O.
A Video Compression Case Study on a Reconfigurable VLIW Architecture [p. 540]
Cornea, R.
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]
Corno, F.
New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]
Cortadella, J.
A Case Study for the Verification of Complex Timed Circuits: IPCMOS [p. 44]
Cota, E.
Test Planning and Design Space Exploration in a Core-Based Environment [p. 478]
Cromer, C.
Verifying Clock Schedules in the Presence of Cross Talk [p. 346]

D

Daems, W.
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics [p. 268]
Daldoss, L.
Analog IP Testing: Diagnosis and Optimization [p. 192]
Dalpasso, M.
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators [p. 1122]
de Jong, G.
A UML-Based Design Methodology for Real-Time and Embedded Systems [p. 776]
De Micheli, G.
Low Power Error Resilient Encoding for On-Chip Data Buses [p. 102]
De Micheli, G.
Networks on Chip: A New Paradigm for Systems on Chip Design [p. 418]
De Micheli, G.
Low Power Embedded Software Optimization Using Symbolic Algebra [p. 1052]
De Roest, D.
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate [p. 1113]
De Vicente, J.
FPGA Placement by Thermodynamic Combinatorial Optimization [p. 54]
Deconinck, G.
Data Reuse Exploration Techniques for Loop-Dominated Applications [p. 428]
Dessouky, M.
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio [p. 576]
Di Carlo, S.
An Optimal Algorithm for the Automatic Generation of March Tests [p. 938]
Di Natale, G.
An Optimal Algorithm for the Automatic Generation of March Tests [p. 938]
Diener, K.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Ding, L.
Optimal Transistor Tapering for High-Speed CMOS Circuits [p. 708]
Ding, L.
Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling [p. 1038]
Diou, C.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]
Dobol, A.
A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems [p. 760]
Domínguez-Castro, R.
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip [p. 362]
Donnay, S.
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach [p. 352]
Donnay, S.
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions [p. 586]
Dörfel, M.
A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems [p. 1095]
Doucet, F.
An Environment for Dynamic Component Composition for Efficient Co-Design [p. 736]
Drozd, A.
Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider [p. 1127]
Drozd, J.
Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider [p. 1127]
Duarte, D.
A Complete Phase-Locked Loop Power Consumption Model [p. 1108]
Dubrova, E.
Composition Trees in Finding Best Variable Orderings for ROBDDs [p. 1084]
Duchini, L.
False Path Elimination in Quasi-Static Scheduling [p. 964]
Dufaza, C.
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications [p. 316]
Dupont, E.
Embedded Robustness IPs [p. 244]
Dutt, N.
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units [p. 36]
Dutt, N.
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]
Dutt, N.
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs [p. 402]
Dutt, N.
Memory System Connectivity Exploration [p. 894]
Dworak, J.
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults [p. 94]

E

Edwards, D.
A Burst-Mode Oriented Back-End for the Balsa Synthesis System [p. 330]
Edwards, M.
The Modelling of Embedded Systems Using HASoC [p. 752]
Einwich, K.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Eles, P.
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems [p. 514]
Elst, G.
The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines [p. 1129]
Entrena, L.
New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]
Ernst, R.
Event Model Interfaces for Heterogeneous System Analysis [p. 506]
Ernst, R.
System Design for Flexibility [p. 854]
Espejo, S.
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip [p. 362]
Essi, Jr., V.
IP is All About Implementation and Customer Satisfaction [p. 132]

F

Fallah, F.
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses [p. 1102]
Favalli, M.
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths [p. 612]
Favalli, M.
Self-Checking Scheme for the On-Line Testing of Power Supply Noise [p. 832]
Favalli, M.
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators [p. 1122]
Fazel, K.
Generalized Early Evaluation in Self-Timed Circuits [p. 255]
Feldmann, P.
Steady State Calculation of Oscillators Using Continuation Methods [p. 1139]
Ferguson, F.
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines [p. 248]
Férnandez, M.
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures [p. 547]
Ferrandi, F.
Functional Verification for SystemC Descriptions Using Constraint Solving [p. 744]
Ferrandi, F.
Error Simulation Based on the SystemC Design Description Language [p. 1135]
Ferrari, A.
A SAT Solver Using Software and Reconfigurable Hardware [p. 1094]
Ferreira, J.
A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs [p. 1126]
Ferretti, M.
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding [p. 1008]
Fesquet, L.
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems [p. 1090]
Flottes, M.
A Heuristic for Test Scheduling at System Level [p. 1124]
Francken, K.
DAISY-CT: A High-Level Simulation Tool for Continuous-Time DeltaSigma Modulators [p. 1110]
Fu, W.
A New Formulation for SOC Floorplan Area Minimization Problem [p. 1100]

G

Gad, E.
Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function [p. 916]
Gajski, D.
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC [p. 1137]
Galambos, T.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Galy, J.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]
Gao, Y.
Maze Routing with Buffer Insertion under Transition Time Constraints [p. 702]
Garcia, A.
Estimation of Power Consumption in Encoded Data Buses [p. 1103]
Gatti, U.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Gauthier, L.
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design [p. 620]
Geishauser, J.
FlexBench: Reuse of Verification IP to Increase Productivity [p. 1131]
Gericota, M.
A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs [p. 1126]
Ghanmi, L.
E-Design Based on the Reuse Paradigm [p. 214]
Ghose, K.
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors [p. 124]
Ghrab, A.
E-Design Based on the Reuse Paradigm [p. 214]
Gielen, G.
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics [p. 268]
Gielen, G.
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices [p. 279]
Gielen, G.
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter [p. 357]
Gielen, G.
DAISY-CT: A High-Level Simulation Tool for Continuous-Time DeltaSigma Modulators [p. 1110]
Gil, T.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]
Ginés, A.
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects [p. 310]
Gizopoulos, D.
Effective Software Self-Test Methodology for Processor Cores [p. 592]
Glesner, M.
Estimation of Power Consumption in Encoded Data Buses [p. 1103]
Glesner, M.
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments [p. 1130]
Goessel, M.
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment [p. 382]
Goffioul, M.
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach [p. 352]
Goldberg, E.
Using Problem Symmetry in Search Based Satisfiability Algorithms [p. 134]
Goldberg, E.
BerkMin: A Fast and Robust Sat-Solver [p. 142]
Gonciari, P.
Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression [p. 604]
Gónzález, I.
New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]
Goossens, K.
Networks on Silicon: Combining Best-Effort and Guaranteed Services [p. 423]
Gordin, R.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Goren, D.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Gören, S.
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines [p. 248]
Goutis, C.
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications [p. 977]
Graeb, H.
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits [p. 78]
Graeb, H.
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets [p. 581]
Grajcar, M.
Improved Constraints for Multiprocessor System Scheduling [p. 1096]
Gramatová, E.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Grass, W.
Improved Constraints for Multiprocessor System Scheduling [p. 1096]
Green, P.
The Modelling of Embedded Systems Using HASoC [p. 752]
Grimaila, M.
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults [p. 94]
Grun, P.
Memory System Connectivity Exploration [p. 894]
Guardiani, C.
Analog IP Testing: Diagnosis and Optimization [p. 192]
Guccione, S.
Design Technology for Networked Reconfigurable FPGA Platforms [p. 994]
Gupta, R.
Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States [p. 117]
Gupta, R.
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]
Gupta, R.
Power Savings in Embedded Processors through Decode Filer Cache [p. 443]
Gupta, R.
An Environment for Dynamic Component Composition for Efficient Co-Design [p. 736]

H

Hajj, I.
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model [p. 456]
Halambi, A.
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs [p. 402]
Haldar, M.
Accurate Area and Delay Estimators for FPGAs [p. 862]
Hamdoun, M.
E-Design Based on the Reuse Paradigm [p. 214]
Hartong, W.
An Approach to Model Checking for Nonlinear Analog Systems [p. 1080]
Hassibi, A.
Automated Optimal Design of Switched-Capacitor Filters [p. 1111]
Hassoun, S.
Verifying Clock Schedules in the Presence of Cross Talk [p. 346]
Haubelt, C.
System Design for Flexibility [p. 854]
Hedrich, L.
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits [p. 274]
Hedrich, L.
An Approach to Model Checking for Nonlinear Analog Systems [p. 1080]
Heintze, N.
Communication Mechanisms for Parallel DSP Systems on a Chip [p. 420]
Henkel, J.
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs [p. 296]
Henkel, J.
An Adaptive Dictionary Encoding Scheme for SOC Data Buses [p. 1059]
Hennig, E.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Hering, K.
A Parallel LCC Simulation System [p. 1134]
Hermida, R.
FPGA Placement by Thermodynamic Combinatorial Optimization [p. 54]
Hermida, R.
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures [p. 547]
Hermida, R.
Multiple-Precision Circuits Allocation Independent of Data-Objects Length [p. 909]
Hermida, R.
Maximizing Conditional Reuse by Pre-Synthesis Transformations [p. 1097]
Hershenson, M.
Automated Optimal Design of Switched-Capacitor Filters [p. 1111]
Hettiaratchi, S.
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory [p. 902]
Hieu, T.
Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis [p. 1104]
Hoffmann, C.
A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits [p. 197]
Hofmann, R.
A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems [p. 1095]
Hsiao, M.
Maximizing Impossibilities for Untestable Fault Identification [p. 949]
Hsieh, T.
A New Formulation for SOC Floorplan Area Minimization Problem [p. 1100]
Hu, G.
Speeding up SAT for EDA [p. 1081]
Hu, J.
Power-Efficient Trace Caches [p. 1091]
Hu, X.
Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor [p. 782]
Huang, H.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Huang, L.
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem [p. 470]
Huang, L.
Maze Routing with Buffer Insertion under Transition Time Constraints [p. 702]
Hwang, C.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]

I

Ienne, P.
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors [p. 1138]
Indrusiak, L.
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments [p. 1130]
Irani, S.
Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States [p. 117]
Irwin, M.
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization [p. 436]
Irwin, M.
Power-Efficient Trace Caches [p. 1091]
Irwin, M.
A Complete Phase-Locked Loop Power Consumption Model [p. 1108]
Issenin, I.
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]
Ivask, E.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Iyengar, V.
Efficient Wrapper/TAM Co-Optimization for Large SOCs [p. 491]

J

Jerke, G.
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits [p. 464]
Jerraya, A.
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design [p. 620]
Jiménez-Garrido, F.
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip [p. 362]
Jin, L.
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees [p. 61]
John, W.
The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines [p. 1129]
Jung, S.
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint [p. 260]

K

Kabulepa, L.
Estimation of Power Consumption in Encoded Data Buses [p. 1103]
Kadayif, I.
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization [p. 436]
Kaivola, R.
Formal Verification of the Pentium 4 Floating-Point Multiplier [p. 20]
Kajitani, Y.
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees [p. 61]
Kalla, P.
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification [p. 285]
Kandemir, M.
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization [p. 436]
Kandemir, M.
A Compiler-Based Approach for Improving Intra-Iteration Data Reuse [p. 984]
Kandemir, M.
Power-Efficient Trace Caches [p. 1091]
Kandemir, M.
Reducing Cache Access Energy in Array-Intensive Applications [p. 1092]
Kang, S.
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint [p. 260]
Kania, D.
Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions [p. 1087]
Kapur, R.
Directed-Binary Search in Logic BIST Diagnostics [p. 1121]
Karri, R.
Exploiting Idle Cycles for Algorithm Level Re-Computing [p. 842]
Katopis, G.
Macromodeling of Digital I/O Ports for System EMC Assessment [p. 1044]
Kazmierski, T.
A Two-Tier Distributed Electronic Design Framework [p. 227]
Kebschull, U.
The Use of Runtime Configuration Capabilities for Networked Embedded Systems [p. 1093]
Khazaka, R.
Compact Macromodel for Lossy Coupled Transmission Lines [p. 1114]
Khomenko, V.
Detecting State Coding Conflicts in STGs Using Integer Programming [p. 338]
Kiliç, Y.
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS [p. 1133]
Kim, C.
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction [p. 163]
Kim, J.
A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis [p. 788]
Kim, K.
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint [p. 260]
Kim, W.
A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis [p. 788]
Koegst, M.
An Encoding Technique for Low Power CMOS Implementations of Controllers [p. 1083]
Koh, C.
Flip-Flop and Repeater Insertion for Early Interconnect Planning [p. 690]
Koh, C.
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods [p. 931]
Kolcu, I.
Reducing Cache Access Energy in Array-Intensive Applications [p. 1092]
Koranne, S.
Formulation of SOC Test Scheduling as a Network Transportation Problem [p. 1125]
Köster, M.
(Self-)reconfigurable Finite State Machines: Theory and Implementation [p. 559]
Koutny, M.
Detecting State Coding Conflicts in STGs Using Integer Programming [p. 338]
Krahn, L.
The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines [p. 1129]
Kranitis, N.
Effective Software Self-Test Methodology for Processor Cores [p. 592]
Krauter, B.
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses [p. 628]
Kreku, J.
Mappability Estimation of Architecture and Algorithm [p. 1132]
Kritzinger, P.
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC [p. 1137]
Kruijtzer, W.
A Data Analysis Method for Software Performance Prediction [p. 971]
Kucuk, G.
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors [p. 124]
Kumar, S.
IDDT Testing of Embedded CMOS SRAMs [p. 1117]
Kunz, W.
Improving Placement under the Constant Delay Model [p. 677]
Kurdahi, F.
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures [p. 547]
Kutzschebauch, T.
Layout Driven Decomposition with Congestion Consideration [p. 672]

L

Lai, M.
Maze Routing with Buffer Insertion under Transition Time Constraints [p. 702]
Lampe, S.
Global Optimization Applied to the Oscillator Problem [p. 322]
Lampe, S.
Steady State Calculation of Oscillators Using Continuation Methods [p. 1139]
Lanchares, J.
FPGA Placement by Thermodynamic Combinatorial Optimization [p. 54]
Latorre, L.
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems [p. 1120]
Laur, R.
Steady State Calculation of Oscillators Using Continuation Methods [p. 1139]
Laur, S.
Global Optimization Applied to the Oscillator Problem [p. 322]
Lauwereins, R.
Data Reuse Exploration Techniques for Loop-Dominated Applications [p. 428]
Lauwers, E.
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter [p. 357]
Lavagno, L.
False Path Elimination in Quasi-Static Scheduling [p. 964]
Lechuga, Y.
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal ICs [p. 205]
Leclercq, Y.
Substrate Parasitic Extraction for RF Integrated Circuits [p. 1107]
Lee, B.
Assigning Program and Data Objects to Scratchpad for Energy Reduction [p. 409]
Lee, C.
A New Formulation for SOC Floorplan Area Minimization Problem [p. 1100]
Lee, C.
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits [p. 1119]
Lee, S.
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults [p. 94]
Lee, T.
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs [p. 296]
Lekatsas, H.
An Adaptive Dictionary Encoding Scheme for SOC Data Buses [p. 1059]
Levant, J.
An EMC-Compliant Design Method of High-Density Integrated Circuits [p. 1115]
Leveugle, R.
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance [p. 837]
Li, J.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Li, P.
A Linear-Centric Modeling Approach to Harmonic Balance Analysis [p. 634]
Lienig, J.
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits [p. 464]
Lilius, J.
Towards a Kernel Language for Heterogeneous Computing [p. 1136]
Lin, H.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Lin, J.
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits [p. 1119]
Lin, J.
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG [p. 69]
Lin, T.
On-Chip Inductance Models: 3D or Not 3D? [p. 1112]
Lin, Y.
A New Formulation for SOC Floorplan Area Minimization Problem [p. 1100]
Liu, C.
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment [p. 382]
Liu, I.
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem [p. 470]
Liu, J.
Incremental Diagnosis and Correction of Multiple Faults and Errors [p. 716]
Liu, S.
Analog IP Testing: Diagnosis and Optimization [p. 192]
Liveris, N.
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications [p. 977]
Livshitz, B.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Lobachev, M.
Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider [p. 1127]
Logothetis, G.
Extending Synchronous Languages for Generating Abstract Real-Time Models [p. 795]
López, C.
New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]
Lu, R.
Flip-Flop and Repeater Insertion for Early Interconnect Planning [p. 690]
Lubaszewski, M.
Test Planning and Design Space Exploration in a Core-Based Environment [p. 478]
Luchetta, A.
Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques [p. 1105]
Lv, T.
An Adaptive Dictionary Encoding Scheme for SOC Data Buses [p. 1059]

M

Macchiarulo, L.
Wire Placement for Crosstalk Energy Minimization in Address Buses [p. 158]
Macii, A.
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors [p. 449]
Macii, E.
Wire Placement for Crosstalk Energy Minimization in Address Buses [p. 158]
Macii, E.
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors [p. 449]
Madrid, N.
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects [p. 310]
Maestre, R.
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures [p. 547]
Maex, K.
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate [p. 1113]
Maio, I.
Macromodeling of Digital I/O Ports for System EMC Assessment [p. 1044]
Majoux, B.
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications [p. 316]
Makki, R.
IDDT Testing of Embedded CMOS SRAMs [p. 1117]
Malcovati, P.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Maloberti, F.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Manetti, S.
Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques [p. 1105]
Marek-Sadowska, M.
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components [p. 176]
Marek-Sadowska, M.
Closed-Form Crosstalk Noise Metrics for Physical Design Applications [p. 812]
Marinissen, E.
Efficient Wrapper/TAM Co-Optimization for Large SOCs [p. 491]
Martens, E.
DAISY-CT: A High-Level Simulation Tool for Continuous-Time DeltaSigma Modulators [p. 1110]
Martin, A.
An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor [p. 640]
Martin, G.
How to Choose Semiconductor IP: Embedded Software [p. 16]
Martin, G.
UML for Embedded Systems Specification and Design: Motivation and Overview [p. 773]
Martínez, M.
An Encoding Technique for Low Power CMOS Implementations of Controllers [p. 1083]
Martínez, M.
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal ICs [p. 205]
Marwedel, P.
Assigning Program and Data Objects to Scratchpad for Energy Reduction [p. 409]
Mazumder, P.
Optimal Transistor Tapering for High-Speed CMOS Circuits [p. 708]
Mazumder, P.
Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects [p. 820]
Mazumder, P.
Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling [p. 1038]
McNamara, P.
Analog IP Testing: Diagnosis and Optimization [p. 192]
Melville, R.
Steady State Calculation of Oscillators Using Continuation Methods [p. 1139]
Menard, D.
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms [p. 529]
Mendias, J.
Multiple-Precision Circuits Allocation Independent of Data-Objects Length [p. 909]
Mendias, J.
Maximizing Conditional Reuse by Pre-Synthesis Transformations [p. 1097]
Mercer, M.
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults [p. 94]
Mesman, B.
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models [p. 1021]
Metra, C.
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths [p. 612]
Metra, C.
Self-Checking Scheme for the On-Line Testing of Power Supply Noise [p. 832]
Michel, H.
Hardware/Software Trade-Offs for Advanced 3G Channel Coding [p. 396]
Miklos, P.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Min, S.
A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis [p. 788]
Miranda, M.
Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities [p. 1072]
Mishra, P.
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units [p. 36]
Missaoui, B.
E-Design Based on the Reuse Paradigm [p. 214]
Mneimneh, M.
Search-Based SAT Using Zero-Suppressed BDDs [p. 1082]
Mo, S.
Beyond UML to an End-of-Line Functional Test Engine [p. 499]
Molina, M.
Multiple-Precision Circuits Allocation Independent of Data-Objects Length [p. 909]
Mozuelos, R.
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal ICs [p. 205]
Mukherjee, A.
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components [p. 176]
Münch, M.
Hardware/Software Trade-Offs for Advanced 3G Channel Coding [p. 396]
Münzenberger, R.
A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems [p. 1095]

N

Nakhla, M.
Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function [p. 916]
Nakhla, M.
Compact Macromodel for Lossy Coupled Transmission Lines [p. 1114]
Narasimhan, N.
Formal Verification of the Pentium 4 Floating-Point Multiplier [p. 20]
Nassif, S.
A Linear-Centric Simulation Framework for Parametric Fluctuations [p. 568]
Nauwelaers, B.
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate [p. 1113]
Nayak, A.
Accurate Area and Delay Estimators for FPGAs [p. 862]
Neumann, I.
Improving Placement under the Constant Delay Model [p. 677]
Nicolaidis, M.
IP for Embedded Robustness [p. 240]
Nicolaidis, M.
Embedded Robustness IPs [p. 244]
Nicolau, A.
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units [p. 36]
Nicolau, A.
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]
Nicolau, A.
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs [p. 402]
Nicolau, A.
Power Savings in Embedded Processors through Decode Filer Cache [p. 443]
Nicolau, A.
Memory System Connectivity Exploration [p. 894]
Nicolescu, G.
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design [p. 620]
Nicolici, N.
Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression [p. 604]
Nitsch, C.
The Use of Runtime Configuration Capabilities for Networked Embedded Systems [p. 1093]
Noessing, G.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Nouet, P.
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems [p. 1120]
Novikov, Y.
BerkMin: A Fast and Robust Sat-Solver [p. 142]
Nowick, S.
A Burst-Mode Oriented Back-End for the Balsa Synthesis System [p. 330]
Nowick, S.
High-Speed Non-Linear Asynchronous Pipelines [p. 1000]

O

Oehmen, J.
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits [p. 274]
Olivares, M.
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC [p. 1137]
Orailoglu, A.
Gate Level Fault Diagnosis in Scan-Based BIST [p. 376]
Orailoglu, A.
Reducing Test Application Time Through Test Data Mutation Encoding [p. 387]
Orailoglu, A.
Test Planning and Design Space Exploration in a Core-Based Environment [p. 478]
Orailoglu, A.
Power Efficient Embedded Processor IP's through Application-Specific Tag Compression in Data Caches [p. 1065]
Otsuka, M.
An Environment for Dynamic Component Composition for Efficient Co-Design [p. 736]
Ozdag, R.
High-Speed Non-Linear Asynchronous Pipelines [p. 1000]

P

Padmanaban, S.
Exact Grading of Multiple Path Delay Faults [p. 84]
Palkovic, M.
Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities [p. 1072]
Panda, R.
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model [p. 456]
Pandey, A.
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs [p. 368]
Pandini, D.
Congestion-Aware Logic Synthesis [p. 664]
Panigrahi, A.
The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits [p. 1106]
Paschalis, A.
Effective Software Self-Test Methodology for Processor Cores [p. 592]
Pasko, R.
Techniques to Evolve a C++ Based System Design Language [p. 302]
Passerone, C.
False Path Elimination in Quasi-Static Scheduling [p. 964]
Pastor, E.
A Case Study for the Verification of Complex Timed Circuits: IPCMOS [p. 44]
Patel, J.
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs [p. 368]
Pateras, S.
Embedded Diagnosis IP [p. 242]
Paul, J.
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems [p. 522]
Pedram, M.
Concurrent and Selective Logic Extraction with Timing Consideration [p. 1086]
Pedram, M.
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses [p. 1102]
Peeters, A.
Networks on Silicon: Combining Best-Effort and Guaranteed Services [p. 423]
Peña, M.
A Case Study for the Verification of Complex Timed Circuits: IPCMOS [p. 44]
Penalba, O.
Maximizing Conditional Reuse by Pre-Synthesis Transformations [p. 1097]
Pénzes, P.
An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor [p. 640]
Peralías, E.
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects [p. 310]
Petrov, P.
Power Efficient Embedded Processor IP's through Application-Specific Tag Compression in Data Caches [p. 1065]
Peymandoust, A.
Low Power Embedded Software Optimization Using Symbolic Algebra [p. 1052]
Peyran, O.
Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures [p. 1099]
Phillips, I.
How to Choose Semiconductor IP? -- Embedded Processors [p. 14]
Phillips, J.
Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation [p. 923]
Piccirilli, M.
Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques [p. 1105]
Pilarski, S.
Speeding up SAT for EDA [p. 1081]
Pileggi, L.
A Linear-Centric Simulation Framework for Parametric Fluctuations [p. 568]
Pileggi, L.
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses [p. 628]
Pileggi, L.
A Linear-Centric Modeling Approach to Harmonic Balance Analysis [p. 634]
Pileggi, L.
Congestion-Aware Logic Synthesis [p. 664]
Pileggi, L.
On-Chip Inductance Models: 3D or Not 3D? [p. 1112]
Pomeranz, I.
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults [p. 722]
Pomeranz, I.
Fault Isolation Using Tests for Non-Isolated Blocks [p. 1123]
Pomeranz, I.
Finding a Common Fault Response for Diagnosis during Silicon Debug [p. 1116]
Poncino, M.
Wire Placement for Crosstalk Energy Minimization in Address Buses [p. 158]
Ponomarev, D.
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors [p. 124]
Popp, R.
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits [p. 274]
Pouget, J.
A Heuristic for Test Scheduling at System Level [p. 1124]
Pozzi, L.
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors [p. 1138]
Prasad, M.
Using Problem Symmetry in Search Based Satisfiability Algorithms [p. 134]
Prinetto, P.
Beyond UML to an End-of-Line Functional Test Engine [p. 499]
Prinetto, P.
An Optimal Algorithm for the Automatic Generation of March Tests [p. 938]
Pronath, M.
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits [p. 78]
Pronath, M.
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets [p. 581]
Pyttel, A.
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering [p. 870]

Q

Qu, Y.
Mappability Estimation of Architecture and Algorithm [p. 1132]
Quan, G.
Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor [p. 782]
Quartana, J.
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems [p. 1090]
Quer, S.
Dynamic Scheduling and Clustering in Symbolic Image Computation [p. 150]
Quintana, J.
An Encoding Technique for Low Power CMOS Implementations of Controllers [p. 1083]

R

Rahajandraibe, W.
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications [p. 316]
Raik, J.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Rajski, J.
Finding a Common Fault Response for Diagnosis during Silicon Debug [p. 1116]
Ramdani, M.
An EMC-Compliant Design Method of High-Density Integrated Circuits [p. 1115]
Ratford, V.
Make Your SOC Design a Winner: Select the Right Memory IP [p. 15]
Reda, S.
Reducing Test Application Time Through Test Data Mutation Encoding [p. 387]
Reddy, S.
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults [p. 722]
Reddy, S.
Finding a Common Fault Response for Diagnosis during Silicon Debug [p. 1116]
Reese, R.
Generalized Early Evaluation in Self-Timed Circuits [p. 255]
Reis, R.
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments [p. 1130]
Renaudin, M.
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems [p. 1090]
Rendine, M.
Functional Verification for SystemC Descriptions Using Constraint Solving [p. 744]
Rettberg, A.
Embedded System Design Based On Webservices [p. 232]
Rezvani, P.
Concurrent and Selective Logic Extraction with Timing Consideration [p. 1086]
Riccò, B.
Self-Checking Scheme for the On-Line Testing of Power Supply Noise [p. 832]
Richter, K.
Event Model Interfaces for Heterogeneous System Analysis [p. 506]
Richter, K.
System Design for Flexibility [p. 854]
Rigaud, J.
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems [p. 1090]
Rizzo, D.
A Video Compression Case Study on a Reconfigurable VLIW Architecture [p. 540]
Rodríguez-Vázquez, A.
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip [p. 362]
Rohr, P.
Embedded Robustness IPs [p. 244]
Ross, J.
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS [p. 1133]
Rouzeyre, B.
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification [p. 285]
Rouzeyre, B.
A Heuristic for Test Scheduling at System Level [p. 1124]
Roy, K.
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction [p. 163]
Roy, K.
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods [p. 931]
Roy, K.
Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis [p. 1118]
Rueda, A.
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects [p. 310]
Rugen-Herzig, I.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Rülke, S.
An Encoding Technique for Low Power CMOS Implementations of Controllers [p. 1083]

S

Saias, D.
Substrate Parasitic Extraction for RF Integrated Circuits [p. 1107]
Sakallah, K.
Search-Based SAT Using Zero-Suppressed BDDs [p. 1082]
Sakanushi, K.
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees [p. 61]
Sami, M.
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores [p. 1128]
Sánchez-Élez, M.
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures [p. 547]
Sansen, W.
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics [p. 268]
Sansen, W.
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices [p. 279]
Sarrafzadeh, M.
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis [p. 1016]
Sassatelli, G.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]
Saucier, G.
E-Design Based on the Reuse Paradigm [p. 214]
Sauer, A.
The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines [p. 1129]
Savoiu, N.
Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation [p. 875]
Saxena, S.
Analog IP Testing: Diagnosis and Optimization [p. 192]
Sayed, D.
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio [p. 576]
Schaumont, P.
Techniques to Evolve a C++ Based System Design Language [p. 302]
Schenkel, F.
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets [p. 581]
Schiano, L.
Self-Checking Scheme for the On-Line Testing of Power Supply Noise [p. 832]
Schmitz, M.
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems [p. 514]
Schneider, A.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Schneider, K.
Extending Synchronous Languages for Generating Abstract Real-Time Models [p. 795]
Schwarz, P.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Schwencker, R.
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets [p. 581]
Sciuto, D.
Functional Verification for SystemC Descriptions Using Constraint Solving [p. 744]
Sciuto, D.
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores [p. 1128]
Sciuto, D.
Error Simulation Based on the SystemC Design Description Language [p. 1135]
Sedlmeier, A.
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering [p. 870]
Seepold, R.
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects [p. 310]
Selic, B.
The Real-Time UML Standard: Definition and Application [p. 770]
Sentieys, O.
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms [p. 529]
Sham, C.
Congestion Estimation with Buffer Planning in Floorplan Design [p. 696]
Sheehan, B.
Library Compatible Ceff for Gate-Level Timing [p. 826]
Sherman, A.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Shrivastava, A.
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs [p. 402]
Shukla, S.
Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States [p. 117]
Shukla, S.
An Environment for Dynamic Component Composition for Efficient Co-Design [p. 736]
Shukla, S.
Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation [p. 875]
Silva, M.
A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs [p. 1126]
Silvano, C.
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores [p. 1128]
Silveira, L.
Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation [p. 923]
Simmons, M.
FlexBench: Reuse of Verification IP to Increase Productivity [p. 1131]
Simunic, T.
Managing Power Consumption in Networks on Chip [p. 110]
Simunic, T.
Low Power Embedded Software Optimization Using Symbolic Algebra [p. 1052]
Singh, M.
High-Speed Non-Linear Asynchronous Pipelines [p. 1000]
Sivasubramaniam, A.
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization [p. 436]
Skiba, K.
E-Design Based on the Reuse Paradigm [p. 214]
Skliarova, I.
A SAT Solver Using Software and Reconfigurable Hardware [p. 1094]
Slomka, F.
A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems [p. 1095]
Smirnov, A.
A Case Study for the Verification of Complex Timed Circuits: IPCMOS [p. 44]
Soininen, J.
Mappability Estimation of Architecture and Algorithm [p. 1132]
Sommer, R.
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications [p. 884]
Sonza Reorda, M.
New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]
Soudris, D.
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications [p. 977]
Squillero, G.
New Techniques for Speeding-Up Fault-Injection Campaigns [p. 847]
Stan, M.
The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits [p. 1106]
Steinke, S.
Assigning Program and Data Objects to Scratchpad for Energy Reduction [p. 409]
Steyaert, M.
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter [p. 357]
Stievano, I.
Macromodeling of Digital I/O Ports for System EMC Assessment [p. 1044]
Stöhr, S.
FlexBench: Reuse of Verification IP to Increase Productivity [p. 1131]
Stok, L.
Layout Driven Decomposition with Congestion Consideration [p. 672]
Strojwas, A.
Congestion-Aware Logic Synthesis [p. 664]
Stucchi, M.
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate [p. 1113]
Su, C.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Sulimma, K.
Improving Placement under the Constant Delay Model [p. 677]
Süße, H.
An Encoding Technique for Low Power CMOS Implementations of Controllers [p. 1083]

T

Taddei, A.
Beyond UML to an End-of-Line Functional Test Engine [p. 499]
Tang, W.
Power Savings in Embedded Processors through Decode Filer Cache [p. 443]
Tang, X.
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem [p. 470]
Teich, J.
(Self-)reconfigurable Finite State Machines: Theory and Implementation [p. 559]
Teich, J.
System Design for Flexibility [p. 854]
Thomas, D.
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems [p. 522]
Thornton, M.
Generalized Early Evaluation in Self-Timed Circuits [p. 255]
Thronicke, W.
Embedded System Design Based On Webservices [p. 232]
Tien, T.
Crosstalk Alleviation for Dynamic PLAs [p. 683]
Tomiyama, H.
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units [p. 36]
Torres, L.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [p. 553]
Tragoudas, S.
Exact Grading of Multiple Path Delay Faults [p. 84]
Traver, C.
Generalized Early Evaluation in Self-Timed Circuits [p. 255]
Tsai, T.
Crosstalk Alleviation for Dynamic PLAs [p. 683]
Tugsinavisut, S.
Control Circuit Templates for Asynchronous Bundled-Data Pipelines [p. 1098]

U

Ubar, R.
Internet-Based Collaborative Test Generation with MOSCITO [p. 221]
Uyttenhove, K.
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter [p. 357]

V

Van Achteren, T.
Data Reuse Exploration Techniques for Loop-Dominated Applications [p. 428]
van de Goor, A.
Modeling Techniques and Tests for Partial Faults in Memory Devices [p. 89]
van de Goor, A.
Minimal Test for Coupling Faults in Word-Oriented Memories [p. 944]
van Eijk, K.
Efficient and Effective Redundancy Removal for Million-Gate Circuits [p. 1088]
van Ginneken, L.
Improving Placement under the Constant Delay Model [p. 677]
van Meerbergen, J.
Networks on Silicon: Combining Best-Effort and Guaranteed Services [p. 423]
Van Thielen, B.
Fast Method to Include Parasitic Coupling in Circuit Simulations [p. 1033]
Vanassche, P.
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices [p. 279]
Vandenbergheo, S.
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate [p. 1113]
Vandenbosch, G.
Fast Method to Include Parasitic Coupling in Circuit Simulations [p. 1033]
Vandenbussche, J.
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter [p. 357]
Vandersteen, G.
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach [p. 352]
Vandersteen, G.
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions [p. 586]
Vedula, V.
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis [p. 730]
Veidenbaum, A.
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints [p. 168]
Velev, M.
Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer [p. 28]
Vemuri, R.
A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems [p. 760]
Veneris, A.
Incremental Diagnosis and Correction of Multiple Faults and Errors [p. 716]
Verbeyst, F.
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions [p. 586]
Verkest, D.
Design Technology for Networked Reconfigurable FPGA Platforms [p. 994]
Vernalde, S.
Techniques to Evolve a C++ Based System Design Language [p. 302]
Vijaykrishnan, N.
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization [p. 436]
Vijaykrishnan, N.
Power-Efficient Trace Caches [p. 1091]
Vijaykrishnan, N.
A Complete Phase-Locked Loop Power Consumption Model [p. 1108]
Vijaykrishnan, N.
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization [p. 436]
Vogels, M.
DAISY-CT: A High-Level Simulation Tool for Continuous-Time DeltaSigma Modulators [p. 1110]
Voorakaranam, R.
A Signature Test Framework for Rapid Production Testing of RF Circuits [p. 186]
Vuletic, M.
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors [p. 1138]

W

Wagner, I.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Wambacq, P.
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach [p. 352]
Wambacq, P.
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions [p. 586]
Wang, K.
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components [p. 176]
Watanabe, Y.
False Path Elimination in Quasi-Static Scheduling [p. 964]
Wehmeyer, L.
Assigning Program and Data Objects to Scratchpad for Energy Reduction [p. 409]
Wehn, N.
Hardware/Software Trade-Offs for Advanced 3G Channel Coding [p. 396]
Weigel, R.
Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network [p. 1028]
Wielage, P.
Networks on Silicon: Combining Best-Effort and Guaranteed Services [p. 423]
Williams, J.
Communication Mechanisms for Parallel DSP Systems on a Chip [p. 420]
Williams, T.
Directed-Binary Search in Logic BIST Diagnostics [p. 1121]
Wilson, P.
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS [p. 1133]
Wolf, W.
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs [p. 296]
Wolf, W.
An Adaptive Dictionary Encoding Scheme for SOC Data Buses [p. 1059]
Wong, D.
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem [p. 470]
Wong, D.
Maze Routing with Buffer Insertion under Transition Time Constraints [p. 702]
Wong, W.
Congestion Estimation with Buffer Planning in Floorplan Design [p. 696]
Worm, A.
Hardware/Software Trade-Offs for Advanced 3G Channel Coding [p. 396]
Wu, C.
A Hierarchical Test Scheme for System-On-Chip Designs [p. 486]
Wu, K.
Exploiting Idle Cycles for Algorithm Level Re-Computing [p. 842]

X

Xiang, H.
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem [p. 470]
Xiang, W.
Analog IP Testing: Diagnosis and Optimization [p. 192]
Xu, Q.
Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects [p. 820]

Y

Yakovlev, A.
Detecting State Coding Conflicts in STGs Using Integer Programming [p. 338]
Yakovlev, A.
Visualization of Partial Order Models in VLSI Design Flow [p. 1089]
Ymeri, H.
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate [p. 1113]
Yoo, S.
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design [p. 620]
Young, F.
Congestion Estimation with Buffer Planning in Floorplan Design [p. 696]
Young, F.
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design [p. 1101]

Z

Zaccaria, V.
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores [p. 1128]
Zafalon, R.
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores [p. 1128]
Zanella, S.
Analog IP Testing: Diagnosis and Optimization [p. 192]
Zelikson, M.
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach [p. 804]
Zeng, Z.
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification [p. 285]
Zervas, N.
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications [p. 977]
Zhao, Q.
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models [p. 1021]
Zheng, Z.
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses [p. 628]
Zhong, G.
Flip-Flop and Repeater Insertion for Early Interconnect Planning [p. 690]
Zhuang, C.
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees [p. 61]
Zhuang, W.
Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures [p. 1099]
Zolotov, V.
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model [p. 456]
Zorian, Y.
Effective Software Self-Test Methodology for Processor Cores [p. 592]
Zorian, Y.
Fault Isolation Using Tests for Non-Isolated Blocks [p. 1123]
Zwolinski, M.
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS [p. 1133]