DATE 2004 DESIGNERS' FORUM, AUTHOR INDEX

A

Abraham, J.

Qualification and Integration of Complex I/O in SoC Design Flows [p. 286]

Agostini, L.

Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation [p. 224]

Aitken, R.

From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions [p. 2]

Appell, J.

Evaluation of a Refinement-Driven SystemC™-Based Design Flow [p. 262]

Ascheid, G.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

Ashenden, P.

Improving Design and Verification Productivity with VHDL-200x [p. 332]

Auletta, R.

Expert System Perimeter Block Placement Floorplanning [p. 140]

B

Bailey, S.

Improving Design and Verification Productivity with VHDL-200x [p. 332]

Bainbridge, W.

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip [p. 274]

Bakshi, J.

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]

Balarin, F.

Utilizing Formal Assertions for System Design of Network Processors [p. 126]

Bampi, S.

Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]

A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications [p. 242]

Bannow, N.

Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications [p. 268]

Bantas, S.

An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain [p. 39]

Beguin, E.

VHDL-AMS Library Development for Pacemaker Applications [p. 338]

Benini, L.

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design [p. 312]

Bensoudane, E.

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding [p. 58]

Berens, F.

Channel Decoder Architecture for 3G Mobile Wireless Terminals [p. 192]

Bhasker, J.

Improving Design and Verification Productivity with VHDL-200x [p. 332]

Bhattacharyya, S.

Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems [p. 161]

Bhuyan, L.

Utilizing Formal Assertions for System Design of Network Processors [p. 126]

Bisdounis, L.

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design [p. 312]

Blanc, S.

Experiences during the Experimental Validation of the Time-Triggered Architecture [p. 256]

Bodgan, M.

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks [p. 248]

Bombana, M.

A Design Methodology for the Exploitation of High Level Communication Synthesis [p. 180]

Bona, A.

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip [p. 318]

Boschetti, M.

A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications [p. 242]

Brandolese, C.

Analysis and Modeling of Energy Reducing Source Code Transformations [p. 306]

Braun, A.

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks [p. 248]

Braun, G.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

Bruschi, F.

A Design Methodology for the Exploitation of High Level Communication Synthesis [p. 180]

C

Calvez, J.

A Generic RTOS Model for Real-Time Systems Simulation with SystemC [p. 82]

Canetti, R.

NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices [p. 218]

Carro, L.

Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs [p. 10]

Catthoor, F.

A Power Optimized Display Memory Organization for Handheld User Terminals [p. 294]

Chattopadhyay, A.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

Chavassieux, M.

VHDL-AMS Library Development for Pacemaker Applications [p. 338]

Chen, X

Utilizing Formal Assertions for System Design of Network Processors [p. 126]

Chen, Y.

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]

Chiu, K.

Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip [p. 108]

Chu, W.

Customisable EPIC Processor: Architecture and Tools [p. 236]

Cilardo, A.

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware [p. 206]

Cocco, M.

A Scalable Architecture for LDPC Decoding [p. 88]

Coppola, M.

OCCN A Network-on-Chip Modeling and Simulation Framework [p. 174]

Curaba, S.

OCCN A Network-on-Chip Modeling and Simulation Framework [p. 174]

D

Dadda, L.

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) [p. 70]

Daglio, P.

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components [p. 336]

Dai, W.

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]

Dandia, S.

Package Design for High Performance ICs [p. 5]

Denolf, K.

A Power Optimized Display Memory Organization for Handheld User Terminals [p. 294]

Deutsch, A.

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses [p. 144]

Dewilde, A.

A Power Optimized Display Memory Organization for Handheld User Terminals [p. 294]

Diaz, J.

Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit [p. 134]

Dielissen, J.

A Scalable Architecture for LDPC Decoding [p. 88]

Dimond, R.

Customisable EPIC Processor: Architecture and Tools [p. 236]

Donno, G.

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design [p. 312]

E

Eklow, B.

IP Testing -- The Future Differentiator? [p. 6]

Elfadel, I.

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses [p. 144]

F

Farouk, H.

Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA [p. 212]

Fernández,, F.

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

Ferrer, D.

NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices [p. 218]

Fischer, H.

At Speed Testing of SOC ICs [p. 120]

Flautner, K.

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling [p. 324]

Fleitas, R.

NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices [p. 218]

Flynn, D.

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling [p. 324]

Fornaciari, W.

Analysis and Modeling of Energy Reducing Source Code Transformations [p. 306]

Fummi, F.

Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]

Modeling and Analysis of Heterogeneous Industrial Networks Architectures [p. 342]

Furber, S.

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip [p. 274]

G

Gaffiot, F.

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems' Application to High-Speed CMOS Photoreceiver Front-Ends [p. 16]

Gerlach, J.

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks [p. 248]

Evaluation of a Refinement-Driven SystemC™-Based Design Flow [p. 262]

Gil, P.

Experiences during the Experimental Validation of the Time-Triggered Architecture [p. 256]

Goel, S.

Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip [p. 108]

González, R.

NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices [p. 218]

Gracia, J.

Experiences during the Experimental Validation of the Time-Triggered Architecture [p. 256]

Grammatikakis, M.

OCCN A Network-on-Chip Modeling and Simulation Framework [p. 174]

Gross, J.

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]

H

Hanisch, J.

Evaluation of a Refinement-Driven SystemC™-Based Design Flow [p. 262]

Harame, D.

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]

Haug, K.

Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications [p. 268]

Hecker, B.

VHDL-AMS Library Development for Pacemaker Applications [p. 338]

Heijligers, M.

A Scalable Architecture for LDPC Decoding [p. 88]

Hekstra, A.

A Scalable Architecture for LDPC Decoding [p. 88]

Hollevoet, L.

A Power Optimized Display Memory Organization for Handheld User Terminals [p. 294]

Horský, P. ;

A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications [p. 34]

Hsieh, H.

Utilizing Formal Assertions for System Design of Network Processors [p. 126]

Huisken, J.

A Scalable Architecture for LDPC Decoding [p. 88]

A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver [p. 230]

I

Iezzi, D.

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components [p. 336]

J

Johann, M.

Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]

Júnior, A.

Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs [p. 10]

K

Koch, T.

At Speed Testing of SOC ICs [p. 120]

Kopcsay, G.

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses [p. 144]

Kornaros, G.

Software Processing Performance in Network Processors [p. 186]

Koutsoyannopoulos, Y.

An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain [p. 39]

Kreiselmaier, G.

Channel Decoder Architecture for 3G Mobile Wireless Terminals [p. 192]

Kreutz, E.

RASoC: A Router Soft-Core for Networks-on-Chip [p. 198]

Krupp, A.

Formal Refinement and Model Checking of an Echo Cancellation Unit [p. 102]

L

Laflutte, M.

VHDL-AMS Library Development for Pacemaker Applications [p. 338]

Lagasse, L.

VHDL-AMS Library Development for Pacemaker Applications [p. 338]

Langevin, M.

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding [p. 58]

Lettnin, D.

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks [p. 248]

Leupers, R.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

Lewis, J.

Improving Design and Verification Productivity with VHDL-200x [p. 332]

Li, W.

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]

Liapis, A.

An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain [p. 39]

Lin, C.

LZW-Based Code Compression for VLIW Embedded Systems [p. 76]

Liu, K.

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]

Louagie, F.

A Power Optimized Display Memory Organization for Handheld User Terminals [p. 294]

Loukusa, V.

Systems on Chips Design: System Manufacturer Point of View [p. 3]

Luk, W.

Customisable EPIC Processor: Architecture and Tools [p. 236]

Luo, Y.

Utilizing Formal Assertions for System Design of Network Processors [p. 126]

Lyonnard, D.

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding [p. 58]

M

Macchetti, M,

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) [p. 70]

Marinissen, E.

Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip [p. 108]

Marschner, E.

Improving Design and Verification Productivity with VHDL-200x [p. 332]

Martini, S.

Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]

Modeling and Analysis of Heterogeneous Industrial Networks Architectures [p. 342]

Maruccia, G.

OCCN A Network-on-Chip Modeling and Simulation Framework [p. 174]

Mazzeo, A.

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware [p. 206]

Mecke, J.

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]

Medeiro, F.

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

Meerbergen, J. van

A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver [p. 230]

Menichelli, F.

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design [p. 312]

Meyr, H.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

Moigne, R. Le

A Generic RTOS Model for Real-Time Systems Simulation with SystemC [p. 82]

Monguzzi, M.

Modeling and Analysis of Heterogeneous Industrial Networks Architectures [p. 342]

Mueller, W.

Formal Refinement and Model Checking of an Echo Cancellation Unit [p. 102]

Mühlberger, A.

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]

Müller, M.

A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core [p. 46]

Muradali, F.

From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions [p. 2]

N

Nebel, W.

Evaluation of a Refinement-Driven SystemC™-Based Design Flow [p. 262]

Neffe, U.

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]

Nguyen, T.

Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip [p. 108]

Niranjan, A.

Islands of Synchronicity, A Design Methodology for SoC Design [p. 64]

Nohl, A.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

O

O'Connor, I.

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems' Application to High-Speed CMOS Photoreceiver Front-Ends [p. 16]

Oliver, I.

Formal Refinement and Model Checking of an Echo Cancellation Unit [p. 102]

Olivieri, M.

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design [p. 312]

Oostdijk, S.

Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip [p. 108]

Oudinot, J.

VHDL-AMS Library Development for Pacemaker Applications [p. 338]

Owen, J.

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) [p. 70]

P

Panato, A.

Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]

Papaefstathiou, I.

Software Processing Performance in Network Processors [p. 186]

Papariello, F.

OCCN A Network-on-Chip Modeling and Simulation Framework [p. 174]

Pasquier, O.

A Generic RTOS Model for Real-Time Systems Simulation with SystemC [p. 82]

Patel, D.

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling [p. 324]

Paulin, P.

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding [p. 58]

Perbellini, G.

Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]

Modeling and Analysis of Heterogeneous Industrial Networks Architectures [p. 342]

Pérez, J.

NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices [p. 218]

Pérez-Verdú, B.

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

Perrott, S.

Customisable EPIC Processor: Architecture and Tools [p. 236]

Pilkington, C.

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding [p. 58]

Plana, L.

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip [p. 274]

Pohjonen, H.

Systems on Chips Design: System Manufacturer Point of View [p. 3]

Poncino, M.

Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]

Modeling and Analysis of Heterogeneous Industrial Networks Architectures [p. 342]

Porto, R.

Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation [p. 224]

Q

Quax, M.

A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver [p. 230]

R

Rao, G.

Qualification and Integration of Complex I/O in SoC Design Flows [p. 286]

Reis, R.

Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]

Ren, B.

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]

Ricciato, F.

Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]

Rieger, E.

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]

Rimondi, D.

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components [p. 336]

Río, R. Del

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

Roberts, D.

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling [p. 324]

Rodríguez-Vázquez, A.

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

Roma, C.

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components [p. 336]

Romano, L.

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware [p. 206]

Rosa, J. Del La

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

Rosenstiel, W.

Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments [p. 96]

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks [p. 248]

Rothbart, K.

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]

Rubin, B.

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses [p. 144]

Ruha, A.

Systems on Chips Design: System Manufacturer Point of View [p. 3]

Ruiz-Amaya, J.

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time ΣΔ Modulators [p. 150]

Ruotsalainen, T.

Systems on Chips Design: System Manufacturer Point of View [p. 3]

S

Saburit, M.

Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit [p. 134]

Saeb, M.

Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA [p. 212]

Saggese, G.

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware [p. 206]

Salice, F.

Analysis and Modeling of Energy Reducing Source Code Transformations [p. 306]

Santapa, S.

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components [p. 336]

Saul, P.

Low Power Analogue 90 Degree Phase Shifter [p. 28]

Scagnelli, D.

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]

Schliebusch, O.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

Schmitt, S.

Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments [p. 96]

Schubert, T.

Evaluation of a Refinement-Driven SystemC™-Based Design Flow [p. 262]

Sciuto, D.

Analysis and Modeling of Energy Reducing Source Code Transformations [p. 306]

Seng, S.

Customisable EPIC Processor: Architecture and Tools [p. 236]

Silva, I.

A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications [p. 242]

Silva, S.

Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]

Simon, S.

A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core [p. 46]

Smith, H.

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses [p. 144]

Steger, C.

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]

Steinert, M.

RTL Processor Synthesis for Architecture Exploration and Implementation [p. 156]

Susin, A.

RASoC: A Router Soft-Core for Networks-on-Chip [p. 198]

T

Thiel, T.

Have I Really Met Timing? Validating Primetime Timing Reports with SPICE [p. 114]

Tissafi-Drissi, F.

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems' Application to High-Speed CMOS Photoreceiver Front-Ends [p. 16]

Turolla, M.

Heterogeneous Co-Simulation of Networked Embedded Systems [p. 168]

V

Varkki, O.

Systems on Chips Design: System Manufacturer Point of View [p. 3]

Varma, A.

Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems [p. 161]

Vorisek, V.

At Speed Testing of SOC ICs [p. 120]

W

Wagner, F.

Design of Very Deep Pipelined Multipliers for FPGAs [p. 52]

Wang, A.

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications [p. 280]

Wehn, N.

Channel Decoder Architecture for 3G Mobile Wireless Terminals [p. 192]

Weiss, R.

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards [p. 300]

Werner, K.

Can IP Quality be Objectively Measured? [p. 330]

Wiscombe, P.

Islands of Synchronicity, A Design Methodology for SoC Design [p. 64]

Wolf, W.

LZW-Based Code Compression for VLIW Embedded Systems [p. 76]

Wortmann, A.

A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core [p. 46]

X

Xie, Y.

LZW-Based Code Compression for VLIW Embedded Systems [p. 76]

Y

Yuan, X.

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology [p. 22]

Z

Zaccaria, V.

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip [p. 318]

Zafalon, R.

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip [p. 318]

Zeferino, C.

RASoC: A Router Soft-Core for Networks-on-Chip [p. 198]

Zervos, N.

Software Processing Performance in Network Processors [p. 186]