Technical Program

2.2.1
11:30 - 12:00

Clock Domain Crossing Aware Sequential Clock Gating
Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi and Abhishek Ranjan

2.2.2
12:00 - 12:30

An Energy Efficient Backup Scheme with Low Inrush Current for Nonvolatile SRAM in Energy Harvesting Sensor Nodes
Hehe Li, Yongpan Liu, Qinghang Zhao, Yizi Gu, Xiao Sheng, Guangyu Sun, Chao Zhang, Meng-Fan Chang, Rong Luo and Huazhong Yang

2.2.3
12:30 - 12:45

Race to Idle or Not: Balancing the Memory Sleep Time with DVS for Energy Minimization
Chenchen Fu, Minming Li and Chun Jason Xue

2.2.4
12:45 - 13:00

Event-Driven and Sensorless Photovoltaic System Reconfiguration for Electric Vehicles
Xue Lin, Yanzhi Wang, Massoud Pedram, Jaemin Kim and Naehyuck Chang

2.3.1
11:30 - 12:00

Online Binding of Applications to Multiple Clock Domains in Shared FPGA-based Systems
Farzad Samie, Lars Bauer, Chih-Ming Hsieh and Jörg Henkel

2.3.2
12:00 - 12:30

Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis
Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama and Jason Anderson

2.3.3
12:30 - 13:00

Schedulability Bound for Integrated Modular Avionics Partitions
Jung-Eun Kim, Tarek Abdelzaher and Lui Sha

2.4.1
11:30 - 12:00

Workload Uncertainty Characterization and Adaptive Frequency Scaling for Energy Minimization of Embedded Systems
Anup Das, Akash Kumar, Bharadwaj Veeravalli, Rishad Shafik, Geoff Merrett and Bashir Al-Hashimi

2.4.2
12:00 - 12:30

Formal Analysis of the Startup Delay of SOME/IP Service Discovery
Jan R. Seyler, Thilo Streichert, Michael Gla, Nicolas Navet and Jürgen Teich

2.4.3
12:30 - 12:45

Analysis of Ethernet-Switch Traffic Shapers for In-Vehicle Networking Applications
Sivakumar Thangamuthu, Nicola Concer, Pieter J.L.Cuijpers and Johan J.Lukkien

2.4.4
12:45 - 13:00

Real-Time Capable CAN to AVB Ethernet Gateway Using Frame Aggregation and Scheduling
Christian Herber, Andre Richter, Thomas Wild and Andreas Herkersdorf

2.5.1
11:30 - 12:00

Automatic Extraction of Assertions from Execution Traces of Behavioural Models
Alessandro Danese, Tara Ghasempouri and Graziano Pravadelli

2.5.2
12:00 - 12:30

A Methodology for Automated Design of Embedded Bit-flips Detectors in Post-Silicon Validation
Pouya Taatizadeh and Nicola Nicolici

2.5.3
12:30 - 12:45

Data Mining Diagnostics and Bug MRIs for HW Bug Localization
Monica Farkash, Bryan Hickerson and Balavinayagam Samynathan

2.5.4
12:45 - 13:00

RTL Property Abstraction for TLM Assertion-Based Verification
Nicola Bombieri, Riccardo Filippozzi, Graziano Pravadelli and Francesco Stefanni

2.6.1
11:30 - 12:00

Low-cost Checkpointing in Automotive Safety-Relevant Systems
Carles Hernandez and Jaume Abella

2.6.2
12:00 - 12:30

Uncertainty-Aware Reliability Analysis and Optimization
Faramarz Khosravi, Malte Müuller, Michael Glaß and Jürgen Teich

2.6.3
12:30 - 12:45

Efficient Soft Error Vulnerability Estimation of Complex Designs
Shahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher and Jacob Abraham

2.6.4
12:45 - 13:00

Detection of Illegitimate Access to JTAG via Statistical Learning in Chip
Xuanle Ren, Vítor Grade Tavares and R. D. (Shawn) Blanton

2.7.1
11:30 - 12:00

Joint Affine Transformation and Loop Pipelining for Mapping Nested Loop on CGRAs
Shouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei and Yike Guo

2.7.2
12:00 - 12:30

Path Selection Based Acceleration of Conditionals in CGRAs
ShriHari RajendranRadhika, Aviral Shrivastava and Mahdi Hamzeh

2.7.3
12:30 - 13:00

Hardware-Assisted Code Obfuscation for FPGA Soft Microprocessors
Meha Kainth, Lekshmi Krishnan, Chaitra Narayana, Sandesh Gubbi Virupaksha and Russell Tessier

3.0.1
13:20 - 13:30

New Life Styles Beyond Your Dreams
Thierry Collette

3.0.2
13:30 - 13:50

Drones that Fly for You
Nicolas Besnard

3.0.3
13:50 - 14:10

Robots that Live With You
Rodolphe Gelin

3.2.1
14:30 - 15:00

Reliable Information Extraction for Single Trace Attacks
Valentina Banciu, Elisabeth Oswald and Carolyn Whitnall

3.2.2
15:00 - 15:30

SCANDALee: A Side-ChANnel-based DisAssembLer using Local Electromagnetic Emanations
Daehyun Strobel, Florian Bache, David Oswald, Falk Schellenberg and Christof Paar

3.2.3
15:30 - 15:45

Side-Channel Attacks from Static Power: When Should We Care?
Santos Merino Del Pozo, François-Xavier Standaert, Dina Kamel and Amir Moradi

3.2.4
15:45 - 16:00

Extrax: Security Extension to Extract Cache Resident Information for Snoop-Based External Monitors
Jinyong Lee, Yongje Lee, Hyungon Moon, Ingoo Heo and Yunheung Paek

3.3.1
14:30 - 15:00

Exploiting Loop-Array Dependencies to Accelerate the Design Space Exploration with High Level Synthesis
Nam Khanh Pham, Amit Kumar Singh, Akash Kumar and Mi Mi Aung Khin

3.3.2
15:00 - 15:30

Interplay of Loop Unrolling and Multidimensional Memory Partitioning in HLS
Alessandro Cilardo and Luca Gallo

3.3.3
15:30 - 16:00

Inter-Tile Reuse Optimization Applied to Bandwidth Constrained Embedded Accelerators
Maurice Peemen, Bart Mesman and Henk Corporaal

3.4.1
14:30 - 15:00

SelectDirectory: A Selective Directory for Cache Coherence in Many-Core Architectures
Yuan Yao, Guanhua Wang, Zhiguo Ge, Tulika Mitra, Wenzhi Chen and Naxin Zhang

3.4.2
15:00 - 15:30

DyReCTape: A Dynamically Reconfigurable Cache using Domain Wall Memory Tapes
Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay Pai, Kaushik Roy and Anand Raghunathan

3.4.3
15:30 - 15:45

Cooperatively Managing Dynamic Writeback and Insertion Policies in a Last-level DRAM Cache
Shouyi Yin, Jiakun Li, Leibo Liu, Shaojun Wei and Yike Guo

3.4.4
15:45 - 16:00

A Generic, Scalable and Globally Arbitrated Memory Tree for Shared DRAM Access in Real-Time Systems
Manil Dev Gomony, Jamie Garside, Benny Akesson, Neil Audsley and Kees Goossens

3.5.1
14:30 - 15:00

Variation-Aware Evaluation of MPSoC Task Allocation and Scheduling Strategies using Statistical Model Checking
Mingsong Chen, Daian Yue, Xiaoke Qin, Xin Fu and Prabhat Mishra

3.5.2
15:00 - 15:30

A Fast Parallel Sparse Solver for SPICE-Based Circuit Simulators
Xiaoming Chen, Yu Wang and Huazhong Yang

3.5.3
15:30 - 15:45

MRP: Mix Real Cores and Pseudo Cores for FPGA-based Chip-Multiprocessor Simulation
Xinke Chen, Guangfei Zhang, Huandong Wang, Ruiyang Wu, Peng Wu and Longbing Zhang

3.5.4
15:45 - 16:00

Source Level Performance Simulation of GPU Cores
Christoph Gerum, Oliver Bringmann and Wolfgang Rosenstiel

3.6.1
14:30 - 15:00

Data-Intensive Applications- A Major Challenge Ahead [1136]
Jan van Lunteren

3.6.2
15:00 - 15:30

CIM Architecture- Beyond Von Neumann [1136]
Koen Bertels and Henk Coorporal

3.6.3
15:30 - 16:00

Memristive Devices - The Key Enabler for CIM Architecture Implementation [1136]
Eike Linn

3.7.1
14:30 - 15:00

Delay Analysis of Structural Real-Time Workload
Nan Guan, Yue Tang, Yang Wang and Wang Yi

3.7.2
15:00 - 15:30

Effective Verification of Low-Level Software with Nested Interrupts
Daniel Kroening, Lihao Liang, Tom Melham, Peter Schrammel and Michael Tautschnig

3.7.3
15:30 - 15:45

Platform-Specific Timing Verification Framework in Model-Based Implementation
BaekGyu Kim, Lu Feng Linh T.X. Phan, Oleg Sokolsky and Insup Lee

3.7.4
15:45 - 16:00

Architecture Description Language Based Retargetable Symbolic Execution
Andreas Ibing

3.8.1
14:30 - 15:00

Error Recovery in Digital Microfluidics for Personalized Medicine
Mohamed Ibrahim and Krishnendu Chakrabarty

3.8.2
15:00 - 15:30

A Cyber-Physical Systems Approach to Personalized Medicine: Challenges and Opportunities for NoC-based Multicore Platforms
Paul Bogdan

3.8.3
15:30 - 16:00

On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications
Turbo Majumder, Partha Pratim Pande and Ananth Kalyanaraman

IP1-1

High-Resolution Online Power Monitoring for Modern Microprocessors
Fabian Oboril, Jos Ewert and Mehdi B. Tahoori

IP1-2

Reducing Energy Consumption in Microcontroller-Based Platforms with Low Design Margin Co-Processors
Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi and Jose Pineda de Gyvez

IP1-3

De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits
Mahdi Jelodari Mamaghani, Jim Garside and Doug Edwards

IP1-4

Automated Feature Localization for Dynamically Generated SystemC Designs
Jannis Stoppe, Robert Wille and Rolf Drechsler

IP1-5

Inductor Optimization for Active Cell Balancing Using Geometric Programming
Matthias Kauer, Swaminathan Narayanaswami, Martin Lukasiewycz, Sebastian Steinhorst and Samarjit Chakraborty

IP1-6

Lightweight Authentication for Secure Automotive Networks
Philipp Mundhenk, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy and Samarjit Chakraborty

IP1-7

Minimizing the Number of Process Corner Simulations during Design Verification
Michael Shoniker, Bruce F. Cockburn, Jie Han and Witold Pedrycz

IP1-8

An Approximate Voting Scheme for Reliable Computing
Ke Chen, Fabrizio Lombardi and Jie Han

IP1-9

FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design
Rochus Nowosielski, Lukas Gerlach, Stephan Bieband, Guillermo Payá-Vayá and Holger Blume

IP1-10

A Unified Hardware/Software MPSoC System Construction and Run-Time Framework
Sam Skalicky, Andrew G. Schmidt, Sonia Lopez and Matthew French

IP1-11

(AS)² : Accelerator Synthesis using Algorithmic Skeletons for Rapid Design Space Exploration
Shakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar and Henk Corporaal

IP1-12

Assisted Generation of Frame Conditions for Formal Models
Philipp Niemann, Frank Hilken, Martin Gogolla and Robert Wille

IP1-13

Towards a Meta-Language for the Concurrency Concern in DSLs
Julien Deantoni, Issa Papa Diallo, Ciprian Teodorov, Joel Champeau and Benoit Combemale

IP1-14

Fast and Accurate Branch Predictor Simulation
Antoine Faravelon, Nicolas Fournel and Frédéric Pétrot

IP1-15

Comparative Study of Test Generation Methods for Simulation Accelerators
Wisam Kadry, Dimtry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong and Jae Cheol Son

IP1-16

Using Structural Relations for Checking Combinationality of Cyclic Circuits
Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang and Chun-Yao Wang

IP1-17

NFRs Early Estimation Through Software Metrics
Andrws Vieira, Pedro Faustini, Luigi Carro and Érika Cota

4.2.1
17:00 - 17:30

Privacy-Preserving Functional IP Verification utilizing Fully Homomorphic Encryption
Charalambos Konstantinou, Anastasis Keliris and Michail Maniatakos

4.2.2
17:30 - 18:00

Efficient Software Implementation of Ring-LWE Encryption
Ruan de Clercq, Sujoy Sinha Roy, Frederik Vercauteren and Ingrid Verbauwhede

4.2.3
18:00 - 18:30

Embedded HW/SW Platform for On-the-Fly Testing of True Random Number Generators
Bohan Yang, Vladimir Rožić, Nele Mentens, Wim Dehaene and Ingrid Verbauwhede

4.3.1
17:00 - 17:30

An Online Thermal-Constrained Task Scheduler for 3D Multi-Core Processors
Chien-Hui Liao, Charles H.-P. Wen and Krishnendu Chakrabarty

4.3.2
17:30 - 18:00

A Symbolic System Synthesis Approach for Hard Real-Time Systems Based on Coordinated SMT-Solving
Alexander Biewer, Benjamin Andres, Jens Gladigau, Torsten Schaub and Christian Haubelt

4.3.3
18:00 - 18:30

E-pipeline: Elastic Hardware/Software Pipelines on a Many-Core Fabric
Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel and Sri Parameswaran

4.4.1
17:00 - 17:30

Soft-Error Reliability and Power Co-Optimization for GPGPUs Register File using Resistive Memory
Jingweijia Tan, Zhi Li and Xin Fu

4.4.2
17:30 - 18:00

Energy-Efficient Cache Design in Emerging Mobile Platforms: The Implications and Optimizations
Kaige Yan and Xin Fu

4.4.3
18:00 - 18:15

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment
Jeremy Constantin, Lai Wang, Georgios Karakonstantis, Anupam Chattopadhyay and Andreas Burg

4.4.4
18:15 - 18:30

Variability-Aware Dark Silicon Management in On-Chip Many-Core Systems
Muhammad Shafique, Dennis Gnad, Siddharth Garg and Jörg Henkel

4.5.1
17:00 - 17:15

Systematic Application of ISO 26262 on a SEooC - Support by Applying a Systematic Reuse Approach
Alejandra Ruiz, Alberto Melzi and Tim Kelly

4.5.2
17:15 - 17:30

Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms
Franck Warte, Leonidas Kosmidisy, Adriana Gogonel, Andrea Baldovin, Zoe Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega and Francisco J. Cazorla

4.5.3
17:30 - 17:45

Silicon Proof of the Intelligent Analog IP Design Flow for Flexible Automotive Components
T. Reich, H. D. B. Prautsch, U. Eichler and R. Buhl

4.5.4
17:45 - 18:00

Fast Optical Simulation From a Reduced Set of Impulse Responses Using SystemC-AMS
Fabien Teysseyre, David Navarro, Ian O'Connor, Francesco Cascio, Fabio Cenni and Olivier Guillaume

4.5.5
18:00 - 18:15

Designer-Level Verification – An Industrial Experience Story
Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek and Vasantha Vuyyuru

4.5.6
18:15 - 18:30

Minimum Current Consumption Transition Time Optimization Methodology for Low Power CTS
Vibhu Sharma

4.6.1
17:00 - 17:30

A Defect-Aware Reconfigurable Cache Architecture for Low-Vccmin DVFS-Enabled Systems
Michail Mavropoulos, Georgios Keramidas and Dimitris Nikolos

4.6.2
17:30 - 18:00

Temperature-Aware Software-Based Self-Testing for Delay Faults
Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li and Masahiro Fujita

4.6.3
18:00 - 18:15

Operational Fault Detection and Monitoring of a Memristor-Based LUT
T. Nandha Kumar, Haider A.F. Almurib and Fabrizio Lombardi

4.6.4
18:15 - 18:30

Power-Aware Online Testing of Manycore Systems in the Dark Silicon Era
Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi and Hannu Tenhunen

4.7.1
17:00 - 17:30

Digital Circuits Reliability with In-Situ Monitors in 28nm Fully Depleted SOI
M. Saliva, F. Cacho, V. Huard, X. Federspiel, D. Angot, A. Benhassain, A. Bravaix and L. Anghel

4.7.2
17:30 - 18:00

Read/Write Robustness Estimation Metrics for Spin Transfer Torque (STT) MRAM Cell
Elena I. Vatajelu, Rosa Rodriguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto and Joan Figueras

4.7.3
18:00 - 18:30

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits
Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon and Giovanni De Micheli

5.1.1
8:30 - 8:52

IoT for healthcare
Giovanni De Micheli

5.1.2
8:52 - 9:14

IoT for smart home
Sylvain Paineau

5.1.3
9:14 - 9:36

IoT for Automotive
Juergen Hornung

5.1.4
9:36 - 9:58

IoT for Smart Cities
Levent Gurgen

5.2.1
8:30 - 9:00

Improved Practical Differential Fault Analysis of Grain-128
Prakash Dey, Abhishek Chakraborty, Avishek Adhikari and Debdeep Mukhopadhyay

5.2.2
9:00 - 9:30

A Score-Based Classification Method for Identifying Hardware-Trojans at Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa and Nozomu Togawa

5.2.3
9:30 - 10:00

Hardware Trojan Detection for Gate-level ICs Using Signal Correlation Based Clustering
Burçin Çakır and Sharad Malik

5.3.1
8:30 - 9:00

Exploiting DRAM Restore Time Variations in Deep Sub-micron Scaling
Xianwei Zhang, Youtao Zhang, Bruce R. Childers and Jun Yang

5.3.2
9:00 - 9:30

Adaptively Tolerate Power-Gating-Induced Power/Ground Noise under Process Variations
Zhe Wang, Xuan Wang, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong, Haoran Li, Rafael K. V. Maeda and Zhifei Wang

5.3.3
9:30 - 9:45

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories
Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Meinerzhagen and Andreas Burg

5.3.4
9:45 - 10:00

Retention Time Measurements and Modelling of Bit Error Rates of WIDE I/O DRAM in MPSoCs
Christian Weis, Matthias Jung, Peter Ehses, Cristiano Santos, Pascal Vivet, Sven Goossens, Martijn Koedam and Norbert Wehn

5.4.1
8:30 - 9:00

Coherent Crosstalk Noise Analyses in Ring-Based Optical Interconnects
Luan H. K. Duong, Mahdi Nikdast, Jiang Xu, Zhehui Wang, Yvain Thonnart, Sébastien Le Beux, Peng Yang, Xiaowen Wu and Zhifei Wang

5.4.2
9:00 - 9:30

Enabling Vertical Wormhole Switching in 3D NoC-Bus Hybrid Systems
Changlin Chen, Marius Enachescu and Sorin D. Cotofana

5.4.3
9:30 - 10:00

A Closed Loop Transmitting Power Self-Calibration Scheme for Energy Efficient WiNoC Architectures
Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania and M. N. Marsono

5.5.1
8:30 - 9:00

Sufficient Response Time Analysis considering Dependencies Between Rate-Dependent Tasks
Timo Feld and Frank Slomka

5.5.2
9:00 - 9:30

Engine Control: Task Modeling and Analysis
Alessandro Biondi and Giorgio Buttazzo

5.5.3
9:30 - 9:45

Evaluation of Diverse Compiling for Software-Fault Detection
Andrea Höller, Nermin Kajtazovic, Tobias Rauter, Kay Römer and Christian Kreiner

5.5.4
9:45 - 10:00

Worst-Case Communication Time Analysis of Networks-on-Chip with Shared Virtual Channels
Eberle A. Rambo and Rolf Ernst

5.6.1
8:30 - 9:00

On the Statistical Memory Architecture Exploration and Optimization
Charalampos Antoniadis, Georgios Karakonstantis, Nestor Evmorfopoulos, Andreas Burg and George Stamoulis

5.6.2
9:00 - 9:30

ECRIPSE: An Efficient Method for Calculating RTN-Induced Failure Probability of an SRAM Cell
Hiromitsu Awano, Masayuki Hiromoto and Takashi Sato

5.6.3
9:30 - 10:00

Subpage Programming for Extending the Lifetime of NAND Flash Memory
Jung-Hoon Kim, Sang-Hoon Kim and Jin-Soo Kim

5.7.1
8:30 - 9:00

Optimized Selection of Reliable and Cost-Effective Cyber-Physical System Architectures
Nikunj Bajaj, Pierluigi Nuzzo, Michael Masin and Alberto Sangiovanni-Vincentelli

5.7.2
9:00 - 9:30

Software Assisted Non-volatile Register Reduction for Energy Harvesting Based Cyber-Physical System
Mengying Zhao, Qingan Li, Mimi Xie, Yongpan Liu, Jingtong Hu and Chun Jason Xue

5.7.3
9:30 - 9:45

A Re-entrant Flowshop Heuristic for Online Scheduling of the Paper Path in a Large Scale Printer
Umar Waqas, Marc Geilen, Jack Kandelaars, Lou Somers, Twan Basten, Sander Stuijk, Patrick Vestjens and Henk Corporaal

5.7.4
9:45 - 10:00

MPIOV: Scaling Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using Non Transparent Bridges to (Multi-Core) Multi-Processor Systems
Daniel Münch, Michael Paulitsch, Oliver Hanka and Andreas Herkersdorf

5.8.1
8:30 - 8:52

Ultra-Fast Source-Level Timing Simulation – High Accuracy Needs Exact Code Matching [1105]
Oliver Bringmann

5.8.2
8:52 - 9:15

Host-Compiled Operating System and Processor Modeling [1105]
Andreas Gerstlauer

5.8.3
9:15 - 9:37

Abstract Communication Models for Accurate and Fast SoC Simulation [1105]
Daniel Mueller-Gritschneder

5.8.4
9:37 - 10:00

Industrial Perspective on Ultra-High Speed and Timing-Accurate SoC and Peripheral Models [1105]
Ajay Goyal

IP2-1

Comparison of Multi-Purpose Cores of Keccak and AES
Panasayya Yalla, Ekawat Homsirikamol and Jens-Peter Kaps

IP2-2

On-Line Prediction of NBTI-induced Aging Rates
Rafal Baranowski, Farshad Firouzi, Saman Kiamehr, Chang Liu, Mehdi Tahoori and Hans-Joachim Wunderlich

IP2-3

Retraining-Based Timing Error Mitigation for Hardware Neural Networks
Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen and Chengyong Wu

IP2-4

Dictionary-Based Sparse Representation for Resolution Improvement in Laser Voltage Imaging of CMOS Integrated Circuits
T. Berkin Cilingiroglu, Mahmoud Zangeneh, Aydan Uyar, W. Clem Karl, Janusz Konrad, Ajay Joshi, Bennett B. Goldberg and M. Selim Unlu

IP2-5

Fault-based Attacks on the Bel-T Block Cipher Family
Philipp Jovanovic and Ilia Polian

IP2-6

On the Premises and Prospects of Timing Speculation
Rong Ye, Feng Yuan, Jie Zhang and Qiang Xu

IP2-7

Impact of Interconnect Multiple-Patterning Variability on SRAMs
Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare and Wim Dehaene

IP2-8

Coherence Based Message Prediction for Optically Interconnected Chip Multiprocessors
Anouk Van Laer, Chamath Ellawala, Muhammad Ridwan Madarbux, Philip M. Watts and Timothy M. Jones

IP2-9

OpenMP and Timing Predictability: A Possible Union?
Roberto Vargas, Eduardo Quinones and Andrea Marongiu

IP2-10

SAHARA: A Security-Aware Hazard and Risk Analysis Method
Georg Macher, Harald Sporer, Reinhard Berlach, Eric Armengaud and Christian Kreiner

IP2-11

CyberPhysical-System-On-Chip (CPSoC): A Self-Aware MPSoC Paradigm with Cross-Layer Virtual Sensing and Actuation
S.Sarma, N.Dutt, P.Gupta, N. Venkatasubramanian and A. Nicolau

IP2-12

Occupancy Detection via iBeacon on Android Devices for Smart Building Management
A. Corna, L. Fontana, A. A. Nacci and D. Sciuto

IP2-13

A Neural Machine Interface Architecture for Real-Time Artificial Lower Limb Control
Jason Kane, Qing Yang, Robert Hernandez, Willard Simoneau and Matthew Seaton

6.1.1
11:00 - 11:22

The Human Intranet — Where Swarms and Humans Meet
Jan M. Rabaey

6.1.2
11:22 - 11:44

Energy efficient electronics for the Internet of Things
Stefan Heinen

6.1.3
11:44 - 12:06

Software Architectures for the Internet of Things
Mario Trapp

6.1.4
12:06 - 12:28

oneM2M : a Standard for an Open and Interoperable M2M Platform, thanks to Semantic Web Tools
Marylin Arndt-Vincent

6.2.1
11:00 - 11:30

Efficient Attacks on Robust Ring Oscillator PUF with Enhanced Challenge-Response Set
Phuong Ha Nguyen, Durga Prasad Sahoo, Rajat Subhra Chakraborty and Debdeep Mukhopadhyay

6.2.2
11:30 - 12:00

A Robust Authentication Methodology Using Physically Unclonable Functions in DRAM Arrays
Maryam S. Hashemian, Bhanu Singh, Francis Wolff, Daniel Weyer, Steve Clay and Christos Papachristou

6.2.3
12:00 - 12:30

A Novel Modeling Attack Resistant PUF Design based on Non-linear Voltage Transfer Characteristics
Arunkumar Vijayakumar and Sandip Kundu

6.3.1
11:00 - 11:30

Asymmetric Underlapped FinFET Based Robust SRAM Design at 7nm Node
A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan and Kaushik Roy

6.3.2
11:30 - 12:00

Quality Configurable Reduce-and-Rank for Energy Efficient Approximate Computing
Arnab Raha, Swagath Venkataramani, Vijay Raghunathan and Anand Raghunathan

6.3.3
12:00 - 12:15

Ultra-Low-Power ECG Front-End Design Based on Compressed Sensing
Hossein Mamaghanian and Pierre Vandergheynst

6.3.4
12:15 - 12:30

GTFUZZ: A Novel Algorithm for Robust Dynamic Power Optimization via Gate Sizing with Fuzzy Games
Tony Casagrande and Nagarajan Ranganathan

6.4.1
11:00 - 11:30

A Ultra-Low-Energy Convolution Engine for Fast Brain-Inspired Vision in Multicore Clusters
Francesco Conti and Luca Benini

6.4.2
11:30 - 12:00

Eliminating Intra-Warp Conflict Misses in GPU
Bin Wang, Zhuo Liu, Xinning Wang and Weikuan Yu

6.4.3
12:00 - 12:15

RNA: A Reconfigurable Architecture for Hardware Neural Acceleration
Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu and Shaojun Wei

6.4.4
12:15 - 12:30

ApproxANN: An Approximate Computing Framework for Artificial Neural Network
Qian Zhang, Ting Wang, Ye Tian, Feng Yuan and Qiang Xu

6.5.1
11:00 - 11:30

DRAM or no-DRAM? Exploring Linear Solver Architectures for Image Domain Warping in 28 nm CMOS
Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic and Luca Benini

6.5.2
11:30 - 12:00

A Small Non-Volatile Write Buffer to Reduce Storage Writes in Smartphones
Mungyu Son, Sungkwang Lee, Kyungho Kim, Sungjoo Yoo and Sunggu Lee

6.5.3
12:00 - 12:15

Clustering-Based Multi-Touch Algorithm Framework for the Tracking Problem with a Large Number of Points
Shih-Lun Huang, Sheng-Yi Hung and Chung-Ping Cheny

6.5.4
12:15 - 12:30

A Low Energy 2D Adaptive Median Filter Hardware
Ercan Kalali and Ilker Hamzaoglu

6.6.1

Panelist [1146]
Giovanni De Micheli

6.6.2

Panelist [1146]
Jalal Bagherli

6.6.3

Panelist [1146]
Thierry Collette

6.6.4

Panelist [1146]
Antun Domic

6.6.5

Panelist [1146]
Horst Symanzik

6.6.6

Panelist [1146]
Sir Hossein Yassaye

6.7.1
11:00 - 11:30

Adaptive on-the-Fly Application Performance Modeling for Many Cores
Sebastian Kobbe, Lars Bauer and Jörg Henkel

6.7.2
11:30 - 12:00

Customization of OpenCL Applications for Efficient Task Mapping under Heterogeneous Platform Constraints
Edoardo Paone, Francesco Robino, Gianluca Palermo, Vittorio Zaccaria, Ingo Sander and Cristina Silvano

6.7.3
12:00 - 12:30

Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures
Tushar Rawat and Aviral Shrivastava

7.0.1(Keynote)
12:50 - 13:20

SPECIAL DAY Keynote: Industrie 4.0: From the Internet of Things to Cyber-Physical Production Systems
Wolfgang Wahlster

7.0.2(Keynote)
13:20 - 13:50

SPECIAL DAY Keynote: The Rise of IoT, and the Role of EDA
Antun Domic

7.1.1
14:30 - 14:52

IoT Challenges and Opportunities
Hannes Schwaderer

7.1.2
14:52 - 15:14

IoT Development for a Connected Car
Marco Bekooij

7.1.3
15:14 - 15:36

If It's Not on the Internet, It's Just a Thing: but what are the IoT problems to solve?
Remy Pottier

7.1.4
15:36 - 15:58

IoT Hardware & Mixed Signal Development
Ian Dennison

7.2.1
14:30 - 14:52

Computing Approximately, and Efficiently
Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy and Anand Raghunathan

7.2.2
14:52 - 15:15

Novel Inexact Memory Aware Algorithm Co-design for Energy Efficient Computation — Algorithmic Principles
Guru Prakash Arumugam, Prashanth Srikanthan, John Augustine, Krishna Palem, Eli Upfal, Ayush Bhargava, Parishkrati and Sreelatha Yenugula

7.2.3
15:15 - 15:37

Designing Inexact Systems Efficiently Using Elimination Heuristics
Shyamsundar Venkataraman, Akash Kumar, Jeremy Schlachter and Christian Enz

7.2.4
15:37 - 16:00

Opportunities for Energy Efficient Computing: A Study of Inexact General Purpose Processors for High-Performance and Big-Data Applications
Peter Düben, Jeremy Schlachter, Parishkrati, Sreelatha Yenugula, John Augustine, Christian Enz, K. Palem and T. N. Palmer

7.3.1
14:30 - 14:45

Introduction to Hardware Trojans Detection Methods
Julien Francq and Florian Frick

7.3.2
14:45 - 15:00

New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans
Sophie Dupuis, Papa-Sidy Ba, Marie-Lise Flottes, Giorgio Di Natale and Bruno Rouzeyre

7.3.3
15:00 - 15:30

Hardware Trojan Detection by Delay and Electromagnetic Measurements
X.-T. Ngo, I. Exurville, S. Bhasin, J.-L. Danger, S. Guilley, Z. Najm, J.-B. Rigaud and B. Robisson

7.3.4
15:30 - 16:00

A High Efficiency Hardware Trojan Detection Technique Based on Fast SEM Imaging
Franck Courbon, Philippe Loubet-Moundi, Jacques J.A. Fournier and Assia Tria

7.4.1
14:30 - 15:00

Mixed Wire and Surface-wave Communication Fabrics for Decentralized On-Chip Multicasting
Ammar Karkar, Kin-Fai Tong, Terrence Mak and Alex Yakovlev

7.4.2
15:00 - 15:30

d² -LBDR: Distance-Driven Routing to Handle Permanent Failures in 2D Mesh NoCs
Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur and José Flich

7.4.3
15:30 - 16:00

Synergistic Use of Multiple On-Chip Networks for Ultra-Low Latency and Scalable Distributed Routing Reconfiguration
Marco Balboni, José Flich and Davide Bertozzi

7.5.1
14:30 - 15:00

Axilog: Language Support for Approximate Hardware Design
Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh and Kia Bazargan

7.5.2
15:00 - 15:30

Improving MPSoC Reliability through Adapting Runtime Task Schedule based on Time-Correlated Fault Behavior
Laura A. Rozo Duque, Jose M. Monsalve Diaz and Chengmo Yang

7.5.3
15:30 - 15:45

ACSEM: Accuracy-Configurable Fast Soft Error Masking Analysis in Combinatorial Circuits
Florian Kriebel, Semeen Rehman, Duo Sun, Pau Vilimelis Aceituno, Muhammad Shafique and Jörg Henkel

7.5.4
15:45 - 16:00

Energy Minimization for Fault Tolerant Scheduling of Periodic Fixed-Priority Applications on Multiprocessor Platforms
Qiushi Han, Ming Fan, Linwei Niu and Gang Quan

7.6.1
14:30 - 15:00

Dp-Fill: A Dynamic Programming Approach to X-Filling for Minimizing Peak Test Power in Scan Tests
Satya A. Trinadh, Sobhan Babu Ch., Shiv Govind Singh, Seetal Potluri and Kamakoti V.

7.6.2
15:00 - 15:30

A Scan Partitioning Algorithm for Reducing Capture Power of Delay-Fault LBIST
Nan Li, Elena Dubrova and Gunnar Carlsson

7.6.3
15:30 - 16:00

Architecture of Ring-based Redundant TSV for Clustered Faults
Wei-Hen Lo, Kang Chi and TingTing Hwang

7.7.1
14:30 - 15:00

Technology-Design Co-optimization of Resistive Cross-point Array for Accelerating Learning Algorithms on Chip
Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma Vrudhula, Jae-sun Seo, Yu Cao and Shimeng Yu

7.7.2
15:00 - 15:30

Spiking Neural Network with RRAM: Can We Use It for Real-World Application?
Tianqi Tang, Lixue Xia, Boxun Li, Rong Luo, Yiran Chen, Yu Wang and Huazhong Yang

7.7.3
15:30 - 16:00

Comparative Study of Power-Gating Architectures for Nonvolatile FinFET-SRAM Using Spintronics-Based Retention Technology
Yusuke Shuto, Shuu’ichirou Yamamoto and Satoshi Sugahara

IP3-1

STT MRAM-Based PUFs
Elena Ioana Vatajelu, Giorgio Di Natale, Marco Indaco and Paolo Prinetto

IP3-2

Spatial and Temporal Granularity Limits of Body Biasing in UTBB-FDSOI
Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann and Wolfgang Rosenstiel

IP3-3

A Hardware Implementation of a Radial Basis Function Neural Network Using Stochastic Logic
Yuan Ji, Feng Ran, Cong Ma and David J. Lilja

IP3-4

SODA: Software Defined FPGA based Accelerators for Big Data
Chao Wang, Xi Li and Xuehai Zhou

IP3-5

Dynamic Reconfigurable Puncturing for Secure Wireless Communication
Liang Tang, Jude Angelo Ambrose, Akash Kumar and Sri Parameswaran

IP3-6

QR-Decomposition Architecture Based on Two-Variable Numeric Function Approximation
Jochen Rust, Frank Ludwig and Steffen Paul

IP3-7

In-place Memory Mapping Approach for Optimized Parallel Hardware Interleaver Architectures
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy and Awais Sani

IP3-8

Maximizing Common Idle Time on Multi-Core Processors with Shared Memory
Chenchen Fu, Yingchao Zhao, Minming Li and Chun Jason Xue

IP3-9

Maximizing IO Performance Via Conflict Reduction for Flash Memory Storage Systems
Qiao Li, Liang Shi, Congming Gao, Kaijie Wu, Chun Jason Xue, Qingfeng Zhuge and Edwin H.-M. Sha

IP3-10

A Hybrid Packet/Circuit-switched Router to Accelerate Memory Access in NoC-based Chip Multiprocessors
Abbas Mazloumi and Mehdi Modarressi

IP3-11

Semiautomatic Implementation of a Bioinspired Reliable Analog Task Distribution Architecture for Multiple Analog Cores
Julius von Rosen, Markus Meissner and Lars Hedrich

IP3-12

Power-Efficient Accelerator Allocation in Adaptive Dark Silicon Many-Core Systems
Muhammad Usman Karim Khan, Muhammad Shafique and Jörg Henkel

IP3-13

Thermal-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems
Davide Pagano, Mikel Vuka, Marco Rabozzi, Riccardo Cattaneo, Donatella Sciuto and Marco D. Santambrogio

IP3-14

Feedback-Bus Oscillation Ring: A General Architecture for Delay Characterization and Test of Interconnects
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han (Hans) Tsai and Wu-Tung Cheng

IP3-15

Analog Neuromorphic Computing Enabled by Multi-Gate Programmable Resistive Devices
Vehbi Calayir, Mohamed Darwish, Jeffrey Weldon and Larry Pileggi

IP3-16

An Energy-efficient Non-volatile In-Memory Accelerator for Sparse-representation based Face Recognition
Yuhao Wang, Hantao Huang, Leibin Ni, Hao Yu, Mei Yan, Chuliang Weng, Wei Yang and Junfeng Zhao

8.1.1

Panelist
Erdinç Öztürk

8.1.2

Panelist
Guido Bertoni

8.1.3

Panelist
Francois-Xavier Standaert

8.1.4

Panelist
Christoph Grimm

8.1.5

Panelist
Wayne Burleson

8.2.1
17:00 - 17:30

HLC: Software-Based Half-Level-Cell Flash Memory
Han-Yi Lin and Jen-Wei Hsieh

8.2.2
17:30 - 18:00

AHEAD: Automated Framework for Hardware Accelerated Iterative Data Analysis
Ebrahim M. Songhori, Azalia Mirhoseini, Xuyang Lu and Farinaz Koushanfar

8.2.3
18:00 - 18:30

Design Method for Multiplier-Less Two-Variable Numeric Function Approximation
Jochen Rust and Steffen Paul

8.3.1
17:00 - 17:30

A Thermal Stress-Aware Algorithm for Power and Temperature Management of MPSoCs
Mehdi Kamal, Arman Iranfar, Ali Afzali-Kusha and Massoud Pedram

8.3.2
17:30 - 18:00

Predictive Dynamic Thermal and Power Management for Heterogeneous Mobile Platforms
Gaurav Singla, Gurinderjit Kaur, Ali K. Unver and Umit Y. Ogras

8.3.3
18:00 - 18:30

Power-Efficient Control of Thermoelectric Coolers Considering Distributed Hot Spots
Mohammad Javad Dousti and Massoud Pedram

8.4.1
17:00 - 17:15

DSP Based Programmable FHD HEVC Decoder
Sangjo Lee, Joonho Song, Wonchang Lee, Doohyun Kim, Jaehyun Kim and Shihwa Lee

8.4.2
17:15 - 17:30

Accelerating Complex Brain-Model Simulations on GPU Platforms
H.A. Du Nguyen, Zaid Al-Ars, Georgios Smaragdos and Christos Strydis

8.4.3
17:30 - 17:45

A Packet-switched Interconnect for Many-core Systems with BE and RT Service
Runan Ma, Zhida Hui and Axel Jantsch

8.4.4
17:45 - 18:00

Reducing Trace Size in Multimedia Applications Endurance Tests
Serge Vladimir Emteu Tchagou, Alexandre Termier, Jean-Franois Méhaut, Brice Videau, Miguel Santana and Ren Quiniou

8.4.5
18:00 - 18:15

Exploration and Design of Embedded Systems Including Neural Algorithms
Jean-Marc Philippe, Alexandre Carbon, Olivier Brousse and Michel Paindavoine

8.4.6
18:15 - 18:30

A New Distributed Framework for Integration of District Energy Data from Heterogeneous Devices
Francesco G. Brundu, Edoardo Patti, Andrea Acquaviva, Michelangelo Grosso, Gaetano Rasconà, Salvatore Rinaudo and Enrico Macii

8.5.1
17:00 - 17:20

Spintronic Devices as Key Elements for Energy-Efficient Neuroinspired Architectures
Nicolas Locatelli, Adrien F. Vincent, Alice Mizrahi, Joseph S. Friedman, Damir Vodenicarevic, Joo-Von Kim, Jacques-Olivier Klein, Weisheng Zhao, Julie Grollier and Damien Querlioz

8.5.2
17:20 - 17:40

Giant Spin Hall Effect (GSHE) Logic Design for Low Power Application
Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li and Yiran Chen

8.5.3
17:40 - 18:00

Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui and Akira Mochizuki

8.5.4
18:00 - 18:15

Potential Applications Based on NVM Emerging Technologies
Sophiane Senni, Raphael Martins Brum, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatie and Bruno Mussard

8.5.5
18:15 - 18:30

From Device to System: Cross-layer Design Exploration of Racetrack Memory
Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, J.-O. Klein, D. Ravelosona, Yongpan Liu, Weisheng Zhao and Huazhong Yang

8.6.1
17:00 - 17:30

Efficient Bit Error Rate Estimation for High-Speed Link by Bayesian Model Fusion
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li and Chenjie Gu

8.6.2
17:30 - 18:00

Fast Deployment of Alternate Analog Test Using Bayesian Model Fusion
John Liaperdos, Haralampos-G. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni and Xin Li

8.6.3
18:00 - 18:15

Bordersearch: An Adaptive Identification of Failure Regions
Markus Dobler, Manuel Harrant, Monica Rafaila, Georg Pelz, Wolfgang Rosenstiel and Martin Bogdan

8.6.4
18:15 - 18:30

A Fast Spatial Variation Modeling Algorithm for Efficient Test Cost Reduction of Analog/RF Circuits
Hugo Gonçalves, Xin Li, Miguel Correia, Vitor Tavares, John Carulli and Kenneth Butler

8.7.1
17:00 - 17:30

Bytecode-to-C Ahead-of-Time Compilation for Android Dalvik Virtual Machine
Hyeong-Seok Oh, Ji Hwan Yeo and Soo-Mook Moon

8.7.2
17:30 - 18:00

A Basic Linear Algebra Compiler for Embedded Processors
Nikolaos Kyrtatas, Daniele G. Spampinato and Markus Püschel

8.7.3
18:00 - 18:30

VARSHA: Variation and Reliability-Aware Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era
Nishit Kapadia and Sudeep Pasricha

9.1.1
8:30 - 9:00

Game changing innovation in Technology and Design for effective health care
Chris Van Hoof

9.1.2
9:00 - 9:30

Advanced Self-Powered Systems of Integrated Sensors and Technologies
Veena Misra

9.1.3
9:30 - 10:00

Healthcare in an Integrated Digital World
Jean-Paul Linnartz

9.2.1
8:30 - 8:52

Transparent Acceleration of Program Execution Using Reconfigurable Hardware
Nuno Paulino, João Canas Ferreira, João Bispo and João M. P. Cardoso

9.2.2
8:52 - 9:15

Accelerating Arithmetic Kernels with Coherent Attached FPGA Coprocessors
Heiner Giefers, Raphael Polig and Christoph Hagleitner

9.2.3
9:15 - 9:37

Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi
Marvin Damschen, Heinrich Riebler, Gavin Vaz and Christian Plessl

9.2.4
9:37 - 10:00

Transparent Linking of Compiled Software and Synthesized Hardware
David B. Thomas, Shane T. Fleming, George A. Constantinides and Dan R. Ghica

9.3.1
8:30 - 9:00

PhaseNoC: TDM Scheduling at the Virtual-Channel Level for Efficient Network Traffic Isolation
A. Psarras, I. Seitanidis, C. Nicopoulos and G. Dimitrakopoulos

9.3.2
9:00 - 9:30

Rate-based vs Delay-Based Control for DVFS in NoC
Mario R. Casu and Paolo Giaccone

9.3.3
9:30 - 10:00

NoC-Enabled Multicore Architectures for Stochastic Analysis of Biomolecular Reactions
Turbo Majumder, Xian Li, Paul Bogdan and Partha Pande

9.4.1
8:30 - 9:00

Optimization of Quantum Computer Architecture using a Resource-Performance Simulator
Muhammad Ahsan and Jungsang Kim

9.4.2
9:00 - 9:30

Volume-Oriented Sample Preparation for Reactant Minimization on Flow-Based Microfluidic Biochips with Multi-Segment Mixers
Chi-Mei Huang, Chia-Hung Liu and Juinn-Dar Huang

9.4.3
9:30 - 10:00

Thermal Aware Design Method for VCSEL-Based On-Chip Optical Interconnect
Hui Li, Alain Fourmigue, Sébastien Le Beux, Xavier Letartre, Ian O'Connor and Gabriela Nicolescu

9.5.1
8:30 - 9:00

Dynamic Power and Performance Back-Annotation for Fast and Accurate Functional Hardware Simulation
Dongwook Lee, Lizy K. John and Andreas Gerstlauer

9.5.2
9:00 - 9:30

Fast and Precise Cache Performance Estimation for Out-Of-Order Execution
Roeland J. Douma, Sebastian Altmeyer and Andy D. Pimentel

9.5.3
9:30 - 10:00

A Calibration Based Thermal Modeling Technique for Complex Multicore Systems
Devendra Rai and Lothar Thiele

9.6.1
8:30 - 9:00

Knowledge-Intensive, Causal Reasoning for Analog Circuit Topology Synthesis in Emergent and Innovative Applications
Fanshu Jiao, Sergio Montano and Alex Doboli

9.6.2
9:00 - 9:30

A CNN-Inspired Mixed Signal Processor Based on Tunnel Transistors
Behnam Sedighi, Indranil Palit, X. Sharon Hu, Joseph Nahas and Michael Niemier

9.6.3
9:30 - 9:45

Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction
Nuno Lourenço, Ricardo Martins and Nuno Horta

9.6.4
9:45 - 10:00

Initial Transient Response of Oscillators with Long Settling Time
Hans Georg Brachtendorf and Kai Bittner

9.7.1
8:30 - 9:00

Quick Error Detection Tests with Fast Runtimes for Effective Post-Silicon Validation and Debug
David Lin, Eswaran S., Sharad Kumar, Eric Rentschler and Subhasish Mitra

9.7.2
9:00 - 9:30

GPU-Accelerated Small Delay Fault Simulation
Eric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen and Hans-Joachim Wunderlich

9.7.3
9:30 - 9:45

Fault Simulation with Parallel Exact Critical Path Tracing in Multiple Core Environment
Maksim Gorev, Raimund Ubar and Sergei Devadze

9.7.4
9:45 - 10:00

On the Automatic Generation of SBST Test Programs for In-Field Test
Andreas Riefert, Riccardo Cantoro, Matthias Sauer Matteo Sonza Reorda and Bernd Becker

9.8.1
8:30 - 9:00

A Comprehensive Study of Monolithic 3D Cell on Cell Design Using Commercial 2D Tool
O. Billoint, H. Sarhan, I. Rayane, M. Vinet, P. Batude, C. Fenouillet-Beranger, O. Rozeau, G. Cibrario, F. Deprat, A. Fustier, J.-E. Michallet, O. Faynot, O. Turkyilmaz, J.-F. Christmann, S. Thuries and F. Clermidy

9.8.2
9:00 - 9:30

Monolithic 3D Integration: A Path from Concept to Reality
Max M. Shulaker, Tony F. Wu, Mohamed M. Sabry, Hai Wei, H.-S. Philip Wong and Subhasish Mitra

9.8.3
9:30 - 10:00

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs
Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici and Giovanni De Micheli

IP4-1

PWL: A Progressive Wear Leveling to Minimize Data Migration Overheads for NAND Flash Devices
Fu-Hsin Chen, Ming-Chang Yang, Yuan-Hao Chang and Tei-Wei Kuo

IP4-2

Towards Trustable Storage Using SSDs with Proprietary FTL
Xiaotong Cui, Minhui Zou, Liang Shi and Kaijie Wu

IP4-3

User-Specific Skin Temperature-Aware DVFS for Smartphones
Begum Egilmez, Gokhan Memik, Seda Ogrenci-Memik and Oguz Ergin

IP4-4

Formal Probabilistic Analysis of Distributed Dynamic Thermal Management
Shafaq Iqtedar, Osman Hasan, Muhammad Shafique and Jörg Henkel

IP4-5

A Hybrid Quasi Monte Carlo Method for Yield Aware Analog Circuit Sizing Tool
Engin Afacan, Gönenç Berkol, Ali Emre Pusane, Günhan Dündar and Faik Baskaya

IP4-6

Feature Selection for Alternate Test Using Wrappers: Application to an RF LNA Case Study
Manuel J. Barragan and Gildas Leger

IP4-7

Improving SIMD Code Generation in QEMU
Sheng-Yu Fu, Jan-Jan Wu and Wei-Chung Hsu

IP4-8

Reuse Distance Analysis for Locality Optimization in Loop-Dominated Applications
Christakis Lezos, Grigoris Dimitroulakos and Konstantinos Masselos

IP4-9

TAPP: Temperature-Aware Application Mapping for NoC-Based Many-Core Processors
Di Zhu, Lizhong Chen, Timothy M. Pinkston and Massoud Pedram

IP4-10

Malleable NoC: Dark Silicon Inspired Adaptable Network-on-Chip
Haseeb Bokhari, Haris Javaid, Muhammad Shafique Jörg Henkel and Sri Parameswaran

IP4-11

Topology Identification for Smart Cells in Modular Batteries
Sebastian Steinhorst and Martin Lukasiewycz

IP4-12

LVS Check for Photonic Integrated Circuits – Curvilinear Feature Extraction and Validation
Ruping Cao, Julien Billoudet, John Ferguson, Lionel Couder, John Cayo, Alexandre Arriordaz and Ian O'Connor

IP4-13

FP-Scheduling for Mode-Controlled Dataflow: A Case Study
Alok Lele, Orlando Moreira and Kees van Berkel

IP4-14

Ageing Simulation of Analogue Circuits and Systems using Adaptive Transient Evaluation
Felix Salfelder and Lars Hedrich

IP4-15

A Tool for the Assisted Design of Charge Redistribution SAR ADCs
S. Brenna, A. Bonetti, A. Bonfanti and A. L. Lacaita

IP4-16

Detection of Asymmetric Aging-Critical Voltage Conditions in Analog Power-Down Mode
Michael Zwerger and Helmut Graeb

IP4-17

High Performance Single Supply CMOS Inverter Level up Shifter for Multi–Supply Voltages Domains
José C. García, Juan A. Montiel–Nelson, J. Sosa and Saeid Nooshabadi

IP4-18

Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing
A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi M.Sonza Reorda

IP4-19

A Breakpoint-Based Silicon Debug Technique with Cycle-Granularity for Handshake-Based SoC
Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li and Kuen-Jong Lee

IP4-20

Fault Diagnosis in Designs with Extreme Low Pin Test Data Compressors
Subhadip Kundu, Parthajit Bhattacharya and Rohit Kapur

IP4-21

Optimizing Dynamic Trace Signal Selection Using Machine Learning and Linear Programming
Charlie Shucheng Zhu and Sharad Malik

10.1.1
11:00 - 11:30

Mobile health monitoring: adoption and system challenges
David Shanes

10.1.2
11:30 - 12:00

Wearable Device For Physical and Emotional Health Monitoring
Srinivasan Murali

10.1.3
12:00 - 12:30

Gait Analysis for Fall Prediction Using Hierarchical Textile-Based Capacitive Sensor Arrays
Rebecca Baldwin, Stan Bobovych, Ryan Robucci, Chintan Patel and Nilanjan Banerjee

10.2.1
11:00 - 11:30

HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory
Miguel Angel Lastras-Montaño, Amirali Ghofrani and Kwang-Ting Cheng

10.2.2
11:30 - 12:00

nCode: Limiting Harmful Writes to Emerging Mobile NVRAM through Code Swapping
Kan Zhong, Duo Liu, Linbo Long, Xiao Zhu, Weichen Liu, Qingfeng Zhuge and Edwin H.-M. Sha

10.2.3
12:00 - 12:15

System Level Exploration of a STT-MRAM based Level 1 Data-Cache
Manu Perumkunnil Komalan, Christian Tenllado, José Ignacio Gómez Pérez, Francisco Tirado Fernández and Francky Catthoor

10.2.4
12:15 - 12:30

High Performance AXI-4.0 Based Interconnect for Extensible Smart Memory Cubes
Erfan Azarkhish, Davide Rossi, Igor Loi and Luca Benini

10.3.1
11:00 - 11:30

The Federated Scheduling of Constrained-Deadline Sporadic DAG Task Systems
Sanjoy Baruah

10.3.2
11:30 - 12:00

Run and Be Safe: Mixed-Criticality Scheduling with Temporary Processor Speedup
Pengcheng Huang, Pratyush Kumar, Georgia Giannopoulou and Lothar Thiele

10.3.3
12:00 - 12:30

Multi-Core Fixed-Priority Scheduling of Real-Time Tasks with Statistical Deadline Guarantee
Tianyi Wang, Linwei Niu, Shaolei Ren and Gang Quan

10.4.1
11:00 - 11:30

Memory Fast-Forward: A Low Cost Special Function Unit to Enhance Energy Efficiency in GPU for Big Data Processing
Eunhyeok Park, Junwhan Ahn, Sungpack Hong, Sungjoo Yoo and Sunggu Lee

10.4.2
11:30 - 12:00

Power Minimization for Data Center with Guaranteed QoS
Shuo Liu, Soamar Homsi, Ming Fan, Shaolei Ren, Gang Quan and Shangping Ren

10.4.3
12:00 - 12:30

Energy-Aware Cooling for Hot-Water Cooled Supercomputers
Christian Conficoni, Andrea Bartolini, Andrea Tilli, Giampietro Tecchiolli, Luca Benini

10.5.1
11:00 - 11:30

Hybrid Adaptive Clock Management for FPGA Processor Acceleration
Alexandru Gheolbănoiu, Lucian Petrică and Sorin Cotofană

10.5.2
11:30 - 12:00

A Scalable and High-Density FPGA Architecture with Multi-Level Phase Change Memory
Chunan Wei, Ashutosh Dhar and Deming Chen

10.5.3
12:00 - 12:30

FPGA Accelerated DNA Error Correction
Anand Ramachandran, Yun Heo, Wen-Mei Hwu, Jian Ma and Deming Chen

10.6.1
11:00 - 11:30

Fast Eye Diagram Analysis for High-Speed CMOS Circuits
Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout and Shobha Vasudevan

10.6.2
11:30 - 12:00

Statistical Library Characterization Using Belief Propagation Across Multiple Technology Nodes
Li Yu, Sharad Saxena, Christopher Hess, Ibrahim (Abe) M. Elfadel, Dimitri Antoniadis and Duane Boning

10.6.3
12:00 - 12:15

Combining Adaptive Alternate Test and Multi-Site
Gildas Leger

10.6.4
12:15 - 12:30

A Method for the Estimation of Defect Detection Probability of Analog/RF Defect-Oriented Tests
John Liaperdos, Angela Arapoyanni and Yiorgos Tsiatouhas

10.7.1
11:00 - 11:30

Automated Rectification Methodologies to Functional State-Space Unreachability
Ryan Berryhill and Andreas Veneris

10.7.2
11:30 - 12:00

Over-Approximating Loops to Prove Properties Using Bounded Model Checking
Priyanka Darke, Bharti Chimdyalwar, R. Venkatesh, Ulka Shrotri and Ravindra Metta

10.7.3
12:00 - 12:15

Automatic Extraction of Micro-Architectural Models of Communication Fabrics from Register Transfer Level Designs
Sebastiaan J. C. Joosten and Julien Schmaltz

10.7.4
12:15 - 12:30

GALS Synthesis and Verification for xMAS Models
Frank Burns, Danil Sokolov and Alex Yakovlev

11.0.1(Keynote)
13:15 - 13:20

Best IP Award Presentation
Oliver Bringmann

11.0.2(Keynote)
13:20 - 13:50

Bioelectronic Medicines - Heralding in a New Therapeutic Approach
Kristoffer Famm

11.1.1
14:00 - 14:30

Active implantable medical devices
Renzo Dal Molin

11.1.2
14:30 - 15:00

Towards next generation Deep Brain Stimulation
Michael Decré

11.1.3
15:00 - 15:30

Integrated Circuits and Microsystems for Emerging Biomedical Devices
Minkyu Je

11.2.1
14:00 - 14:30

Variation-Aware, Reliability-Emphasized Design and Optimization of RRAM Using SPICE Model
H. Li, Z. Jiang, P. Huang, Y. Wu, H.-Y. Chen, B. Gao, X. Y. Liu, J. F. Kang and H.-S. P. Wong

11.2.2
14:30 - 15:00

Impact of Process-Variations in STTRAM and Adaptive Boosting for Robustness
Seyedhamidreza Motaman, Swaroop Ghosh and Nitin Rathi

11.2.3
15:00 - 15:15

Device/Circuit/Architecture Co-Design of Reliable STT-MRAM
Zoha Pajouhi, Xuanyao Fong and Kaushik Roy

11.2.4
15:15 - 15:30

Sub-10 nm FinFETs and Tunnel-FETs: From Devices to Systems
Ankit Sharma, A. Arun Goud and Kaushik Roy

11.3.1
14:00 - 14:15

5% or 5X? The Performance Gap in SIMD Optimization, and Possible Solutions [1129]
Ben Juurlink

11.3.2
14:15 - 14:30

Model-Based Design of Real-Time Systems [1129]
Lothar Thiele

11.3.3
14:30 - 14:45

Programming Adaptive and Energy-Efficient Many-Cores [1129]
Jeronimo Castrillon

11.3.4
14:45 - 15:00

Confidence in the Use of Software Tools According to the ISO 26262 in Automotive Multicore Applications [1129]
Ralph Jessenberger

11.3.5
15:00 - 15:15

Automotive Multicore Microcontroller Simulation, Debugging and Analysis using Virtual Prototypes [1129]
Victor Reyes

11.3.6
15:15 - 15:30

Applying Multicore Compiler Research into Industrial Practices: An Early Experience Report [1129]
Weihua Sheng

11.4.1
14:00 - 14:30

A New Approximate Adder with Low Relative Error and Correct Sign Calculation
Junjun Hu and Weikang Qian

11.4.2
14:30 - 15:00

Towards Binary Circuit Models That Faithfully Capture Physical Solvability
Matthias Függer, Robert Najvirt, Thomas Nowak and Ulrich Schmid

11.4.3
15:00 - 15:15

A Coupling Area Reduction Technique Applying ODC Shifting
Yi Diao, Tak-Kei Lam, Xing Wei and Yu-Liang Wu

11.4.4
15:15 - 15:30

A General Design of Stochastic Circuit and Its Synthesis
Zheng Zhao and Weikang Qian

11.5.1
14:00 - 14:30

Paper, Pen and Ink: An Innovative System and Software Framework to Assist Writing Rehabilitation
Leonardo Guardati, Filippo Casamassima, Elisabetta Farella and Luca Benini

11.5.2
14:30 - 15:00

An All-Digital Spike-Based Ultra-Low-Power IR-UWB Dynamic Average Threshold Crossing Scheme for Muscle Force Wireless Transmission
Amirhossein, Masoud Shahshahani, Paolo Motto Ros, Alberto Bonanno, Marco Crepaldi, Maurizio Martina, Danilo Demarchi and Guido Masera

11.5.3
15:00 - 15:30

A Pulsed-Index Technique for Single-Channel, Low-Power, Dynamic Signaling
Shahzad Muzaffar, Jerald Yoo, Ayman Shabra and Ibrahim (Abe) M. Elfadel

11.6.1
14:00 - 14:30

SAPPHIRE: An Always-on Context-Aware Computer Vision System for Portable Devices
Swagath Venkataramani, Victor Bahl, Xian-Sheng Hua, Jie Liu, Jin Li, Matthai Phillipose, Bodhi Priyantha and Mohammed Shoaib

11.6.2
14:30 - 15:00

Approximate Associative Memristive Memory for Energy-Efficient GPUs
Abbas Rahimi, Amirali Ghofrani, Kwang-Ting Cheng, Luca Benini and Rajesh K. Gupta

11.6.3
15:00 - 15:15

Platform-Aware Dynamic Configuration Support for Efficient Text Processing on Heterogeneous System
Mi Sun Park, Omesh Tickoo, Vijaykrishnan Narayanan, Mary Jane Irwin and Ravi Iyer

11.6.4
15:15 - 15:30

A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
Cláudio Machado Diniz, Muhammad Shafique, Felipe Vogel Dalcin, Sergio Bampi and Jörg Henkel

11.7.1
14:00 - 14:30

MatEx: Efficient Transient and Peak Temperature Computation for Compact Thermal Models
Santiago Pagani, Jian-Jia Chen, Muhammad Shafique, and Jörg Henkel

11.7.2
14:30 - 15:00

Distributed Reinforcement Learning for Power Limited Many-Core System Performance Optimization
Zhuo Chen and Diana Marculescu

11.7.3
15:00 - 15:15

An Energy-Efficient Virtual Channel Power-Gating Mechanism for On-Chip Networks
Amirhossein Mirhosseini, Mohammad Sadrosadati, Ali Fakhrzadehgan, Mehdi Modarressi and Hamid Sarbazi-Azad

11.7.4
15:15 - 15:30

M-DTM: Migration-based Dynamic Thermal Management for Heterogeneous Mobile Multi-core Processors
Young Geun Kim, Minyong Kim, Jae Min Kim and Sung Woo Chung

IP5-1

Towards Systematic Design of 3D pNML Layouts
Robert Perricone, Yining Zhu, Katherine M. Sanders, X. Sharon Hu and Michael Niemier

IP5-2

DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches
Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey S. Vetter and Yuan Xie

IP5-3

Big-Data Streaming Applications Scheduling with Online Learning and Concept Drift Detection
Karim Kanoun and Mihaela van der Schaar

IP5-4

Design Flow and Run-Time Management for Compressed FPGA Configurations
Christophe Huriaux, Antoine Courtay and Olivier Sentieys

IP5-5

Empirical Modelling of FDSOI CMOS Inverter for Signal/Power Integrity Simulation
Wael Dghais and Jonathan Rodriguez

IP5-6

On-Chip Measurement of Bandgap Reference Voltage Using a Small Form Factor VCO Based Zoom-in ADC
Osman Emir Erol, Sule Ozev, Chandra Suresh, Rubin Parekhji and Lakshmanan Balasubramanian

IP5-7

Logical Equivalence Checking of Asynchronous Circuits Using Commercial Tools
Arash Saifhashemi, Hsin-Ho Huang, Priyanka Bhalerao and Peter A. Beerel

IP5-8

May-Happen-in-Parallel Analysis of ESL Models Using UPPAAL Model Checking
Che-Wei Chang and Rainer Dömer

IP5-9

Verifying Synchronous Reactive Systems using Lazy Abstraction
Kumar Madhukar, Mandayam Srivas, Björn Wachter, Daniel Kroening and Ravindra Metta

IP5-10

SPINTASTIC: Spin-Based Stochastic Logic for Energy-Efficient Computing
Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy and Anand Raghunathan

IP5-11

Leakage Power Reduction for Deeply-Scaled FinFET Circuits Operating in Multiple Voltage Regimes Using Fine-Grained Gate-Length Biasing Technique
Ji Li, Qing Xie, Yanzhi Wang, Shahin Nazarian and Massoud Pedram

IP5-12

SubHunter: A High-Performance and Scalable Sub-Circuit Recognition Method with Prüfer-Encoding
Hong-Yan Su, Chih-Hao Hsu and Yih-Lang Li

IP5-13

Timing Verification for Adaptive Integrated Circuits
Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann and Jiang Hu

IP5-14

A Robust Approach for Process Variation Aware Mask Optimization
Jian Kuang, Wing-Kai Chow and Evangeline F.Y. Young

IP5-15

FastTree: A Hardware KD-Tree Construction Acceleration Engine for Real-Time Ray Tracing
Xingyu Liu, Yangdong Deng, Yufei Ni and Zonghui Li

IP5-16

Reverse Longstaff-Schwartz American Option Pricing on hybrid CPU/FPGA Systems
Christian Brugger, Javier Alejandro Varela, Norbert Wehn, Songyin Tang and Ralf Korn

IP5-17

Accurate Electrothermal Modeling of Thermoelectric Generators
Mohammad Javad Dousti, Antonio Petraglia and Massoud Pedram

IP5-18

Efficiency-Driven Design Time Optimization of a Hybrid Energy Storage System with Networked Charge Transfer Interconnnect
Qing Xie, Younghyun Kim, Donkyu Baek, Yanzhi Wang, Massoud Pedram and Naehyuck Chang

12.1.1
16:00 - 16:30

Ultraflexible Integrated Circuits for imperceptible Bio-Sensors
Tsuyoshi Sekitani

12.1.2
16:30 - 17:00

Nanoelectronics for disruptive diagnostic platforms
Liesbet Lagae

12.1.3
17:00 - 17:30

An Ultra-Low Power Dual-mode ECG Monitor for Healthcare and Wellness
Daniele Bortolotti, Mauro Mangia, Andrea Bartolini, Riccardo Rovatti, Gianluca Setti and Luca Benini

12.2.1
16:00 - 16:30

Solving DQBF Through Quantifier Elimination
Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl and Bernd Becker

12.2.2
16:30 - 17:00

Formal Verification of Sequential Galois Field Arithmetic Circuits Using Algebraic Geometry
Xiaojun Sun, Priyank Kalla, Tim Pruss and Florian Enescu

12.2.3
17:00 - 17:15

A Universal Macro Block Mapping Scheme for Arithmetic Circuits
Xing Wei, Yi Diao, Tak-Kei Lam and Yu-Liang Wu

12.2.4
17:15 - 17:30

Towards An Accurate Reliability, Availability and Maintainability Analysis Approach for Satellite Systems Based on Probabilistic Model Checking
Khaza Anuarul Hoque, Otmane Ait Mohamed and Yvon Savaria

12.3.1
16:00 - 16:30

An Effective Triple Patterning Aware Grid-Based Detailed Routing Approach
Zhiqing Liu, Chuangwen Liu and Evangeline F. Y. Young

12.3.2
16:30 - 17:00

Simultaneous Transistor Pairing and Placement for CMOS Standard Cells
Ang Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang and Rung-Bin Lin

12.3.3
17:00 - 17:15

A TSV Noise-Aware 3-D Placer
Yu-Min Lee, Chun Chen, JiaXing Song and Kuan-Te Pan

12.3.4
17:15 - 17:30

Identifying Redundant Inter-Cell Margins and Its Application to Reducing Routing Congestion
Woohyun Chung, Seongbo Shim and Youngsoo Shin

12.4.1
16:00 - 16:30

Models for Deterministic Execution of Real-Time Multiprocessor Applications
Peter Poplavko, Dario Socci, Paraskevas Bourgos, Saddek Bensalem and Marius Bozga

12.4.2
16:30 - 17:00

Pre-Simulation Symbolic Analysis of Synchronization Issues between Discrete Event and Timed Data Flow Models of Computation
Liliana Andrade, Torsten Maehne, Alain Vachoux, Cédric Ben Aoun, François Pêcheux and Marie-Minerve Louërat

12.4.3
17:00 - 17:30

Formal Consistency Checking over Specifications in Natural Languages
Rongjie Yan, Chih-Hong Cheng and Yesheng Chai

12.5.1
16:00 - 16:30

Tackling the Bottleneck of Delay Tables in 3D Ultrasound Imaging
A. Ibrahim, P. Hager, A. Bartolini, F. Angiolini, M. Arditi, L. Benini and G. De Micheli

12.5.2
16:30 - 17:00

Integrated CMOS Receiver for Wearable Coil Arrays in MRI Applications
Benjamin Sporrer, Luca Bettini, Christian Vogt, Andreas Mehmann, Jonas Reber, Josip Marjanovic, David O. Brunner, Thomas Burger, Klaas P. Pruessmann, Gerhard Tröster and Qiuting Huang

12.5.3
17:00 - 17:30

Tactile Prosthetics in WiseSkin
J. Farserotu, J-D. Decotignie, J. Baborowski, P-N Volpe, C.R. Quirós, V. Kopta, C. Enz, S. Lacour, H. Michaud, R. Martuzzi, V. Koch, H. Huang, T. Li and C. Antfolk

12.6.1
16:00 - 16:30

The Old, the New, and the Recycled – EDA Algorithms in Connectomic
Lou Scheffer

12.6.2
16:30 - 17:00

Computational Modeling and Simulation of Synchronized Firing Behaviors of the Brain
Peng Li

12.6.3
17:00 - 17:30

Electromagnetic Power Deposition Analysis Tool for High Resolution Magnetic Resonance Imaging Brain Scans
Jorge F. Villena, Athanasios G. Polimeridis, Lawrence L. Wald, Elfar Adalsteinsson, Jakob K. White and Luca Daniel

12.7.1
16:00 - 16:15

Towards a quantitative measurement of mental disorders
Jordi Aguiló

12.7.2
16:15 - 16:40

Improving the monitoring and the understanding of mental disorders
Giovanni de Girolamo and Josep Maria Haro

12.7.3
16:40 - 17:05

World Analysis of non-invasive cardiovascular signals for the monitoring of psychophysiological states
Michele Orini and Pablo Laguna

12.7.4
17:05 - 17:30

Healthcare in an Integrated Digital World
Arben Merkoçi

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