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doi: 10.3850/978-3-9815370-4-8_0856
A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
Cláudio Machado Diniz1,a, Muhammad Shafique2,d, Felipe Vogel Dalcin1,b, Sergio Bampi1,c and Jörg Henkel2,e
1Informatics Institute, PPGC, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil.
acmdiniz@inf.ufrgs.br
bfvdalcin@inf.ufrgs.br
cbampi@inf.ufrgs.br
2Chair for Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), Germany.
dmuhammad.shafique@kit.edu
ehenkel@kit.edu
ABSTRACT
The new deblocking filter (DF) tool of the next generation High Efficiency Video Coding (HEVC) standard is one of the most time consuming algorithms in video decoding. In order to achieve real-time performance at low-power consumption, we developed a hardware accelerator for this filter. This paper proposes a high throughput hardware architecture for HEVC deblocking filter employing hardware reuse to accelerate filtering decision units with a low area cost. Our architecture achieves either higher or equivalent throughput (4096×2048 @ 60 fps) with 5X-6X lower area compared to stateof- the-art deblocking filter architectures.
Keywords: HEVC coding, Deblocking filter, Hardware architecture.
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