|
doi: 10.3850/978-3-9815370-4-8_0203
E-pipeline: Elastic Hardware/Software Pipelines on a Many-Core Fabric
Xi Zhang1,a, Haris Javaid1,b, Muhammad Shafique2,e, Jorgen Peddersen1,c, Jörg Henkel2,f and Sri Parameswaran1,d
1School of Computer Science and Engineering, University of New South Wales, Sydney, Australia.
azhangx@cse.unsw.edu.au
bharisj@cse.unsw.edu.au
cjorgenp@cse.unsw.edu.au
dsridevan@cse.unsw.edu.au
2Chair for Embedded Systems, Karlsruhe Institute of Technology, Karlsruhe, Germany.
emuhammad.shafique@kit.edu
fhenkel@kit.edu
ABSTRACT
On-chip many-core systems are expected to be in common use in the future. A set of homogeneous processors in a many-core system can be used to implement multiple pipelines which execute simultaneously. Pipelines of processors use varying numbers of cores when their workloads vary at run time. In this paper, we show how such a system executing multiple pipelines with varying workloads can be implemented. We further show how the system can switch cores within a pipeline (intra-elasticity) and between pipelines (inter-elasticity). The method is named E-pipeline, and is implemented and evaluated in a commercial tool suite. Compared to reference design methods with clock gating, E-pipeline achieves the same power savings, maintains the throughput to meet throughput constraints and reduces core usage by an average of 37.7%. The adaptation overhead for switching cores is approximately 2µs.
Full Text (PDF)
|