Detection of Asymmetric Aging-Critical Voltage Conditions in Analog Power-Down Mode

Michael Zwerger and Helmut Graeb

Institute for Electronic Design Automation, Technische Universität München, Munich, Germany

ABSTRACT

In this work, a new verification method for the power-down mode of analog circuit blocks is presented. In power-down mode, matched transistors can be stressed with asymmetric voltages. This will cause time-dependent mismatch due to transistor aging. In order to avoid reliability problems, a new method for automatic detection of asymmetric power-down stress conditions is presented. Therefore, power-down voltage-matching rules are formulated. The method combines structural analysis and voltage propagation. Experimental results demonstrate the efficiency and effectiveness of the approach.

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