doi: 10.3850/978-3-9815370-4-8_1122

ABSTRACT

The acceleration of applications, running on a gen-eral purpose processor (GPP), by mapping parts of their execu-tion to reconfigurable hardware is an approach which does not involve program’s source code and still ensures program porta-bility over different target reconfigurable fabrics. However, the problem is very challenging, as suitable sequences of GPP in-structions need to be translated/mapped to hardware, possibly at runtime. Thus, all mapping steps, from compiler analysis and optimizations to hardware generation, need to be both efficient and fast. This paper introduces some of the most representative approaches for binary acceleration using reconfigurable hard-ware, and presents our binary acceleration approach and the latest results. Our approach extends a GPP with a Reconfigura-ble Processing Unit (RPU), both sharing the data memory. Re-peating sequences of GPP instructions are migrated to an RPU composed of functional units and interconnect resources, and able to exploit instruction-level parallelism, e.g., via loop pipelin-ing. Although we envision a fully dynamic system, currently the RPU resources are selected and organized offline using execution trace information. We present implementation prototypes of the system on a Spartan-6 FPGA with a MicroBlaze as GPP and the very encouraging results achieved with a number of benchmarks.

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