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doi: 10.3850/978-3-9815370-4-8_0015
(AS)2: Accelerator Synthesis using Algorithmic Skeletons for Rapid Design Space Exploration
Shakith Fernando1,a, Mark Wijtvliet1, Cedric Nugteren1, Akash Kumar2 and Henk Corporaal1
1Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands.
as.fernando@tue.nl
2Department of Electrical & Computer Engineering, National University of Singapore, Singapore
ABSTRACT
Hardware accelerators in heterogeneous multiprocessor
system-on-chips are becoming popular as a means of
meeting performance and energy efficiency requirements of modern
embedded systems. Current design methods for accelerator
synthesis, such as High-Level Synthesis, are not fully automated.
Therefore, time consuming manual iterations are required to
explore efficient accelerator alternatives: the programmer is still
required to think in terms of the underlying architecture. In
this paper, we present (AS)2: a design flow for Accelerator
Synthesis using Algorithmic Skeletons. Skeletonization separates
the structure of a parallel computation from an algorithms’ functionality,
enabling efficient implementations without requiring the
programmer to have hardware knowledge. We define three such
skeletons (for three image processing kernels) enabling FPGA
specific parallelization techniques and optimizations. As a case
study, we present a design space exploration of these skeletons
and show how multiple design points with area–performance
trade-offs for the accelerators can be efficiently and rapidly
synthesized. We show that (AS)2 is a promising direction for
accelerator synthesis as it generates a pareto front of 8 design
points in under half an hour for each of the three image
processing kernels.
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