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doi: 10.3850/978-3-9815370-4-8_0977
A Scalable and High-Density FPGA Architecture with Multi-Level Phase Change Memory
Chunan Weia, Ashutosh Dharb and Deming Chenc
Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA.
aalbertcnw@gmail.com
badhar2@illinois.edu
cdchen@illinois.edu
ABSTRACT
As CMOS technology is stretched to its limits it has become imperative to look to alternative solutions for the next generation of FPGAs. In particular, due to the configurable nature of FPGAs, on-chip memory remains to be a major concern for designers. In this work we explore the use of Phase-Change Memory (PCM).We exploit the ability of PCM to exist in multiple intermediate states to store 2 bits per cell and develop a new Look Up Table (LUT) architecture. The new LUT can either store two functions with shared inputs or a single function with an additional input. We also explore the use of PCM in local routing mechanisms and thus propose a new Configurable Logic Block (CLB) composed of CMOS and PCM. The new design promises significant improvements in logic density and performance with area improvements of over 40% for all LUT sizes and delay improvements of 7% to 13% on an average for LUTs of size 10 to 6.
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