Session Label | Session Title | Time | Location | Details |
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2.1 | Executive Panel: How Electronics May Change Our Lives, and the World | 11:30 - 13:00 | Saal 2 | Read More |
2.2 | Energy Efficient Neural Networks | 11:30 - 13:00 | Konf. 6 | Read More |
2.3 | High-Level Synthesis | 11:30 - 13:00 | Konf. 1 | Read More |
2.4 | Model Checking | 11:30 - 13:00 | Konf. 2 | Read More |
2.5 | GPU and GPU-based heterogeneous system management | 11:30 - 13:00 | Konf. 3 | Read More |
2.6 | Circuit Locking and Camouflaging | 11:30 - 13:00 | Konf. 4 | Read More |
2.7 | Special Session: Spintronics based New Computing Paradigms and Applications | 11:30 - 13:00 | Konf. 5 | Read More |
3.1 | Executive Session: Design Automation for Quantum Computing | 14:30 - 16:00 | Saal 2 | Read More |
3.2 | Approximate and Near-Threshold Computing | 14:30 - 16:00 | Konf. 6 | Read More |
3.3 | Optimization Techniques for MPSoCs | 14:30 - 16:00 | Konf. 1 | Read More |
3.4 | Optimizing Computing with Neuromorphic Architectures and Accelerators | 14:30 - 15:30 | Konf. 2 | Read More |
3.5 | Memory Reliability | 14:30 - 16:00 | Konf. 3 | Read More |
3.6 | Real-time Multiprocessing | 14:30 - 16:00 | Konf. 4 | Read More |
IP1 | Interactive Presentations | 16:00 - 16:30 | Conference Level, Foyer | Read More |
4.1 | Executive Session: Exact Synthesis and SAT | 17:00 - 18:30 | Saal 2 | Read More |
4.2 | Domain Specific Design Methodologies | 17:00 - 18:30 | Konf. 6 | Read More |
4.3 | System Modelling for Simulation and Optimisation | 17:00 - 18:30 | Konf. 1 | Read More |
4.4 | Overcoming the Limitations of Worst-Case IC Design | 17:00 - 18:30 | Konf. 2 | Read More |
4.5 | Test: innovative infrastructures and ATPG techniques | 17:00 - 18:00 | Konf. 3 | Read More |
4.6 | Special Session: Securing Power-constrained System-on-Chips: Challenges and Opportunities | 17:00 - 18:30 | Konf. 4 | Read More |
4.7 | Adaptive Reliable Computing Using Memristive and Reconfigurable Hardware | 17:00 - 18:30 | Konf. 5 | Read More |