Date: Tuesday 20 March 2018
Time: 17:00 - 18:30
Location / Room: Konf. 4

Chair:
Mukhopadhyay Saibal, School of ECE, Georgia Institute of Technology, US

The power is the key constraint for modern System-on-Chip (SoC) design. After decade long research and development, the low-power circuit techniques and run-time power-management schemes are maturing at circuit, logic, and system levels. Now the SoCs face a new but critical design challenge: how to keep them secure - and techniques are being investigated in software and hardware to achieve this goal. This session is dedicated to study the critical, but often complex, interplay between power and security, in different aspects of design-for-security practices in SoCs.

Time	Label	Presentation Title Authors
17:00	4.6.1	ULTRA-LOW ENERGY CIRCUIT BUILDING BLOCKS FOR SECURITY TECHNOLOGIES Speaker: Sanu Mathew, Intel Corporation, US Authors: Sanu Mathew1, Sudhir Satpathy2, Vikram Suresh2 and Ram Krishnamurthy2 1Intel Labs, US; 2Intel Corporation, Hillsboro, US Abstract Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication in IoT platforms. This paper describes 3 designs that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve >0.99 min-entropy with 3pJ/bit energy-efficiency. Download Paper (PDF; Only available from the DATE venue WiFi)
17:15	4.6.2	EMBEDDED RANDOMNESS AND DATA DEPENDENCIES DESIGN PARADIGM: ADVANTAGES AND CHALLENGES Speaker: Itamar Levi, Université catholique de Louvain (UCL), Belgium, BE Authors: Itamar Levi, Alexander Fish and Osnat Keren, Faculty of Engineering, Bar-Ilan University, IL Abstract Information leakage through physical channels is a major hurdle in embedded hardware security. This paper overviews the three key factors in the embedded hardware security space, focusing on gray-box (bounded resources) power analysis attacks: the adversary's knowledge and abilities, the security metrics used by adversaries' and security evaluators and gate-level countermeasures. A new design paradigm, dubbed pAsynch, that utilizes internal signals and random signals to uniformly spread the information-carrying energy within the clock period in a specific way with a resolution below the band-width and noise-filtering abilities of advanced measurement equipment is introduced. The advantages and design challenges introduced by the pAsynch paradigm are discussed. Download Paper (PDF; Only available from the DATE venue WiFi)
17:40	4.6.3	EXPLOITING ON-CHIP POWER MANAGEMENT FOR SIDE-CHANNEL SECURITY Speaker: Saibal Mukhopadhyay, Georgia Institute of Technology, US Authors: Arvind Singh1, Monodeep Kar1, Sanu Mathew2, Anand Rajan2, Vivek De3 and Saibal Mukhopadhyay1 1Georgia Institute of Technology, US; 2Intel Labs, US; 3Intel Corporation, US Abstract The high-performance and energy-efficient encryption engines have emerged as a key component for modern System-On-Chip (SoC) in various platforms including servers, desktops, mobile, and IoT edge devices. A key bottleneck to secure operation of encryption engines is leakage of information through various side-channels. For example, an adversary can extract the secret key by performing statistical analysis on measured power and electromagnetic (EM) emission signatures generated by the hardware during encryption. Countermeasures to such side-channel attacks often come at high power, area, or performance overheads. Therefore, design of side-channel secure encryption engines is a critical challenge for high-performance and/or power-/energy efficient operations. This paper reviews that although low-power requirement imposes critical challenge for side-channel security, but circuit techniques traditionally developed for power management also present new opportunities for side-channel resistance. As a case study, we review the feasibility of using integrated voltage regulator and dynamic voltage frequency scaling normally used for efficient power management, for increasing power-side-channel resistance of AES engines. The hardware measurement results from test-chip fabricated in 130nm process are presented to demonstrate the impact of power management circuits on side-channel security. Download Paper (PDF; Only available from the DATE venue WiFi)
18:05	4.6.4	ENERGY-SECURE SWARM POWER MANAGEMENT Speaker: Pradip Bose, IBM Corporation, US Authors: Augusto Vega, Alper Buyuktosunoglu and Pradip Bose, IBM T. J. Watson Research, US Abstract We present a visionary concept of a distributed (or decentralized) power/thermal control mechanism that applies the bio-inspired artificial intelligence paradigm of swarm intelligence. The target use case is a future many-core processor. Preliminary results based on a swarm simulator are presented. The talk then addresses the challenge of making such power control systems secure against energy attacks - i.e. maliciously launched virus programs that are designed to disrupt the power control mechanism and cause performance shortfalls or even physical damage from over-heating.
18:30		End of session Exhibition Reception in Exhibition Area The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees.