4.5 Test: innovative infrastructures and ATPG techniques

Time	Label	Presentation Title Authors
17:00	4.5.1	PRE-ASSEMBLY TESTING OF INTERCONNECTS IN EMBEDDED MULTI-DIE INTERCONNECT BRIDGE (EMIB) DIES Speaker: Krishnendu Chakrabarty, Duke University, US Authors: Sudipta Mondal and Krishnendu Chakrabarty, Duke University, US Abstract The embedded multi-die interconnect bridge (EMIB) is an advanced packaging technology for 2.5D integration. This paper presents a bridge test architecture based on the proposed IEEE Std. P1838. The proposed test method enables access to interconnects at a pre-assembly stage by pairing the interconnects using metal shorts and probing on coarse-pitch C4 bumps. It can efficiently detect resistive-open and resistive-short defects in the bridge interconnects and micro-bumps. Simulation results are presented to evaluate the range of defects that can be detected by the proposed method. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	4.5.2	ON THE REUSE OF TIMING RESILIENT ARCHITECTURE FOR TESTING PATH DELAY FAULTS IN CRITICAL PATHS Speaker: Luciano Ost, University of Leicester, GB Authors: Felipe Kuentzer, Leonardo Juracy and Alexandre Amory, PUCRS University, BR Abstract Energy efficiency has become one of the most common and important demands for contemporary applications, increasing the desire for chips that operate near the threshold voltage levels, which unfortunately worsens the effects of process, voltage, and temperature (PVT) variability. An alternative solution to cope with PVT variations are the timing resilient architectures, such as the synchronous Razor family and the asynchronous Blade template, that rely on error detection logic (EDL) to detect and recover from timing violations. On one hand, the use of timing resilient architectures makes the path delay testing more challenging because it is not a matter of simple pass or fails the test. On the other hand, we show that timing resilient architectures, such as Blade, present opportunities to design low-cost online delay testing of the critical paths. Results show the area overhead and fault coverage using functional testing on a 32-bit MIPS CPU and a crypto core. Download Paper (PDF; Only available from the DATE venue WiFi)
17:45	4.5.3	CHARACTERIZATION OF POSSIBLY DETECTED FAULTS BY ACCURATELY COMPUTING THEIR DETECTION PROBABILITY Speaker: Jan Burchard, Mentor, a Siemens Business, DE Authors: Jan Burchard¹, Dominik Erb² and Bernd Becker¹ ¹University of Freiburg, DE; ²Infineon Technologies, DE Abstract With ever more complex and larger VLSI devices and higher and higher reliability requirements, high quality test with a large fault and defect coverage is becoming even more relevant. At the same time, when unspecified or unknown input values (X-values) have to be considered in a pattern, commercial ATPG tools are sometimes not capable of determining whether a fault can be tested - but there is at least a chance to detect the fault, as 0/X or 1/X could be propagated to at least one output. Consequently, these faults are considered to be possibly detected and often counted towards the overall fault coverage with a weighting factor. However, as the actual probability to detect these faults with the considered test pattern is not taken into account, this could lead to an over- or underestimation of their real fault coverage, falsifying the test results. We introduce a #SAT-based characterization algorithm for this class of faults. This new algorithm is, for the first time, able to accurately compute the detection probability for faults marked as possibly detected by state-of-the-art commercial tools. Our experimental results for the largest ITC'99 benchmarks as well as larger industrial-circuits show that our algorithm can accurately determine the detection probability for most of the possibly detected faults and also identify faults that are completely untestable or found with a probability of 100% irrespective of the assignment of the inputs with an X-value. Furthermore, they show that the detection probability is circuit dependent and consequently should not just be estimated by a simple weighting factor but requires a more in-depth evaluation. Otherwise, there is a high risk that the achieved results could clearly be to optimistic or pessimistic with regard to the real fault coverage. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	IP1-16, 728	A BOOLEAN MODEL FOR DELAY FAULT TESTING OF EMERGING DIGITAL TECHNOLOGIES BASED ON AMBIPOLAR DEVICES Speaker: Davide Bertozzi, DE - University of Ferrara, IT Authors: Marcello Dalpasso¹, Davide Bertozzi² and Michele Favalli² ¹DEI - UNiv. of Padova, IT; ²DE - Univ. of Ferrara, IT Abstract Emerging nanotechnonologies such as ambipolar carbon nanotube field effect transistors (CNTFETs) and silicon nanowire FETs (SiNFETs) provide ambipolar devices allowing the design of more complex logic primitives than those found in today's typical CMOS libraries. When switching, such devices show a behavior not seen in simpler CMOS and FinFET cells, making unsuitable the existing delay fault testing approaches. We provide a Boolean model of switching ambipolar devices to support delay fault testing of logic cells based on such devices both in Boolean and Pseudo-Boolean satisfiability engines. Download Paper (PDF; Only available from the DATE venue WiFi)
18:01	IP1-17, 845	ATPG POWER GUARDS: ON LIMITING THE TEST POWER BELOW THRESHOLD Speaker: Virendra Singh, Indian Institute of Technology Bombay, IN Authors: Rohini Gulve¹ and Virendra Singh² ¹Indian Institute of Technology Bombay, IN; ²IIT Bombay, IN Abstract Modern circuits with high performance and low power requirements impose strict constraints on manufacturing test generation, particularly on timing test. Delay test is used for performance grading of the circuit. During the application of the test, power consumption has to be less than the functional threshold value, in order to avoid yield loss. This work proposes a new direction to generate power safe test without any changes in DFT (design for testability) structure or existing CAD (computeraided design) tools. We propose a virtual wrapper circuitry around the circuit under test (CUT), for test generation purpose, which acts as a shield to obtain power safe vectors. The wrapper prohibits the generation of test vector if power consumption exceeds the threshold limits. We consider analytical power models for power analysis of candidate test vector patterns. Experiments performed on benchmark circuits show power safe test generation without coverage loss. Download Paper (PDF; Only available from the DATE venue WiFi)
18:02	IP2-1, 369	IN-GROWTH TEST FOR MONOLITHIC 3D INTEGRATED SRAM Speaker: Yixun Zhang, Shanghai Jiao Tong University, CN Authors: Pu Pang¹, Yixun Zhang¹, Tianjian Li¹, Sung Kyu Lim², Quan Chen¹, Xiaoyao Liang¹ and Li Jiang¹ ¹Shanghai Jiao Tong University, CN; ²Georgia Tech, US Abstract Monolithic three-dimensional integration (M3I) directly fabricates tiers of integrated circuits upon each other and provides millions of vertical interconnections with interlayer vias (ILVs). It thus brings higher integration density and communication capability compared with three-dimensional stacked integration (3D-SI). However, the Known-Good-Die problem haunting 3D-SI-a faulty tier causes the failure of the entire stack-also occurs in M3I. Lack of efficient test methodologies such as the pre-bond testing in 3D-SI, M3I may have a more significant yield drop and thus its cost may be unacceptable for main-stream adoption. This paper introduces a novel In-growth test method for M3I SRAM. We propose a novel Design-for- Test (DfT) methodology to enable the proposed In-growth test on cell-level partitioned incomplete SRAM cells. We also build a statistical model of cost and discover a prospective judgement to determine whether or not to stop the fabrication, in order to prevent from raising the cost of fabricating more tiers upon the irreparable tiers. We find that a "sweet point" exists in the judgement, which can minimize the overall cost. Experimental results show the effectiveness of our proposed test methodology. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00		End of session
18:30		Exhibition Reception in Exhibition Area The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees.

Time

Label

Presentation Title
Authors

17:00

4.5.1

PRE-ASSEMBLY TESTING OF INTERCONNECTS IN EMBEDDED MULTI-DIE INTERCONNECT BRIDGE (EMIB) DIES
Speaker:
Krishnendu Chakrabarty, Duke University, US
Authors:
Sudipta Mondal and Krishnendu Chakrabarty, Duke University, US
Abstract
The embedded multi-die interconnect bridge (EMIB) is an advanced packaging technology for 2.5D integration. This paper presents a bridge test architecture based on the proposed IEEE Std. P1838. The proposed test method enables access to interconnects at a pre-assembly stage by pairing the interconnects using metal shorts and probing on coarse-pitch C4 bumps. It can efficiently detect resistive-open and resistive-short defects in the bridge interconnects and micro-bumps. Simulation results are presented to evaluate the range of defects that can be detected by the proposed method.
Download Paper (PDF; Only available from the DATE venue WiFi)

17:30

4.5.2

ON THE REUSE OF TIMING RESILIENT ARCHITECTURE FOR TESTING PATH DELAY FAULTS IN CRITICAL PATHS
Speaker:
Luciano Ost, University of Leicester, GB
Authors:
Felipe Kuentzer, Leonardo Juracy and Alexandre Amory, PUCRS University, BR
Abstract
Energy efficiency has become one of the most common and important demands for contemporary applications, increasing the desire for chips that operate near the threshold voltage levels, which unfortunately worsens the effects of process, voltage, and temperature (PVT) variability. An alternative solution to cope with PVT variations are the timing resilient architectures, such as the synchronous Razor family and the asynchronous Blade template, that rely on error detection logic (EDL) to detect and recover from timing violations. On one hand, the use of timing resilient architectures makes the path delay testing more challenging because it is not a matter of simple pass or fails the test. On the other hand, we show that timing resilient architectures, such as Blade, present opportunities to design low-cost online delay testing of the critical paths. Results show the area overhead and fault coverage using functional testing on a 32-bit MIPS CPU and a crypto core.
Download Paper (PDF; Only available from the DATE venue WiFi)

17:45

4.5.3

CHARACTERIZATION OF POSSIBLY DETECTED FAULTS BY ACCURATELY COMPUTING THEIR DETECTION PROBABILITY
Speaker:
Jan Burchard, Mentor, a Siemens Business, DE
Authors:
Jan Burchard¹, Dominik Erb² and Bernd Becker¹
¹University of Freiburg, DE; ²Infineon Technologies, DE
Abstract
With ever more complex and larger VLSI devices and higher and higher reliability requirements, high quality test with a large fault and defect coverage is becoming even more relevant. At the same time, when unspecified or unknown input values (X-values) have to be considered in a pattern, commercial ATPG tools are sometimes not capable of determining whether a fault can be tested - but there is at least a chance to detect the fault, as 0/X or 1/X could be propagated to at least one output. Consequently, these faults are considered to be possibly detected and often counted towards the overall fault coverage with a weighting factor. However, as the actual probability to detect these faults with the considered test pattern is not taken into account, this could lead to an over- or underestimation of their real fault coverage, falsifying the test results. We introduce a #SAT-based characterization algorithm for this class of faults. This new algorithm is, for the first time, able to accurately compute the detection probability for faults marked as possibly detected by state-of-the-art commercial tools. Our experimental results for the largest ITC'99 benchmarks as well as larger industrial-circuits show that our algorithm can accurately determine the detection probability for most of the possibly detected faults and also identify faults that are completely untestable or found with a probability of 100% irrespective of the assignment of the inputs with an X-value. Furthermore, they show that the detection probability is circuit dependent and consequently should not just be estimated by a simple weighting factor but requires a more in-depth evaluation. Otherwise, there is a high risk that the achieved results could clearly be to optimistic or pessimistic with regard to the real fault coverage.
Download Paper (PDF; Only available from the DATE venue WiFi)

18:00

IP1-16, 728

A BOOLEAN MODEL FOR DELAY FAULT TESTING OF EMERGING DIGITAL TECHNOLOGIES BASED ON AMBIPOLAR DEVICES
Speaker:
Davide Bertozzi, DE - University of Ferrara, IT
Authors:
Marcello Dalpasso¹, Davide Bertozzi² and Michele Favalli²
¹DEI - UNiv. of Padova, IT; ²DE - Univ. of Ferrara, IT
Abstract
Emerging nanotechnonologies such as ambipolar carbon nanotube field effect transistors (CNTFETs) and silicon nanowire FETs (SiNFETs) provide ambipolar devices allowing the design of more complex logic primitives than those found in today's typical CMOS libraries. When switching, such devices show a behavior not seen in simpler CMOS and FinFET cells, making unsuitable the existing delay fault testing approaches. We provide a Boolean model of switching ambipolar devices to support delay fault testing of logic cells based on such devices both in Boolean and Pseudo-Boolean satisfiability engines.
Download Paper (PDF; Only available from the DATE venue WiFi)

18:01

IP1-17, 845

ATPG POWER GUARDS: ON LIMITING THE TEST POWER BELOW THRESHOLD
Speaker:
Virendra Singh, Indian Institute of Technology Bombay, IN
Authors:
Rohini Gulve¹ and Virendra Singh²
¹Indian Institute of Technology Bombay, IN; ²IIT Bombay, IN
Abstract
Modern circuits with high performance and low power requirements impose strict constraints on manufacturing test generation, particularly on timing test. Delay test is used for performance grading of the circuit. During the application of the test, power consumption has to be less than the functional threshold value, in order to avoid yield loss. This work proposes a new direction to generate power safe test without any changes in DFT (design for testability) structure or existing CAD (computeraided design) tools. We propose a virtual wrapper circuitry around the circuit under test (CUT), for test generation purpose, which acts as a shield to obtain power safe vectors. The wrapper prohibits the generation of test vector if power consumption exceeds the threshold limits. We consider analytical power models for power analysis of candidate test vector patterns. Experiments performed on benchmark circuits show power safe test generation without coverage loss.
Download Paper (PDF; Only available from the DATE venue WiFi)

18:02

IP2-1, 369

IN-GROWTH TEST FOR MONOLITHIC 3D INTEGRATED SRAM
Speaker:
Yixun Zhang, Shanghai Jiao Tong University, CN
Authors:
Pu Pang¹, Yixun Zhang¹, Tianjian Li¹, Sung Kyu Lim², Quan Chen¹, Xiaoyao Liang¹ and Li Jiang¹
¹Shanghai Jiao Tong University, CN; ²Georgia Tech, US
Abstract
Monolithic three-dimensional integration (M3I) directly fabricates tiers of integrated circuits upon each other and provides millions of vertical interconnections with interlayer vias (ILVs). It thus brings higher integration density and communication capability compared with three-dimensional stacked integration (3D-SI). However, the Known-Good-Die problem haunting 3D-SI-a faulty tier causes the failure of the entire stack-also occurs in M3I. Lack of efficient test methodologies such as the pre-bond testing in 3D-SI, M3I may have a more significant yield drop and thus its cost may be unacceptable for main-stream adoption. This paper introduces a novel In-growth test method for M3I SRAM. We propose a novel Design-for- Test (DfT) methodology to enable the proposed In-growth test on cell-level partitioned incomplete SRAM cells. We also build a statistical model of cost and discover a prospective judgement to determine whether or not to stop the fabrication, in order to prevent from raising the cost of fabricating more tiers upon the irreparable tiers. We find that a "sweet point" exists in the judgement, which can minimize the overall cost. Experimental results show the effectiveness of our proposed test methodology.
Download Paper (PDF; Only available from the DATE venue WiFi)

18:00

End of session

18:30

Exhibition Reception in Exhibition Area
The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees.