2.7 Special Session: Spintronics based New Computing Paradigms and Applications

Time	Label	Presentation Title Authors
11:30	2.7.1	MAIN MEMORY ORGANIZATION TRADE-OFFS WITH DRAM AND STT-MRAM OPTIONS BASED ON EXTENDED GEM5/NVMAIN SIMULATION FRAMEWORK Speaker: Manu Komalan, IMEC, BE Authors: Manu Komalan¹, Oh Hyung Rock¹, Matthias Hartmann¹, Sushil Sakhare¹, Christian Tenllado², Jose Ignacio Gomez², Gouri Sankar Kar¹, Arnaud Furnemont¹, Francky Catthoor¹, Sophiane Senni³, David Novo⁴, Abdoulaye Gamatie⁵ and Lionel Torres⁶ ¹IMEC, BE; ²Universidad Complutense de Madrid (UCM), ES; ³LIRMM, FR; ⁴French National Centre for Scientific Research (CNRS), FR; ⁵CNRS LIRMM / University of Montpellier, FR; ⁶University of Montpellier, FR Abstract Current main memory organizations in embedded and mobile application systems are DRAM dominated. The everincreasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other associated challenges like refresh provides some undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STTMRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multi-core architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. Download Paper (PDF; Only available from the DATE venue WiFi)
11:45	2.7.2	EXPLORING THE OPPORTUNITY OF IMPLEMENTING NEUROMORPHIC COMPUTING SYSTEMS WITH SPINTRONIC DEVICES Speaker: Hai Li, Duke University, US Authors: Bonan Yan¹, Fan Chen¹, Yaojun Zhang², Chang Song¹, Hai (Helen) Li³ and Yiran Chen¹ ¹Duke University, US; ²University of Pittsburgh, US; ³Duke University/TUM-IAS, US Abstract Many cognitive algorithms such as neural networks cannot be efficiently executed by von Neumann architectures, the performance of which is constrained by the memory wall between microprocessor and memory hierarchy. Hence, researchers started to investigate new computing paradigms such as neuromorphic computing that can adapt their structure to the topology of the algorithms and accelerate their executions. New computing units have been also invented to support this effort by leveraging emerging nano-devices. In this work, we will discuss the opportunity of implementing neuromorphic computing systems with spintronic devices. We will also provide insights on how spintronic devices fit into different part of neuromorphic computing systems. Approaches to optimize the circuits are also discussed. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	2.7.3	SPINTRONIC NORMALLY-OFF HETEROGENEOUS SYSTEM-ON-CHIP DESIGN Speaker: Rajendra Bishnoi, Karlsruhe Institute of Technology, DE Authors: Anteneh Gebregiorgis, Rajendra Bishnoi and Mehdi Tahoori, Karlsruhe Institute of Technology, DE Abstract One of the major challenges in device down-scaling is the increase in the leakage power, which becomes a major component in the overall system power consumption. One way to deal with this problem is to introduce the concept of normally-off instant-on computing architectures, in which the system components are powered off when they are not active. An associated challenge is the back-up and restoration of system states, which in turn can introduce additional costs that erode some of the gains. A promising alternative is the use of non-volatile storage elements in the System-on-Chip (SoC) design which can instantly power-down and retain their values. In this work, we show how we can design a normally-off SoC by exploiting non-volatile latches, flip-flops and registers. The idea is to design a hybrid architecture containing conventional CMOS bistables as well as different flavors of spintronic-based non-volatile storage elements, to balance performance, area, and energy efficiency. Download Paper (PDF; Only available from the DATE venue WiFi)
12:15	2.7.4	MAGNETIC SKYRMIONS FOR FUTURE POTENTIAL MEMORY AND LOGIC APPLICATIONS: ALTERNATIVE INFORMATION CARRIERS Speaker and Author: Wang Kang, Beihang University, CN Abstract Magnetic skyrmions are swirling topological configurations, which are mostly induced by chiral interactions between atomic spins in non-centrosymmetric magnetic bulks or in thin films with broken inversion symmetry. They hold promise as information carriers in future ultra-dense, low-power memory and logic devices owing to the nanocale size and extremely low spin-polarized currents needed to move them. To date, an intense research effort has led to the identification, creation/annihilation, motion and manipulation of skyrmions at room temperature. Meanwhile, a rich variety of skyrmion-based device concepts and prototypes have been proposed, indicating the considerable potential of magnetic skyrmions in future electronic applications. However, current studies mainly focus on physical or principle investigations, whereas the electrical design methodology, implementation and evaluations are still lacking. In this paper, we will bring the readers in the "design, automation and test (DAT) society" the current status and outlook of skyrmions in relation to future potential racetrack memory and neuromorphic computing applications. Most importantly, we also want to evoke the effort from the DAT society to address the challenges, e.g., all-electrical manipulation of skyrmions at room temperature, for the research and development of practical skyrmion-based electronics. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	2.7.5	NOVEL APPLICATION OF SPINTRONICS IN COMPUTING, SENSING, STORAGE AND CYBERSECURITY Speaker: Anirudh Iyengar, Pennsylvania State University, US Author: Swaroop Ghosh, Pennsylvania State University, US Abstract With conventional Von Neumann computing struggling to match the energy-efficiency of biological systems, there is pressing need to explore alternative computing models. CMOS switches, although universal, fails to offer additional features to meet this end goal. Recent experimental studies have revealed that spintronics possess many promising features that can not only enable non Von Neumann compute models but also high-density storage, sensing of environmental parameters and protection from cybersecurity threats. This talk will provide an in-depth study of spintronics and its relation to these novel aspects from device, circuit and system standpoint. Download Paper (PDF; Only available from the DATE venue WiFi)
12:45	2.7.6	LARGE SCALE, HIGH DENSITY INTEGRATION OF ALL SPIN LOGIC Speaker and Author: Jacques-Olivier Klein, C2N, Univ. Paris-Sud, FR Abstract Spintronics brings new features that make it a viable candidate technology to implement non-conventional processing for new computing paradigms in an efficient way. The first milestone of the spintronics roadmap was the fabrication of hybrid systems where the data processing relies mostly on charge-based electronics devices (CMOS), while the memory hierarchy is partially or totally replaced by MRAM. In the next step, spintronics can also be used for data processing, still in conjunction with CMOS. Nevertheless, replacing all the processing by pure spintronic circuits, without any charge current, remains the ultimate objective of spintronics. All spin logic (ASL) paves the way towards that goal, even if some CMOS control circuits are still necessary. However, as ASL does not rely on the same computing principle as CMOS, it is necessary to address some specific issues. Pure spin current propagates in every direction, including backwards in the presence of multiple inputs; and is divided when crossings are encountered. It combines mainly linearly, while logic operations require non-linear binary decisions. Interconnect between logic gates requires directionality from inputs to outputs, and fanout with negligible signal attenuation. In this context, we develop new strategies for ASL modeling and logic design. We propose an architecture and a design strategy based on a high-density array to address the specific issues of directionality, attenuation and linearity. Moreover, the feasibility is supported through the modeling and the simulation of its basic block. This implies modularity to simulate complex circuits, even when they are ahead of today's experimental demonstrations. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00		End of session Lunch Break in Großer Saal and Saal 1 Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 21, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 22, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00 Keynote Lecture in "Saal 2" 13:20 - 13:50 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

11:30

2.7.1

MAIN MEMORY ORGANIZATION TRADE-OFFS WITH DRAM AND STT-MRAM OPTIONS BASED ON EXTENDED GEM5/NVMAIN SIMULATION FRAMEWORK
Speaker:
Manu Komalan, IMEC, BE
Authors:
Manu Komalan¹, Oh Hyung Rock¹, Matthias Hartmann¹, Sushil Sakhare¹, Christian Tenllado², Jose Ignacio Gomez², Gouri Sankar Kar¹, Arnaud Furnemont¹, Francky Catthoor¹, Sophiane Senni³, David Novo⁴, Abdoulaye Gamatie⁵ and Lionel Torres⁶
¹IMEC, BE; ²Universidad Complutense de Madrid (UCM), ES; ³LIRMM, FR; ⁴French National Centre for Scientific Research (CNRS), FR; ⁵CNRS LIRMM / University of Montpellier, FR; ⁶University of Montpellier, FR
Abstract
Current main memory organizations in embedded and mobile application systems are DRAM dominated. The everincreasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other associated challenges like refresh provides some undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STTMRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multi-core architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture.
Download Paper (PDF; Only available from the DATE venue WiFi)

11:45

2.7.2

EXPLORING THE OPPORTUNITY OF IMPLEMENTING NEUROMORPHIC COMPUTING SYSTEMS WITH SPINTRONIC DEVICES
Speaker:
Hai Li, Duke University, US
Authors:
Bonan Yan¹, Fan Chen¹, Yaojun Zhang², Chang Song¹, Hai (Helen) Li³ and Yiran Chen¹
¹Duke University, US; ²University of Pittsburgh, US; ³Duke University/TUM-IAS, US
Abstract
Many cognitive algorithms such as neural networks cannot be efficiently executed by von Neumann architectures, the performance of which is constrained by the memory wall between microprocessor and memory hierarchy. Hence, researchers started to investigate new computing paradigms such as neuromorphic computing that can adapt their structure to the topology of the algorithms and accelerate their executions. New computing units have been also invented to support this effort by leveraging emerging nano-devices. In this work, we will discuss the opportunity of implementing neuromorphic computing systems with spintronic devices. We will also provide insights on how spintronic devices fit into different part of neuromorphic computing systems. Approaches to optimize the circuits are also discussed.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:00

2.7.3

SPINTRONIC NORMALLY-OFF HETEROGENEOUS SYSTEM-ON-CHIP DESIGN
Speaker:
Rajendra Bishnoi, Karlsruhe Institute of Technology, DE
Authors:
Anteneh Gebregiorgis, Rajendra Bishnoi and Mehdi Tahoori, Karlsruhe Institute of Technology, DE
Abstract
One of the major challenges in device down-scaling is the increase in the leakage power, which becomes a major component in the overall system power consumption. One way to deal with this problem is to introduce the concept of normally-off instant-on computing architectures, in which the system components are powered off when they are not active. An associated challenge is the back-up and restoration of system states, which in turn can introduce additional costs that erode some of the gains. A promising alternative is the use of non-volatile storage elements in the System-on-Chip (SoC) design which can instantly power-down and retain their values. In this work, we show how we can design a normally-off SoC by exploiting non-volatile latches, flip-flops and registers. The idea is to design a hybrid architecture containing conventional CMOS bistables as well as different flavors of spintronic-based non-volatile storage elements, to balance performance, area, and energy efficiency.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:15

2.7.4

MAGNETIC SKYRMIONS FOR FUTURE POTENTIAL MEMORY AND LOGIC APPLICATIONS: ALTERNATIVE INFORMATION CARRIERS
Speaker and Author:
Wang Kang, Beihang University, CN
Abstract
Magnetic skyrmions are swirling topological configurations, which are mostly induced by chiral interactions between atomic spins in non-centrosymmetric magnetic bulks or in thin films with broken inversion symmetry. They hold promise as information carriers in future ultra-dense, low-power memory and logic devices owing to the nanocale size and extremely low spin-polarized currents needed to move them. To date, an intense research effort has led to the identification, creation/annihilation, motion and manipulation of skyrmions at room temperature. Meanwhile, a rich variety of skyrmion-based device concepts and prototypes have been proposed, indicating the considerable potential of magnetic skyrmions in future electronic applications. However, current studies mainly focus on physical or principle investigations, whereas the electrical design methodology, implementation and evaluations are still lacking. In this paper, we will bring the readers in the "design, automation and test (DAT) society" the current status and outlook of skyrmions in relation to future potential racetrack memory and neuromorphic computing applications. Most importantly, we also want to evoke the effort from the DAT society to address the challenges, e.g., all-electrical manipulation of skyrmions at room temperature, for the research and development of practical skyrmion-based electronics.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

2.7.5

NOVEL APPLICATION OF SPINTRONICS IN COMPUTING, SENSING, STORAGE AND CYBERSECURITY
Speaker:
Anirudh Iyengar, Pennsylvania State University, US
Author:
Swaroop Ghosh, Pennsylvania State University, US
Abstract
With conventional Von Neumann computing struggling to match the energy-efficiency of biological systems, there is pressing need to explore alternative computing models. CMOS switches, although universal, fails to offer additional features to meet this end goal. Recent experimental studies have revealed that spintronics possess many promising features that can not only enable non Von Neumann compute models but also high-density storage, sensing of environmental parameters and protection from cybersecurity threats. This talk will provide an in-depth study of spintronics and its relation to these novel aspects from device, circuit and system standpoint.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:45

2.7.6

LARGE SCALE, HIGH DENSITY INTEGRATION OF ALL SPIN LOGIC
Speaker and Author:
Jacques-Olivier Klein, C2N, Univ. Paris-Sud, FR
Abstract
Spintronics brings new features that make it a viable candidate technology to implement non-conventional processing for new computing paradigms in an efficient way. The first milestone of the spintronics roadmap was the fabrication of hybrid systems where the data processing relies mostly on charge-based electronics devices (CMOS), while the memory hierarchy is partially or totally replaced by MRAM. In the next step, spintronics can also be used for data processing, still in conjunction with CMOS. Nevertheless, replacing all the processing by pure spintronic circuits, without any charge current, remains the ultimate objective of spintronics. All spin logic (ASL) paves the way towards that goal, even if some CMOS control circuits are still necessary. However, as ASL does not rely on the same computing principle as CMOS, it is necessary to address some specific issues. Pure spin current propagates in every direction, including backwards in the presence of multiple inputs; and is divided when crossings are encountered. It combines mainly linearly, while logic operations require non-linear binary decisions. Interconnect between logic gates requires directionality from inputs to outputs, and fanout with negligible signal attenuation. In this context, we develop new strategies for ASL modeling and logic design. We propose an architecture and a design strategy based on a high-density array to address the specific issues of directionality, attenuation and linearity. Moreover, the feasibility is supported through the modeling and the simulation of its basic block. This implies modularity to simulate complex circuits, even when they are ahead of today's experimental demonstrations.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:00

End of session
Lunch Break in Großer Saal and Saal 1

Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD).

Lunch Breaks (Großer Saal + Saal 1)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 20, 2018