Home

Technical Programme Committee 2018

Printer-friendly version PDF version

Track D: Design Methods and Tools (click to open)

This track addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Ayse Coskun, Boston University, US, Contact

Topics

D1 System Specification and Modeling (click to open)

Chair: Ingo Sander, KTH Royal Institute of Technology, SE, Contact

Co-Chair: Andreas Gerstlauer, The University of Texas at Austin, US, Contact

Topic Members (click to open)

  • Patricia Balbastre, Universtat Politecnica de Valencia, ES, Contact
  • Michael Huebner, Ruhr-University Bochum, DE, Contact
  • Gianluca Palermo, Politecnico di Milano, IT, Contact
  • Laurence Pierre, Univ. Grenoble Alpes, TIMA Lab., FR, Contact
  • Martin Radetzki, University of Stuttgart, DE, Contact
  • Jürgen Teich, University of Erlangen-Nuremberg, DE, Contact

Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; concurrency and communication models; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; performance modeling; timing analysis; predictive and learning-based models; system-level platform and architecture models and simulation.

D2 System Design, High-Level Synthesis, and Optimization (click to open)

Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact

Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact

Topic Members (click to open)

  • Lars Bauer, Karlsruhe Institute of Technology, DE, Contact
  • Kiyoung Choi, Seoul National University, KR, Contact
  • Michael Glaß, Ulm University, DE, Contact
  • Soonhoi Ha, Seoul National University, KR, Contact
  • Dirk Koch, University of Manchester, GB, Contact
  • Luciano Lavagno, Politecnico di Torino, IT, Contact
  • David Novo, French National Centre for Scientific Research (CNRS), FR, Contact
  • Sudeep Pasricha, Colorado State University, US, Contact
  • Donatella Sciuto, Politecnico di Milano, IT, Contact
  • Todor Stefanov, Leiden University, NL, Contact
  • jason xue, City University of Hong Kong, HK, Contact
  • Daniel Ziener, University of Twente, NL, Contact

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; multi-objective optimization techniques (e.g., performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.

D3 System Simulation and Validation (click to open)

Chair: Valeria Bertacco, University of Michigan, US, Contact

Co-Chair: Graziano Pravadelli, University of Verona, IT, Contact

Topic Members (click to open)

  • Anupam Chattopadhyay, Nanyang Technological University, SG, Contact
  • Flavio M. de Paula, IBM Corporation, US, Contact
  • Daniel Grosse, University of Bremen/DFKI, DE, Contact
  • Tushar Krishna, Georgia Institute of Technology, US, Contact
  • Florian Letombe, Synopsys, FR, Contact
  • Katell Morin-Allory, TIMA Laboratory, FR, Contact
  • Jaan Raik, Tallinn university of Technology, EE, Contact
  • Sandip Ray, University of Florida, US, Contact
  • Daniel Schostak, ARM Ltd, GB, Contact
  • Shobha Vasudevan, UIUC, US, Contact
  • Sara Vinco, Politecnico di Torino, IT, Contact
  • Li-C. Wang, UCSB, US, Contact

Simulation-based and semi-formal validation and verification of SoCs, MPSoCs, and emerging architectures at any level (from system to circuits), including digital, analog, interconnect or mixed-signal components; testbench and assertion generation and qualification; checker synthesis and optimization; multi-domain and mixed-critical simulation techniques; acceleration-driven and emulation-based approaches for verification and validation; simulation-based pre- and post-silicon diagnosis and debugging solutions; validation and verification for IoT and cloud infrastructures; validation and verification using artificial intelligence or machine learning techniques.

D4 Formal Methods and Verification (click to open)

Chair: Christoph Scholl, University Freiburg, DE, Contact

Co-Chair: Armin Biere, Johannes Kepler University Linz, AT, Contact

Topic Members (click to open)

  • Roderick Bloem, Graz University of TEchnology, AT, Contact
  • Gianpiero Cabodi, Politecnico di Torino, IT, Contact
  • Alessandro Cimatti, Fondazione Bruno Kessler, IT, Contact
  • Daniel Kroening, University of Oxford, GB, Contact
  • Julien Schmaltz, Eindhoven University of Technology, NL, Contact
  • Daryl Stewart, ARM, GB, Contact
  • Dominik Stoffel, TU Kaiserslautern, DE, Contact
  • Christoph M. Wintersteiger, Microsoft Research, GB, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, decomposition techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

Chair: Andrè Ivanov, University of British Columbia, CA, Contact

Co-Chair: Georges Gielen, KU Leuven, BE, Contact

Topic Members (click to open)

  • Manuel Barragan, TIMA Laboratory, FR, Contact
  • Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact
  • Deukhyoun Heo, Washington State University, US, Contact
  • Nuno Horta, Instituto de Telecomunicações /Instituto Superior Técnico – Universidade de Lisboa, PT, Contact
  • Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES, Contact
  • Mark Po-Hung Lin, National Chung Cheng University, TW, Contact
  • Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR, Contact
  • Shahriar Mirabbasi, University of British Columbia, CA, Contact
  • Manoj Sachdev, University of Waterloo, CA, Contact
  • Shreyas Sen, ECE, Purdue University, US, Contact
  • Gerd Vandersteen, Vrije Universiteit Brussel - dept. ELEC, BE, Contact

Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; HW description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.

DT6 Design and Test of Secure Systems (click to open)

Chair: Ilia Polian, University of Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

Topic Members (click to open)

  • Aydin Aysu, North Carolina State University, US, Contact
  • Wayne Burleson, U Massachusetts Amherst, US, Contact
  • Jean Luc Danger, Télécom ParisTech, FR, Contact
  • Wieland Fischer, Infineon Technologies, DE, Contact
  • Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US, Contact
  • Mike Hutter, Cryptography Research Inc., US, Contact
  • Farinaz Koushanfar, University of California San Diego, US, Contact
  • Roel Maes, Intrinsic-ID, NL, Contact
  • Yiorgos Makris, The University of Texas at Dallas, US, Contact
  • Nele Mentens, KU Leuven, BE, Contact
  • David Oswald, School of Computer Science, University of Birmingham, GB, Contact
  • Francesco Regazzoni, ALaRI, CH, Contact
  • Kazuo Sakiyama, The University of Electro-Communications, JP, Contact
  • Matthias Sauer, University of Freiburg, DE, Contact
  • Mark M. Teranipoor, University of Florida, US, Contact
  • Marc Witteman, Riscure, NL, Contact

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks.

D7 Network on Chip (click to open)

Chair: Luca Carloni, Columbia University, US, Contact

Co-Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Masoud Daneshtalab, KTH Royal Institute of Technology, SE, Contact
  • Ravi Iyer, Intel, US, Contact
  • Axel Jantsch, TU Wien, AT, Contact
  • Ajay Joshi, Boston University, US, Contact
  • John Kim, KAIST, KR, Contact
  • Romain Lemaire, CEA-Leti, FR, Contact
  • Fernando Moraes, PUCRS University, BR, Contact
  • Gabriela Nicolescu, Ecole Polytechnique de Montréal, CA, Contact
  • Li-Shiuan Peh, Professor, National University of Singapore, SG, Contact
  • Jiang Xu, Hong Kong University of Science and Technology, HK, Contact
  • Davide Zoni, Politecnico di Milano, IT, Contact

Architecture, design methodologies, and modeling techniques for NoC, including: topology, switching, routing and flow control; NoC service frameworks for Quality-of-Service, security, and power management; techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; integration of external interfaces or memory controllers with NoCs; cache-coherent NoCs; HW-SW communication abstractions; component-based modeling; platform-based design and methodologies; NoC design space exploration frameworks; programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

D8 Architectural and Microarchitectural Design (click to open)

Chair: Eli Bozorgzadeh, Univ. of California, Irvine, US, Contact

Co-Chair: Francisco Cazorla, Barcelona Supercomputing Center and IIIA-CSIC, ES, Contact

Topic Members (click to open)

  • Jung Ho Ahn, Seoul National University, KR, Contact
  • Mladen Berekovic, TU Braunschweig, DE, Contact
  • Ramon Canal, Universitat Politècnica de Catalunya, ES, Contact
  • Jeronimo Castrillon, TU Dresden, DE, Contact
  • Reetuparna Das, Michigan, US, Contact
  • Giuseppe Desoli, STMicroelectronics, IT, Contact
  • Zhenman Fang, Xilinx/UCLA, US, Contact
  • Houman Homayoun, George Mason University, US, Contact
  • Lei Ju, Shandong University, CN, Contact
  • Georgios Keramidas, Think Silicon S.A./Technological Educational Institute of Western Greece, GR, Contact
  • Samira Khan, University of Virginia, US, Contact
  • Eren Kursun, IEEE, US, Contact
  • Andrea Marongiu, IIS, ETH Zurich, IT, Contact
  • Gokhan Memik, Northwestern University, US, Contact
  • Roxana Rusitoru, ARM Ltd., GB, Contact
  • Toshinori Sato, Fukuoka University, JP, Contact
  • Olivier Sentieys, INRIA, FR, Contact
  • Zili Shao, The Chinese University of Hong Kong, HK, Contact
  • Antonino Tumeo, Pacific Northwest National Laboratory, US, Contact
  • Sotirios Xydis, National Technical University of Athens, GR, Contact

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, safety, and timing predictability.

D9 Power Modeling, Low-Power Design, and Power-Aware Optimization (click to open)

Chair: Alberto Macii, Politecnico di Torino, IT, Contact

Co-Chair: Naehyuck Chang, KAIST, KR, Contact

Topic Members (click to open)

  • Paolo Amato, Micron, IT, Contact
  • Nadine Azemard, LIRMM, FR, Contact
  • Andrea Bartolini, University of Bologna, IT, Contact
  • Andrea Calimera, Politecnico di Torino, IT, Contact
  • Jae-Joon Kim, Pohang University of Science and Techology, KR, Contact
  • Hiroshi Nakamura, The University of TOKYO, JP, Contact
  • Alberto Nannarelli, Technical University, DK, Contact
  • Salvatore Rinaudo, STMicroelectronics, IT, Contact
  • Johanna Sepulveda, TU Munich, DE, Contact
  • Donghwa Shin, Department of Smart Systems Software, Soongsil University, KR, Contact
  • Sheldon Tan, University of California at Riverside, US, Contact
  • Pascal Vivet, CEA-Leti, FR, Contact
  • Yanzhi Wang, University of Southern California, US, Contact
  • Shusuke Yoshimoto, Osaka University, JP, Contact

Algorithms, techniques, and tools for modeling, estimating, or optimizing power consumption of electronic systems, applicable at all levels of the design (HW, SW, or system level), including: dynamic power management; leakage current minimization; design flows and circuit architectures for ultra-low power consumption; energy harvesting; battery modeling and design.

D10 Temperature and Variability-Aware System Design and Optimization (click to open)

Chair: Giovanni Ansaloni, USI Lugano, CH, Contact

Co-Chair: Jose L. Ayala, Complutense University of Madrid, ES, Contact

Topic Members (click to open)

  • Georgios Karakonstantis, Queen's University Belfast, GB, Contact
  • Mohamed M. Sabry, Nanyang Technological University, SG, Contact
  • Vasilis Pavlidis, University of Manchester, GB, Contact
  • Qinru Qiu, Syracuse University, US, Contact
  • Rene van Leuken, Delft University of Technology, NL, Contact
  • Pieter Weckx, IMEC, BE, Contact

Methods, techniques, and architectures for counteracting circuit and system variability due to manufacturing process, temperature, or aging effects, including: design-time and runtime temperature, variability, and reliability management of SoCs and multi-core platforms (both at HW and SW level); modeling and optimization approaches for manufacturing-induced or temperature variations; modeling and optimization methods targeting degradation mechanisms in emerging integration and manufacturing technologies (e.g., 3D stacking).

D11 Reconfigurable Computing (click to open)

Chair: Fabrizio Ferrandi, Politecnico di Milano, IT, Contact

Co-Chair: Florent de Dinechin, INSA-Lyon, FR, Contact

Topic Members (click to open)

  • Michaela Blott, Xilinx, IE, Contact
  • Philip Brisk, University of California, Riverside, US, Contact
  • Alessandro Cilardo, University of Naples Federico II, IT, Contact
  • Suhaib A. Fahmy, University of Warwick, GB, Contact
  • Ryan Kastner, University of California, San Diego, US, Contact
  • Bogdan Pasca, Intel, FR, Contact
  • Marco Platzner, University of Paderborn, DE, Contact
  • Hayden So, The University of Hong Kong, HK, Contact

Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; reconfigurable computing for high-performance computers and data centers; statically and dynamically reconfigurable and reprogrammable systems and components; FPGA architectures and FPGA circuit design; design methods and tools for reconfigurable computing and communication systems.

D12 Logical and Physical Analysis and Design (click to open)

Chair: Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT, Contact

Co-Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact

Topic Members (click to open)

  • Luca Amaru, Synopsys, US, Contact
  • Anna Bernasconi, Universita' di Pisa, IT, Contact
  • Luca Daniel, M.I.T., US, Contact
  • Patrick Groeneveld, DAC, US, Contact
  • Igor L. Markov, University of Michigan, US, Contact
  • Jose Monteiro, INESC-ID, Técnico, U Lisboa, PT, Contact
  • Rajeev Murgai, Synopsys India Pvt. Ltd., IN, Contact
  • Farhana Sheikh, Intel Corporation, US, Contact
  • Mathias Soeken, Integrated System Laboratory – EPFL, CH, Contact
  • Wenjian Yu, Tsinghua University, CN, Contact

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D13 Emerging Technologies for Future Computing (click to open)

Chair: Aida Todri-Sanial, CNRS-LIRMM/University of Montpellier, FR, Contact

Co-Chair: Walter Weber, NaMLab gGmbH and CfAED, DE, Contact

Topic Members (click to open)

  • Yuanqing Cheng, Beihang University, CN, Contact
  • Elena Gnani, University of Bologna, IT, Contact
  • Mariagrazia Graziano, Politecnico di Torino, IT, Contact
  • Marc Heyns, IMEC, BE, Contact
  • Subhasish Mitra, Stanford University, US, Contact
  • Arijit Raychowdhury, Georgia Institute of Technology, US, Contact
  • Max Shulaker, MIT, US, Contact

Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).

D14 Emerging Technologies for Future Memories (click to open)

Chair: Jean-Michel Portal, Aix-Marseille University, FR, Contact

Co-Chair: Pierre-Emmanuel Gaillardon, University of Utah, US, Contact

Topic Members (click to open)

  • Bastien Giraud, CEA LETI, FR, Contact
  • Arne Heittman, RWTH Aachen University, DE, Contact
  • Yu Hua, Huazhong University of Science and Technology, CN, Contact
  • Kyungsu Kang, Samsung, KR, Contact
  • Dhireesha Kudithipudi, Rochester Institute of Technology, US, Contact
  • Shahar Kvatinsky, Technion, IL, Contact
  • Luca Larcher, Università di Modena e Reggio Emilia, IT, Contact
  • Pascal Meinerzhagen, Intel Circuit Research Lab, US, Contact
  • Tajana Rosing, University of California, San Diego, US, Contact
  • Stefan Slesazeck, NaMLab gGmbH, DE, Contact
  • Naveen Verma, Princeton University, US, Contact
  • Chengmo Yang, University of Delaware, US, Contact
  • Hao Yu, Southern University of Science and Technology, China, CN, Contact
  • Weisheng Zhao, Beihang University, CN, Contact

Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.

Track A: Application Design (click to open)

This track is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow's silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topics

A1 Power-efficient and Sustainable Computing (click to open)

Chair: Muhammad Shafique, TU Wien, AT, Contact

Co-Chair: Baris Aksanli, San Diego State University, US, Contact

Topic Members (click to open)

  • Luca Benini, University Of Bologna, IT, Contact
  • Jungwook Choi, IBM T. J. Watson Research Center, US, Contact
  • william fornaciari, Politecnico di Milano - DEIB, IT, Contact
  • Hai (Helen) Li, Duke University/TUM-IAS, US, Contact
  • Saibal Mukhopadhyay, Georgia Institute of Technology, US, Contact
  • Umit Ogras, Arizona State University, US, Contact
  • Semeen Rehman, TU Wien, AT, Contact
  • Alexandre Valentian, CEA LETI, FR, Contact
  • Chia-Lin Yang, National Taiwan University, TW, Contact

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.

A2 Communication, Consumer and Multimedia Systems (click to open)

Chair: Steffen Paul, University Bremen, DE, Contact

Co-Chair: Theocharis Theocharides, University of Cyprus, CY, Contact

Topic Members (click to open)

  • Baghdadi Amer, Institut Mines-Telecom; Telecom Bretagne; CNRS Lab-STICC, FR, Contact
  • Christos Bouganis, Imperial College London, GB, Contact
  • Christian Drewes, Intel, DE, Contact
  • Ioannis Papaefstathiou, Technical university of Crete, GR, Contact

Application design experiences for communication, multimedia, and consumer systems such as smartphones, smart-books/tablets, photo and video cameras, including: digital integrated circuit design of flexible baseband processing systems; intellectual properties for wireless communication, design challenges for SW-defined/cognitive radio systems; embedded systems design in the field of audio, video, and computer vision domains; embedded IP and processor design; sensor networks for dense IoT environments (e.g., Industry 4.0 or smart homes/cities).

A3 Automotive Systems and Smart Energy Systems (click to open)

Chair: Davide Brunelli, University of Trento, IT, Contact

Co-Chair: Sebastian Steinhorst, Technical University of Munich, DE, Contact

Topic Members (click to open)

  • Dip Goswami, Eindhoven University of Technology, NL, Contact
  • Paul Havinga, University of Twente, NL, Contact
  • Massimo Poncino, Politecnico di Torino, IT, Contact
  • Bart Vermeulen, NXP Semiconductors, NL, Contact
  • Haibo Zeng, Virginia Tech, US, Contact
  • Dirk Ziegenbein, Robert Bosch GmbH, DE, Contact

Design experiences for automotive systems, energy scavenging and harvesting for energy-neutral embedded systems, smart energy systems (from small to microgrid), and related applications. Topics of interest include: integrated circuits; MEMS; integrated sensors and transducers; RF architectures; in-vehicle networks; systems for electric vehicles; networks of systems; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; hardware solutions for runtime system management such as self-diagnostics and repair; energy generation; novel energy harvesting, battery management, and renewable energy subsystems; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Healthcare, Wellness, and Assistive Technologies (click to open)

Chair: Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT, Contact

Co-Chair: Joaquín Recas, Computer Science Faculty, Complutense University of Madrid, ES, Contact

Topic Members (click to open)

  • Amir Aminifar, Swiss Federal Institute of Technology Lausanne (EPFL), CH, Contact
  • Guillermo Botella, Complutense University of Madrid, ES, Contact
  • Luca Fanucci, University of Pisa, IT, Contact
  • Christian Fayomi, Printable Smart Devices Lab/UQAM, CA, Contact
  • Michele Magno, ETH Zurich, CH, Contact

Design experiences covering the use of IoT, wireless body sensor networks, assistive and wearable technologies for healthcare, rehabilitation and wellness. Topics of interest include: technologies and application-specific design methodologies (including approximate or significance-driven computing) for ultra-low/zero power systems for personal vital sign monitoring (such as heart rate, fitness devices); body area networks; mobile systems for motor disorder assessment and rehabilitation; wearable and edge computing technologies and designs; devices and systems for personal health and personalized medicine; ambient assisted living technologies; innovative nano-technologies for both non-intrusive or implantable miniaturized sensors and actuators, smart spaces for youngsters, elderly, or impaired users; technologies for motor disorders; personal health devices and assistive technology; power management, on-board performance optimization and networking technologies for body area networks; and ambient intelligence in wellness, healthcare, and fitness.

A5 Secure Systems, Circuits, and Architectures (click to open)

Chair: Tim Güneysu, University of Bremen & DFKI, DE, Contact

Co-Chair: Stefan Mangard, Graz University of Technology, AT, Contact

Topic Members (click to open)

  • Todd Austin, University of Michigan, US, Contact
  • Luca Breveglieri, Politecnico di Milano, IT, Contact
  • Aurélien Francillon, EURECOM, FR, Contact
  • Frank Gurkaynak, ETH Zurich, CH, Contact
  • Marcel Medwed, NXP Semiconductors Austria GmbH, AT, Contact
  • Thomas Poeppelmann, Infineon Technologies AG, DE, Contact
  • Sergei Skorobogatov, University of Cambridge, GB, Contact
  • Lionel Torres, University of Montpellier, FR, Contact
  • Ingrid Verbauwhede, imec-COSIC, KU Leuven, BE, Contact

Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and prototypes. Topics of interest include: secure HW architectures; novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip enciphering and integrity checking; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Reconfigurable and Robust Systems (click to open)

Chair: Christian Weis, University of Kaiserslautern, DE, Contact

Co-Chair: Antonio Miele, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Diana Goehringer, TU Dresden, DE, Contact
  • Christian Pilato, Politecnico di Milano, IT, Contact
  • Amir M. Rahmani, University of California, Irvine, US, Contact
  • Wenjing Rao, University of Illinois at Chicago, US, Contact

Design experiences in the area of adaptive systems targeting reliability, robustness and variability-aware functionality in practical and industrial applications. Topics of interest include: reliable and reconfigurable system development and optimization; practical application mechanisms and use cases that compensate reliability issues such as aging, variability and temperature; reconfigurable systems and applications; static and dynamic reconfiguration techniques; context-aware applications and self-adaptive architectures.

A7 Applications of Emerging Technologies (click to open)

Chair: Andy Tyrrell, University of York, GB, Contact

Co-Chair: Yu Wang, Tsinghua University, CN, Contact

Topic Members (click to open)

  • Armin Alaghi, University of Washington, US, Contact
  • Michal Bidlo, Brno University of Technology, CZ, Contact
  • Philip Brisk, University of California, Riverside, US, Contact
  • Anup Das, IMEC, US, Contact
  • Jie Han, University of Alberta, CA, Contact
  • Jim Harkin, Ulster University, GB, Contact
  • Tsung-Yi Ho, National Tsing Hua University, TW, Contact
  • Li Jiang, Shanghai Jiao Tong University, CN, Contact
  • Paul Kaufmann, University of Paderborn, DE, Contact
  • Bing Li, Technical University of Munich, DE, Contact
  • yongpan liu, tsinghua university, CN, Contact
  • Lukas Sekanina, Brno University of Technology, CZ, Contact
  • Martin Albrecht Trefzer, University of York, GB, Contact
  • Robert Wille, Johannes Kepler University Linz, AT, Contact
  • Hailong Yao, Tsinghua University, CN, Contact

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers (click to open)

Chair: Fabien Clermidy, CEA-Leti, FR, Contact

Co-Chair: Norbert Wehn, University of Kaiserslautern, DE, Contact

Topic Members (click to open)

  • Mario Diaz Nava, STMicroelectronics, FR, Contact
  • Doris Keitel-Schulz, Infineon AG, DE, Contact
  • Enrico Macii, Politecnico di Torino, IT, Contact
  • Emil Matus, Technische Universität Dresden, DE, Contact

Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.

Track T: Test, Reliability, and Robustness (click to open)

This track covers all test, design-for-test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analog and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Topics

T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability (click to open)

Chair: Mehdi Tahoori, Karlsruhe Institute of Technology (KIT), DE, Contact

Co-Chair: Said Hamdioui, TU Delft, NL, Contact

Topic Members (click to open)

  • Vikas Chandra, ARM, US, Contact
  • Saman Kiamehr, Bosch Starter Generator GmbH, DE, Contact
  • Bram Kruseman, NXP Semiconductors, NL, Contact
  • Hans Manhaeve, Ridgetop Europe, BE, Contact
  • Jose Pineda, NXP Semiconductors, NL, Contact
  • Rosa Rodríguez-Montañés, UPC, ES, Contact
  • Elena Ioana Vatajelu, TIMA, FR, Contact

Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

T2 Test Generation, Simulation and Diagnosis (click to open)

Chair: Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT, Contact

Co-Chair: Davide Appello, STMicroelectronics, IT, Contact

Topic Members (click to open)

  • Stephan Eggersglüß, Mentor Graphics, DE, Contact
  • Emil Gizdarski, Synopsys, US, Contact
  • Huawei Li, Institute of Computing Technology Chinese Academy of Sciences, Beijing, CN, Contact
  • Arnaud Virazel, LIRMM, FR, Contact

Algorithms for test pattern generation (TPG); TPG for delay and small-delay faults; TPG for low power; algorithms for test compression and compaction; ATPGs; fault simulation; diagnosis; power issues in testing; test generation for microprocessors, memories, FPGAs and regular structures; algorithms for board and system test; volume diagnosis and yield analysis.

T3 Design-for-Test, Test Infrastructures, Test Standards (click to open)

Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

Co-Chair: Jerzy Tyszer, Poznan University of Technology, PL, Contact

Topic Members (click to open)

  • Erik Larsson, Lund University, SE, Contact
  • Teresa McLaurin, ARM, US, Contact
  • Grzegorz Mrugalski, Mentor Graphics, PL, Contact
  • Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact

Architectures and solutions for design for test, diagnosis, debug, post silicon validation; functional safety; in-system run-time test; BIST and embedded test; power-on self-test; test architectures and infrastructures for memories, FPGAs, 2.5D, 3D, SiP, SoC, NoC, and microprocessors; ATE architectures; test standards (JTAG, IJTAG, 1500, 1687, P1838).

T4 System-Level Reliability Design, Analysis and On-line Test (click to open)

Chair: Jaume Abella, Barcelona Supercomputing Center (BSC-CNS), ES, Contact

Co-Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY, Contact

Topic Members (click to open)

  • Lorena Anghel, Grenoble-Alpes University, FR, Contact
  • Luigi Carro, UFRGS, BR, Contact
  • Stefano Di Carlo, Politecnico di Torino, IT, Contact
  • Maksim Jenihhin, Tallinn University of Technology, EE, Contact
  • Brett Meyer, McGill University, CA, Contact
  • Dimitris Nikolos, University of Patras, GR, Contact
  • Mihalis Psarakis, University of Piraeus, GR, Contact
  • Andreas Steininger, Vienna University of Technology, AT, Contact
  • Vasileios Tenentes, ARM/ECS Research Centre, University of Southampton, GB, Contact

Fault models; permanent, transient and soft errors; reliability evaluation; space-, time- and information-redundancy solutions for availability, reliability and maintainability; highly-available systems; reliable and fail-safe system design; HW/SW solutions for on-line fault detection, tolerance, recovery, and aging mitigation.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

Chair: Andrè Ivanov, University of British Columbia, CA, Contact

Co-Chair: Georges Gielen, KU Leuven, BE, Contact

Topic Members (click to open)

  • Manuel Barragan, TIMA Laboratory, FR, Contact
  • Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact
  • Deukhyoun Heo, Washington State University, US, Contact
  • Nuno Horta, Instituto de Telecomunicações /Instituto Superior Técnico – Universidade de Lisboa, PT, Contact
  • Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES, Contact
  • Mark Po-Hung Lin, National Chung Cheng University, TW, Contact
  • Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR, Contact
  • Shahriar Mirabbasi, University of British Columbia, CA, Contact
  • Manoj Sachdev, University of Waterloo, CA, Contact
  • Shreyas Sen, ECE, Purdue University, US, Contact
  • Gerd Vandersteen, Vrije Universiteit Brussel - dept. ELEC, BE, Contact

Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; HW description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.

DT6 Design and Test of Secure Systems (click to open)

Chair: Ilia Polian, University of Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

Topic Members (click to open)

  • Aydin Aysu, North Carolina State University, US, Contact
  • Wayne Burleson, U Massachusetts Amherst, US, Contact
  • Jean Luc Danger, Télécom ParisTech, FR, Contact
  • Wieland Fischer, Infineon Technologies, DE, Contact
  • Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US, Contact
  • Mike Hutter, Cryptography Research Inc., US, Contact
  • Farinaz Koushanfar, University of California San Diego, US, Contact
  • Roel Maes, Intrinsic-ID, NL, Contact
  • Yiorgos Makris, The University of Texas at Dallas, US, Contact
  • Nele Mentens, KU Leuven, BE, Contact
  • David Oswald, School of Computer Science, University of Birmingham, GB, Contact
  • Francesco Regazzoni, ALaRI, CH, Contact
  • Kazuo Sakiyama, The University of Electro-Communications, JP, Contact
  • Matthias Sauer, University of Freiburg, DE, Contact
  • Mark M. Teranipoor, University of Florida, US, Contact
  • Marc Witteman, Riscure, NL, Contact

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks.

Track E: Embedded and Cyber-physical Systems (click to open)

This track is devoted to the modeling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked systems, and dependable systems.

Track Chair: Franco Fummi, Universita' di Verona, IT, Contact

Topics

E1 Real-time, Networked, and Dependable Systems (click to open)

Chair: Kai Lampka, Electrobit Automotive GmbH, DE, Contact

Co-Chair: Dionisio de Niz, Carnegie Mellon University, US, Contact

Topic Members (click to open)

  • Sebastian Altmeyer, University of Amsterdam, NL, Contact
  • Marc Boyer, ONERA, FR, Contact
  • Rolf Ernst, TU Braunschweig, DE, Contact
  • Gerhard Fohler, Technische Universität Kaiserlautern, DE, Contact
  • Leandro Indrusiak, University of York, GB, Contact
  • Hyoseung Kim, University of California, Riverside, US, Contact
  • Dorin Maxim, University of Lorraine - Loria - Inria Nancy Grand Est, FR, Contact
  • Florian Pölzlbauer, Virtual Vehicle, AT, Contact
  • Frank Slomka, Ulm University, DE, Contact

Real-time programming languages and software; real-time (software) performance analysis, e.g., network calculus, worst case execution time analysis, scheduling and software timing estimation, simulation and measurement-based analysis techniques; real-time system optimization; software for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and mixed-criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications.

E2 Compilers and Software Synthesis (click to open)

Chair: Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg, DE, Contact

Co-Chair: Bjorn De Sutter, Ghent University, BE, Contact

Topic Members (click to open)

  • Nicola Bombieri, University of Verona, IT, Contact
  • Florian Brandner, Télécom ParisTech, FR, Contact
  • Oliver Bringmann, University of Tuebingen / FZI, DE, Contact
  • Tony Givargis, University of California, Irvine, US, Contact
  • Laura Pozzi, USI Lugano, CH, Contact
  • Jingling Xue, UNSW, AU, Contact

Compiler support for multi-core/many-core architectures, GPUs, CGRAs, FPGAs, accelerators in heterogeneous computing platforms, memory hierarchy including caches, scratchpad, and non-volatile memories; code analysis, optimization, and generation for different metrics (e.g., performance, power/energy, code/data size, reliability, security, WCET, etc.); just-in-time compilation, interpreters, binary translation; compiler support for enhanced debugging, profiling, and traceability; Software tools and techniques for design space exploration (compilers, simulators, synthesis tools); compilation infrastructures for high-level synthesis and domain-specific or streaming languages for embedded systems; software synthesis for IoT, wearables, cyber-physical systems, programmable microfluidics.

E3 Model-based Design and Verification (click to open)

Chair: Petru Eles, Linkoping University, SE, Contact

Co-Chair: Borzoo Bonakdarpour, Iowa State University, US, Contact

Topic Members (click to open)

  • Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG, Contact
  • Yliès Falcone, Univ. Grenoble Alpes, Inria, FR, Contact
  • Florence Maraninchi, Univ. Grenoble-Alpes & Verimag, FR, Contact
  • Kristin Yvonne Rozier, NASA Ames Research Center, US, Contact
  • Lothar Thiele, ETH Zurich, CH, Contact

Verification techniques for embedded and cyber-physical systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems.

E4 Embedded Software Architectures (click to open)

Chair: Akash Kumar, Technische Universität Dresden, DE, Contact

Co-Chair: Orlando Moreira, Intel Corporation, PT, Contact

Topic Members (click to open)

  • Marc Geilen, Eindhoven University of Technology, NL, Contact
  • Anca Molnos, CEA-Leti, Grenoble, FR, Contact
  • Tanguy Risset, Inria/INSA-Lyon, FR, Contact
  • Aviral Shrivastava, Arizona State University, US, Contact
  • Amit Kumar Singh, University of Essex, GB, Contact
  • Hiroyuki Tomiyama, Ritsumeikan University, JP, Contact

Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; software support for approximate computation and accelerators; software architectures for low power and temperature awareness.

E5 Software Architectures for Cyber-Physical Systems (click to open)

Chair: Shiyan Hu, Michigan Technological University, US, Contact

Co-Chair: Thomas Nolte, MRTC/Mälardalen University, SE, Contact

Topic Members (click to open)

  • Mohammad Al Faruque, University of California Irvine, US, Contact
  • radu grosu, Vienna University of Technology, AT, Contact
  • Davide Quaglia, University of Verona, IT, Contact
  • Qi Zhu, Northwestern University, US, Contact

Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); modeling techniques for large-scale cyber physical systems design and analysis; verification and validation in CPS; safety and cybersecurity in CPS systems; internet-of-things and CPS: modeling, analysis, and design; software-intensive CPS; data-mining and CPS; autonomous and semi-autonomous large-scale CPS and related issues; socio-technical systems (e.g., empowered consumer and organizational behavior in smart grids) and CPS; cognitive control for CPS; modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis.

< Return to last page