DATE 2012 Proceedings - Author Index

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Aasaraai, K: [1] [2] Toward Virtualizing Branch Direction Prediction [p. 455]
Abate, F: [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Abdallah, L: [5] [6] Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Abed, I S: [7] [8] Double-Patterning Friendly Grid-Based Detailed Routing with Online Conflict Resolution [p. 1475]
Abelein, U: [9] [10] Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Abellan, J L: [11] [12] Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Aboushady, H: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Abraham, J A: [15] [16] On-Chip Source Synchronous Interface Timing Test Scheme with Calibration [p. 1146]
Acacio, M E: [11] [12] Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Acquaviva, A: [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Adlkofer, H: [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Adve, S V: [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Afzali-Kusha, A: [21] [22] An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Ahn, J H: [23] [24] CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Ahopelto, J: [25] [26] Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Aisopos, K: [27] [28] PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Akbari, S: [29] [30] AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Akesson, B: [31] [32] DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]; [33] [34] Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Aksanli, B: [35] [36] Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers [p. 175]
Aksoy, L: [37] [38] Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Aktouf, O-E-K: [39] [40] Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Al-Faruque, M A: [41] [42] Intelligent and Collaborative Embedded Computing in Automation Engineering [p. 344]; [43] [44] Towards Parallel Execution of IEC 61131 Industrial Cyber-Physical Systems Applications [p. 554]
Al-Hashimi, B M: [45] [46] Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Almeroth, B: [47] [48] Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Aloufi, M: [45] [46] Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Altet, J: [5] [6] Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Alvarez-Herault, J: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Amara, A: [51] [52] Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Ambrose, A: [53] [54] A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Anagnostopoulos, I: [55] [56] A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Anderson, J: [57] [58] Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Anghel, L: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Anis, M: [61] [62] AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Annaswamy, A: [63] [64] Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Appleton, E: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Aridhi, H: [67] [68] Towards Improving Simulation of Analog Circuits Using Model Order Reduction [p. 1337]
Ascheid, G: [69] [70] Hybrid Simulation for Extensible Processor Cores [p. 288]
Ashouei, M: [71] [72] Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Atienza, D: [73] [74] Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation [p. 599]; [75] [76] Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]; [77] [78] A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Aubert, A: [79] [80] Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Augustine, C: [81] [82] A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach [p. 1443]
Austin, T: [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Avresky, D: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Axer, P: [83] [84] Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Ayoub, R: [85] [86] TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs [p. 593]
Azevedo, J: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]

B

Babayan, E: [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Bahl, S: [89] [90] EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Bainbridge, W J: [91] [92] Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Bamakhrama, M A: [93] [94] A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Banerjee, A: [95] [96] Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]; [63] [64] Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Baronti, F: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Bartolini, A: [99] [100] Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]
Bartzas, A: [55] [56] A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Basten, T: [101] [102] Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]; [103] [104] Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Basu, S: [105] [106] Correct-by-Construction Multi-Component SoC Design [p. 647]
Bathen, L A D: [107] [108] VaMV: Variability-aware Memory Virtualization [p. 284]; [109] [110] 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]
Battezzati, N: [111] [112] SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Bauer, L: [113] [114] Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]; [115] [116] Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Baumanns, S: [117] [118] Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Beaumont, M: [119] [120] SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Becker, B: [121] [122] On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]; [123] [124] Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Becker, J: [125] [126] A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]; [127] [128] On Demand Dependent Deactivation of Automotive ECUs [p. 69]; [129] [130] Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Becker, M: [131] [132] MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Belta, C: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Benini, L: [133] [134] Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]; [135] [136] Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]; [99] [100] Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]; [11] [12] Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]; [137] [138] A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]; [139] [140] P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]; [141] [142] Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]; [143] [144] An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Benkner, S: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Benoit, P: [147] [148] Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
Berangi, R: [29] [30] AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Berkelaar, M: [149] [150] Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Beroulle, V: [39] [40] Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Bertacco, V: [151] [152] Approximating Checkers for Simulation Acceleration [p. 153]; [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Bertels, K: [153] [154] Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Bertozzi, D: [11] [12] Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]; [155] [156] A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Bertrand, D: [157] [158] Challenges and New Trends in Probabilistic Timing Analysis [p. 810]
Beste, M: [159] [160] Layout-Driven Robustness Analysis for Misaligned Carbon Nanotubes in CNTFET-based Standard Cells [p. 1609]
Bhardwaj, K: [161] [162] An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Bhatia, S: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Bi, X: [163] [164] Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Bittner, K: [165] [166] Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Blech, J O: [167] [168] Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Blom, H: [169] [170] Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Bocca, A: [171] [172] Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Bolchini, C: [173] [174] An Adaptive Approach for Online Fault Management in Many-Core Architectures [p. 1429]
Bombieri, N: [175] [176] FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]
Bonamy, R: [177] [178] UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Bonilla, E: [179] [180] Predicting Best Design Trade-offs: A Case Study in Processor Customization [p. 1030]
Borde, E: [181] [182] Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Bordoloi, U D: [183] [184] A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Bortolotti, D: [11] [12] Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Bose, P: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Bosio, A: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Bovington, J: [187] [188] Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Bowman, K: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Bozga, M: [189] [190] State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Brachtendorf, H G: [165] [166] Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Brandl, M: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Brault, J -M: [191] [192] NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Brayton, R: [193] [194] Mapping into LUT Structures [p. 1579]
Brayton, R K: [195] [196] Scalable Progress Verification in Credit-Based Flow-Control Systems [p. 905]
Brenner, U: [197] [198] VLSI Legalization with Minimum Perturbation by Iterative Augmentation [p. 1385]
Bringmann, O: [199] [200] Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]; [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]; [203] [204] Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies [p. 862]
Brisk, P: [205] [206] Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Brockman, J B.: [23] [24] CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Brokalakis, A: [207] [208] An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Bruening, A: [209] [210] Memristor Technology in Future Electronic System Design [p. 592]; [211] [212] Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Brunelli, D: [133] [134] Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Buckl, C: [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; [167] [168] Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Burg, A: [75] [76] Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Burgio, P: [135] [136] Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]
Buyuktosunoglu, A: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]

C

Cai, Y: [213] [214] Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Calazans, N: [215] [216] An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design [p. 224]
Calimera, A: [217] [218] IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]; [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Campagna, S: [219] [220] An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation [p. 1433]
Campbell, S A: [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Camposano, R: [223] [224] Moore Meets Maxwell [p. 1275]
Canedo, A: [41] [42] Intelligent and Collaborative Embedded Computing in Automation Engineering [p. 344]; [43] [44] Towards Parallel Execution of IEC 61131 Industrial Cyber-Physical Systems Applications [p. 554]
Carloni, L P: [225] [226] Compositional System-Level Design Exploration with Planning of High-Level Synthesis [p. 641]
Carr, S B: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Catthoor, F: [71] [72] Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]; [77] [78] A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Cenni, F: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Cha, B: [227] [228] Salvaging Chips with Caches beyond Repair [p. 1263]
Chakrabarty, K: [229] [230] Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]; [231] [232] Test Pin Count Reduction for NoC-based Test Delivery in Multicore SOCs [p. 787]; [233] [234] A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Chakraborty, K: [161] [162] An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Chakraborty, S: [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; [235] [236] Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]; [63] [64] Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Chandrasekar, K: [237] [238] A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Chang, K-H: [239] [240] RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Chang, L-P: [241] [242] Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks [p. 117]
Chang, N: [243] [244] Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; [245] [246] State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Chang, S-C: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chang, Y-W: [249] [250] Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]
Chao, H-L: [251] [252] Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chatterjee, D: [151] [152] Approximating Checkers for Simulation Acceleration [p. 153]
Chaturvedi, S: [253] [254] Static Analysis of Asynchronous Clock Domain Crossings [p. 1122]
Chatziparaskevas, G: [207] [208] An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Chen, C: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]; [193] [194] Mapping into LUT Structures [p. 1579]
Chen, C-L: [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Chen, D: [257] [258] Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Chen, H: [259] [260] QBF-Based Boolean Function Bi-Decomposition [p. 816]; [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Chen, H-M: [263] [264] Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization [p. 1391]; [265] [266] On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, J: [267] [268] A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Chen, J-J: [63] [64] Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Chen, K: [23] [24] CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Chen, L: [269] [270] Online Scheduling for Multi-Core Shared Reconfigurable Fabric [p. 582]; [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Chen, M-L: [265] [266] On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, Q: [271] [272] Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]; [273] [274] Characterization of the Bistable Ring PUF [p. 1459]
Chen, S-H: [265] [266] On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, S-J: [251] [252] Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chen, W: [275] [276] Out-of-Order Parallel Simulation for ESL Design [p. 141]
Chen, Y: [277] [278] 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]; [163] [164] Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]; [279] [280] Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]; [281] [282] Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Chen, Y-C: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chen, Y-R: [251] [252] Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chen, Y-T: [283] [284] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Cheng, K-T: [187] [188] Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Cheng, X: [285] [286] Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Cherkaoui, A: [79] [80] Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Chian, M: [287] [288] New Foundry Models - Accelerations in Transformations of the Semiconductor Industry [p. 2]
Chiang, M-F: [289] [290] A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Chillet, D: [177] [178] UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Choi, K: [291] [292] State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Chong, S: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Chou, C-N: [293] [294] Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Chou, H-M: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chou, H-Z: [239] [240] RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Choudhary, A: [295] [296] Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Chua, L O: [209] [210] Memristor Technology in Future Electronic System Design [p. 592]
Chuang, Y-L: [249] [250] Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]
Cifrain, M: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Clavier, L: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Colazzo, S: [111] [112] SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Condo, C: [297] [298] A Network-on-Chip-based Turbo/LDPC Decoder Architecture [p. 1525]
Cong, J: [283] [284] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]; [299] [300] Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Constantin, J: [75] [76] Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Cordes, D: [301] [302] Multi-Objective Aware Extraction of Task-Level Parallelism Using Genetic Algorithms [p. 394]
Corporaal, H: [101] [102] Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]; [303] [304] Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]; [103] [104] Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Cosemans, S: [71] [72] Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Coskun, A K: [99] [100] Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]; [305] [306] Analysis and Runtime Management of 3D Systems with Stacked DRAM for Boosting Energy Efficiency [p. 611]; [307] [308] Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads [p. 994]
Costa, E: [37] [38] Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Craninckx, J: [309] [310] Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Cristal, A: [311] [312] TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Csaba, G: [273] [274] Characterization of the Bistable Ring PUF [p. 1459]
Cucuccio, A: [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Cui, T: [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Cui, X: [313] [314] Modeling and Testing of Interference Faults in the Nano NAND Flash Memory [p. 527]
Cui, Z: [257] [258] Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Cullmann, C: [199] [200] Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Cupaiuolo, T: [315] [316] A Flexible and Fast Software Implementation of the FFT on the BPE Platform [p. 1467]
Czutro, A: [121] [122] On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]

D

Daghar, A: [317] [318] Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Damavandpeyma, M: [103] [104] Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Daneshtalab, M: [319] [320] CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Dang, X: [321] [322] S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Danger, J-L: [323] [324] RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Daniel, L: [325] [326] An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems [p. 1203]
Darringer, J A: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Das, A: [295] [296] Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]; [327] [328] PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Das, S: [329] [330] PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations [p. 550]
Dasgupta, P: [95] [96] Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]
Dastgeer, U: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
David, A: [189] [190] State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Davoodi, A: [331] [332] A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection [p. 1331]; [333] [334] Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations [p. 1591]
De Jonghe, D: [335] [336] Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]; [337] [338] Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
De Micheli, G: [339] [340] Voltage Propagation Method for 3-D Power Grid Analysis [p. 844]
De Smedt, B: [117] [118] Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
De, V: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Defo, G B G: [131] [132] MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Dehaene, W: [341] [342] Design of a Low-Energy Data Processing Architecture for WSN Nodes [p. 570]; [71] [72] Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Deniz, E: [343] [344] Verification Coverage of Embedded Multicore Applications [p. 252]
Densmore, D: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Desbarbieux, J-I: [345] [346] An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Dey, O: [129] [130] Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Di Carlo, S: [155] [156] A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Di Guglielmo, G: [347] [348] Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Di Guglielmo, L: [347] [348] Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Di Natale, M: [349] [350] Task Implementation of Synchronous Finite State Machines [p. 206]
Dilillo, L: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Dimitrakopoulos, G: [351] [352] Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches [p. 542]
Doemer, R: [275] [276] Out-of-Order Parallel Simulation for ESL Design [p. 141]
Dogan, A Y: [75] [76] Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Dolinsky, U: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Domic, A: [211] [212] Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Donno, M: [171] [172] Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
dos Santos, L C V: [353] [354] On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Dousti, M J: [355] [356] Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric [p. 840]
Drach, N: [345] [346] An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Drechsler, R: [357] [358] A Guiding Coverage Metric for Formal Verification [p. 617]; [359] [360] Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]; [361] [362] Debugging of Inconsistent UML/OCL Models [p. 1078]; [363] [364] Eliminating Invariants in UML/OCL Models [p. 1142]
Druml, N: [365] [366] Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Du, K: [367] [368] High Performance Reliable Variable Latency Carry Select Addition [p. 1257]
Duan, G: [369] [370] Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Dutt, N D: [107] [108] VaMV: Variability-aware Memory Virtualization [p. 284]; [109] [110] 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]

E

Ebeid, E: [371] [372] Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Ebrahimi, M: [319] [320] CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]; [373] [374] SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Edwards, D: [91] [92] Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Een, N: [193] [194] Mapping into LUT Structures [p. 1579]
Ejlali, A: [373] [374] SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Eklow, B: [375] [376] On Effective TSV Repair for 3D-Stacked ICs [p. 793]
Eles, P: [377] [378] Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]; [183] [184] A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Ellen, C: [379] [380] Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Enescu, F: [381] [382] Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]
Ernst, R: [383] [384] Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]; [385] [386] A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]; [387] [388] Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]; [389] [390] Optimizing Performance Analysis for Synchronous Dataflow Graphs with Shared Resources [p. 635]; [157] [158] Challenges and New Trends in Probabilistic Timing Analysis [p. 810]; [83] [84] Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Etzien, C: [379] [380] Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Eusse, J: [69] [70] Hybrid Simulation for Extensible Processor Cores [p. 288]

F

Fabiano, M: [155] [156] A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Fahmy, S: [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Fan, M: [391] [392] Neighbor-Aware Dynamic Thermal Management for Multi-core Platform [p. 187]; [393] [394] Harmonic Semi-Partitioned Scheduling for Fixed-Priority Real-Time Tasks on Multi-Core Platform [p. 503]
Fan, X: [395] [396] Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Fantechi, G: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Fanucci, L: [397] [398] Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]; [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Fatemi, H: [399] [400] Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems [p. 1048]
Fathy, M: [29] [30] AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Faura, D: [181] [182] Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Fernandez, J: [11] [12] Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Ferrari, A: [171] [172] Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Fesquet, L: [79] [80] Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Fettweis, G: [401] [402] Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) [p. 1161]; [47] [48] Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Figueras, J: [403] [404] Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation [p. 1343]
Fiorini, P: [405] [406] Predictive Control of Networked Control Systems over Differentiated Services Lossy Networks [p. 1245]
Firouzi, F: [407] [408] NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]
Fischer, V: [79] [80] Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Flamand, E: [139] [140] P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Flores, P: [37] [38] Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Fohler, G: [409] [410] On-line Scheduling of Target Sensitive Periodic Tasks with the Gravitational Task Model [p. 578]
Fradet, P: [411] [412] SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Franchi, E: [397] [398] Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]
Fritz, G: [39] [40] Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Fu, X: [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Fuin, D: [139] [140] P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Fummi, F: [347] [348] Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]; [131] [132] MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]; [175] [176] FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]; [371] [372] Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Furst, J-N: [99] [100] Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]

G

Gadkari, A: [413] [414] An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Gall, H: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Gamatie, A: [415] [416] Design of Streaming Applications on MPSoCs Using Abstract Clocks [p. 763]
Gan, J: [417] [418] Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Ganguly, R: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Ganta, D: [419] [420] ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Gao, J: [421] [422] A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Gao, M: [187] [188] Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Gao, P: [309] [310] Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Garcia-Ortiz, A: [359] [360] Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]
Garside, J: [91] [92] Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Garudadri, H: [423] [424] A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Gatti, M: [181] [182] Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Gebhard, G: [199] [200] Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Geilen, M: [101] [102] Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]; [103] [104] Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Genser, A: [365] [366] Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Gerdes, M: [425] [426] Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Ghodrat, M A: [427] [428] Optimization Intensive Energy Harvesting [p. 272]
Giegerich, M: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Gielen, G: [335] [336] Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]; [429] [430] A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems [p. 751]; [431] [432] Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]; [309] [310] Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]; [337] [338] Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Girard, P: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Girault, A: [411] [412] SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Giusto, P: [383] [384] Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]
Givargis, T: [433] [434] MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups [p. 1417]
Glass, M: [435] [436] Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Goehringer, D: [129] [130] Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Goel, M: [437] [438] A High Performance Split-Radix FFT with Constant Geometry Architecture [p. 1537]
Goel, S K: [89] [90] EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Gol, E A: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Goldman, R: [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Gomony, M D: [31] [32] DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]
Gong, J: [439] [440] Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Goossens, K: [31] [32] DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]; [33] [34] Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]; [53] [54] A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Goossens, S: [33] [34] Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Gope, D: [223] [224] Moore Meets Maxwell [p. 1275]
Goswami, D: [235] [236] Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Goswami, D: [63] [64] Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Graeb, H: [441] [442] ITRS 2011 Analog EDA Challenges and Approaches - Invited Paper [p. 1150]
Graef, M W M: [25] [26] Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Grass, E: [395] [396] Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Grivet-Talocia, S: [223] [224] Moore Meets Maxwell [p. 1275]
Grosse, D: [357] [358] A Guiding Coverage Metric for Formal Verification [p. 617]
Grudnitsky, A: [115] [116] Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Gruian, F: [417] [418] Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Guarnieri, V: [175] [176] FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]
Guderian, F: [47] [48] Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Guerra, R: [409] [410] On-line Scheduling of Target Sensitive Periodic Tasks with the Gravitational Task Model [p. 578]
Guilley, S: [323] [324] RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Guo, X: [419] [420] ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Gupta, A: [443] [444] Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]
Gupta, M S: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Gupta, P: [107] [108] VaMV: Variability-aware Memory Virtualization [p. 284]; [229] [230] Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Gupta, R K: [141] [142] Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]
Gupta, S K: [227] [228] Salvaging Chips with Caches beyond Repair [p. 1263]; [445] [446] Layout-Aware Optimization of STT MRAMs [p. 1455]

H

Haddock, T: [65] [66] Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Haedicke, F: [357] [358] A Guiding Coverage Metric for Formal Verification [p. 617]
Hahn, D: [9] [10] Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Haid, J: [365] [366] Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Hamdioui, S: [447] [448] DfT Schemes for Resistive Open Defects in RRAMs [p. 799]
Hameed, F: [113] [114] Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]
Hammami, O: [191] [192] NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Hamouche, R: [449] [450] Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design [p. 1421]
Hamouda, A Y: [61] [62] AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Han, K: [291] [292] State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Han, X: [275] [276] Out-of-Order Parallel Simulation for ESL Design [p. 141]
Han, Y: [421] [422] A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Hanke, M: [387] [388] Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]
Hankendi, C: [307] [308] Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads [p. 994]
Hansen, J: [451] [452] Multi-Token Resource Sharing for Pipelined Asynchronous Systems [p. 1191]
Hansen, R: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Hapke, F: [89] [90] EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Haratsch, E F: [213] [214] Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Hardavellas, N: [295] [296] Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Hari, S K S: [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Haron, N Z: [447] [448] DfT Schemes for Resistive Open Defects in RRAMs [p. 799]
Harrant, M: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Hartmanns, A: [189] [190] State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Hasholzner, R: [455] [456] Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Hassoun, S: [457] [458] Genetic/Bio Design Automation for (Re-)Engineering Biological Systems [p. 242]
Haubelt, C: [455] [456] Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
He, Y: [303] [304] Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Healy, M B: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Hedrich, L: [459] [460] Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Heer, C: [395] [396] Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Hely, D: [39] [40] Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Henkel, J: [461] [462] Accurate Source-Level Simulation of Embedded Software with Respect to Compiler Optimizations [p. 382]; [113] [114] Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]; [463] [464] Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]; [115] [116] Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Henry, M B: [419] [420] ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Henschel, O P: [353] [354] On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Herkersdorf, A: [465] [466] Virtual Platforms: Breaking New Grounds [p. 685]
Hermanns, H: [189] [190] State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Heuser, A: [467] [468] Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models [p. 1179]
Ho, T-Y: [233] [234] A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Holt, J: [343] [344] Verification Coverage of Embedded Multicore Applications [p. 252]
Hopkins, B: [119] [120] SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Howe, R T: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Hsiao, M S: [469] [470] RAG: An Efficient Reliability Analysis of Logic Circuits on Graphics Processing Units [p. 316]; [237] [238] A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Hsiung, P-A: [251] [252] Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Hsu, H-W: [265] [266] On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Hsuing, H: [227] [228] Salvaging Chips with Caches beyond Repair [p. 1263]
Hu, Y: [439] [440] Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Huang, C-Y: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]; [293] [294] Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Huang, H: [283] [284] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]; [471] [472] Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Huang, J: [167] [168] Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]; [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Huang, K: [439] [440] Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Huang, M: [299] [300] Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Huang, P-K: [293] [294] Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Huang, S: [419] [420] ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Huebner, M: [129] [130] Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Huisken, J: [71] [72] Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Hung, C Y: [473] [474] Challenges in Verifying an Integrated 3D Design [p. 167]
Huss, A: [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]
Huss, S A: [475] [476] Side Channel Analysis of the SHA-3 Finalists [p. 1012]

I

Ienne, P: [205] [206] Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Ike, A: [477] [478] Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Illikkal, R: [27] [28] PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Indaco, M: [155] [156] A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Irwin, M J: [479] [480] An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Iyengar, V: [473] [474] Challenges in Verifying an Integrated 3D Design [p. 167]
Iyer, R: [27] [28] PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]

J

Jacobson, H: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Jafari, F: [481] [482] Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]
Jahn, M: [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Jandhyala, V: [223] [224] Moore Meets Maxwell [p. 1275]
Jang, M-W: [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Jang, S: [193] [194] Mapping into LUT Structures [p. 1579]
Janota, M: [259] [260] QBF-Based Boolean Function Bi-Decomposition [p. 816]
Janssen, R: [117] [118] Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Jantsch, A: [481] [482] Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]; [483] [484] Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC [p. 1289]
Jedda, H: [485] [486] Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]
Jentsch, M: [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Jeong, K: [487] [488] MAPG: Memory Access Power Gating [p. 1054]
Jerke, G: [489] [490] Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Jha, N K: [491] [492] Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals [p. 437]
Jiang, J: [121] [122] On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]; [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Jiang, K: [377] [378] Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]
Jiang, L: [375] [376] On Effective TSV Repair for 3D-Stacked ICs [p. 793]; [271] [272] Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]
Jin, T: [369] [370] Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Jin, Y: [493] [494] Post-Deployment Trust Evaluation in Wireless Cryptographic ICs [p. 965]
Jones, A K: [279] [280] Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Jones, D L: [257] [258] Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Jones, S: [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]
Jonsson, F: [267] [268] A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Jouppi, N P.: [23] [24] CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Jovic, J: [69] [70] Hybrid Simulation for Extensible Processor Cores [p. 288]
Juan, D-C: [249] [250] Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]

K

Kahng, A B: [487] [488] MAPG: Memory Access Power Gating [p. 1054]
Kakoee, M R: [137] [138] A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]
Kalla, P: [381] [382] Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]
Kalligeros, E: [351] [352] Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches [p. 542]
Kamal, M: [21] [22] An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Kandemir, M: [495] [496] Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Kang, S: [487] [488] MAPG: Memory Access Power Gating [p. 1054]
Karim, K S: [61] [62] AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Karimi, N: [229] [230] Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Karlsson, D: [169] [170] Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Karnik, T: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Karri, R: [497] [498] Logic Encryption: A Fault Analysis Perspective [p. 953]
Kasper, M: [475] [476] Side Channel Analysis of the SHA-3 Finalists [p. 1012]
Kathareios, G: [55] [56] A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Katoen, J-P: [499] [500] Model Checking of Scenario-Aware Dataflow with CADP [p. 653]
Katz, Y: [501] [502] Generating Instruction Streams Using Abstract CSP [p. 15]
Kazmierski, T J: [45] [46] Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Keng, B: [503] [504] Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Kerkhoff, H G: [505] [506] Monitoring Active Filters under Automotive Aging Scenarios with Embedded Instrument [p. 1096]
Kessler, C: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Kestur, S: [479] [480] An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Khatri, S P: [507] [508] A Fast, Source-Synchronous Ring-based Network-on-Chip Design [p. 1489]
Khellah, M: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Kiamehr, S: [407] [408] NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]
Kim, D: [509] [510] A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]
Kim, H: [15] [16] On-Chip Source Synchronous Interface Timing Test Scheme with Calibration [p. 1146]
Kim, N S: [511] [512] Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors [p. 1134]
Kim, Y: [243] [244] Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; [509] [510] A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]; [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Kirsch, C: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Kluge, F: [425] [426] Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Knoedler, K: [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]
Knoll, A: [167] [168] Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]; [513] [514] Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
Knoth, C: [485] [486] Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]
Kocabas, U: [327] [328] PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Kocik, R: [449] [450] Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design [p. 1421]
Koenig, R: [125] [126] A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]
Kogel, T: [465] [466] Virtual Platforms: Breaking New Grounds [p. 685]
Kondratyev, A: [515] [516] Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Kotiyal, S: [517] [518] Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder [p. 721]
Kouters, T: [33] [34] Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Kress, R: [211] [212] Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Kriebel, F: [463] [464] Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Krinke, A: [489] [490] Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Kristic, M: [395] [396] Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Krone, S: [47] [48] Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Kulkarni, J: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Kuntz, S: [169] [170] Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Kunze, M: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Kural, E: [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]
Kuwamura, S: [477] [478] Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Kwon, S: [509] [510] A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]

L

Lafaye, M: [181] [182] Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Lai, L-C: [519] [520] Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs [p. 1479]
Lam, T-K: [521] [522] Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]
Landis, D L: [523] [524] Hazard Driven Test Generation for SMT Processors [p. 256]
Landolt, F: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Larsen, K G: [189] [190] State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Lau, J: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Laur, R: [165] [166] Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Lavagno, L: [515] [516] Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Laversanne, S: [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]
Le, B: [57] [58] Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]; [503] [504] Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Lee, C L: [313] [314] Modeling and Testing of Interference Faults in the Nano NAND Flash Memory [p. 527]
Lee, C-J: [263] [264] Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization [p. 1391]
Lee, D: [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Lee, M-C: [525] [526] Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Lee, S: [509] [510] A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]; [527] [528] Bloom Filter-based Dynamic Wear Leveling for Phase-Change RAM [p. 1513]
Lee, W S: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Legay, A: [189] [190] State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Lehner, W: [401] [402] Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) [p. 1161]
Leteinturier, P: [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Leupers, R: [69] [70] Hybrid Simulation for Extensible Processor Cores [p. 288]; [465] [466] Virtual Platforms: Breaking New Grounds [p. 685]
Leveque, A: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Lewis, M: [123] [124] Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Li, B: [455] [456] Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Li, H: [163] [164] Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]; [281] [282] Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]; [529] [530] A Complexity Adaptive Channel Estimator for Low Power [p. 1531]
Li, H-C: [265] [266] On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Li, M: [469] [470] RAG: An Efficient Reliability Analysis of Logic Circuits on Graphics Processing Units [p. 316]; [331] [332] A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection [p. 1331]; [333] [334] Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations [p. 1591]
Li, S: [23] [24] CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]; [289] [290] A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Li, T: [531] [532] Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors [p. 875]
Li, X: [421] [422] A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]; [439] [440] Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]; [191] [192] NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Li, Y: [279] [280] Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Liang, Y: [257] [258] Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Lilja, D J: [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Liljeberg, P: [319] [320] CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Lin, H-Y: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Lin, R-B: [519] [520] Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs [p. 1479]
Lin, W-H: [241] [242] Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks [p. 117]
Lin, X: [245] [246] State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Lindwer, M: [533] [534] Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Lippautz, M: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Lisherness, P: [187] [188] Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Liu, B: [283] [284] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]; [439] [440] Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]; [429] [430] A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems [p. 751]; [299] [300] Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Liu, C: [283] [284] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Liu, D: [535] [536] A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Liu, G: [391] [392] Neighbor-Aware Dynamic Thermal Management for Multi-core Platform [p. 187]
Liu, H: [439] [440] Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]; [537] [538] An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]
Liu, H-Y: [225] [226] Compositional System-Level Design Exploration with Planning of High-Level Synthesis [p. 641]
Liu, S: [483] [484] Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC [p. 1289]
Liu, S S-Y: [263] [264] Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization [p. 1391]
Liu, X: [285] [286] Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Liu, X-X: [443] [444] Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]; [539] [540] Parallel Statistical Analysis of Analog Circuits by GPU-accelerated Graph-based Approach [p. 852]; [541] [542] A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation [p. 1349]
Liu, Y: [289] [290] A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Lo Iacono, D: [315] [316] A Flexible and Fast Software Implementation of the FFT on the BPE Platform [p. 1467]
Lochner, H: [9] [10] Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Loghi, M: [543] [544] Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Loi, I: [137] [138] A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]; [143] [144] An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Lorentz, V: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Louerat, M-M: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Lu, J: [321] [322] S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Lu, K: [545] [546] Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level [p. 135]
Lu, S-L: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Lu, Z: [481] [482] Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]; [483] [484] Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC [p. 1289]
Lugli, P: [273] [274] Characterization of the Bistable Ring PUF [p. 1459]
Lukasiewycz, M: [435] [436] Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]; [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; [235] [236] Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Luo, Y: [233] [234] A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Luy, L: [459] [460] Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Lv, J: [381] [382] Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]

M

Macii, A: [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Macii, E: [217] [218] IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]; [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]; [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]; [543] [544] Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Mackay, K: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Madsen, J: [417] [418] Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Maffione, M: [111] [112] SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Magno, M: [133] [134] Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Mahapatra, R N: [507] [508] A Fast, Source-Synchronous Ring-based Network-on-Chip Design [p. 1489]
Mahmood, H: [543] [544] Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Mahmood, Z: [325] [326] An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems [p. 1203]
Mai, K: [213] [214] Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Majumdar, S: [423] [424] A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Makosiej, A: [51] [52] Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Makris, Y: [493] [494] Post-Deployment Trust Evaluation in Wireless Cryptographic ICs [p. 965]
Maliuk, D: [493] [494] Post-Deployment Trust Evaluation in Wireless Cryptographic ICs [p. 965]
Mammo, B: [151] [152] Approximating Checkers for Simulation Acceleration [p. 153]
Mancini, S: [547] [548] Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow [p. 1130]
Mandal, A: [507] [508] A Fast, Source-Synchronous Ring-based Network-on-Chip Design [p. 1489]
Mangassarian, H: [503] [504] Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Marconi, T: [269] [270] Online Scheduling for Multi-Core Shared Reconfigurable Fabric [p. 582]
Marculescu, D: [249] [250] Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]; [525] [526] Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Mariani, G: [153] [154] Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Maricau, E: [335] [336] Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]; [337] [338] Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Marin, P: [123] [124] Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Marinho, J M: [549] [550] Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]
Marinissen, E J: [89] [90] EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]; [551] [552] Challenges and Emerging Solutions in Testing TSV-Based 2 1/2D-and 3D-Stacked ICs - Invited Paper [p. 1277]
Marinkovic, S: [133] [134] Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Markov, I L: [239] [240] RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Marongiu, A: [135] [136] Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]; [11] [12] Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Marques-Silva, J: [259] [260] QBF-Based Boolean Function Bi-Decomposition [p. 816]
Marsh, G: [423] [424] A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Martin, G: [465] [466] Virtual Platforms: Breaking New Grounds [p. 685]
Martina, M: [297] [298] A Network-on-Chip-based Turbo/LDPC Decoder Architecture [p. 1525]
Martinez Nova, A: [427] [428] Optimization Intensive Energy Harvesting [p. 272]
Marwedel, P: [301] [302] Multi-Objective Aware Extraction of Task-Level Parallelism Using Genetic Algorithms [p. 394]
Masera, G: [297] [298] A Network-on-Chip-based Turbo/LDPC Decoder Architecture [p. 1525]
Masrur, A: [63] [64] Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Masson, G: [553] [554] UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications - Invited Paper [p. 1160]
Massouri, A: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Matthes, M: [117] [118] Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Maurine, P: [147] [148] Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
McConaghy, T: [337] [338] Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Meder, K: [555] [556] The Mobile Society - Chances and Challenges for Micro- and Power Electronics [p. 1]
Meissner, M: [459] [460] Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Melikyan, V: [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Meloni, P: [533] [534] Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Melpignano, D: [139] [140] P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
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Meng, J: [305] [306] Analysis and Runtime Management of 3D Systems with Stacked DRAM for Boosting Energy Efficiency [p. 611]
Mesman, B: [303] [304] Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Messaoudi, J: [429] [430] A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems [p. 751]
Meumeu Yomsi, P: [157] [158] Challenges and New Trends in Probabilistic Timing Analysis [p. 810]
Meyer zu Bexten, V: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Meyer, M: [515] [516] Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Miele, A: [173] [174] An Adaptive Approach for Online Fault Management in Many-Core Architectures [p. 1429]
Milbredt, P: [435] [436] Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Miller, B: [433] [434] MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups [p. 1417]
Miller, C: [123] [124] Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Mir, S: [5] [6] Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Miremadi, S G: [373] [374] SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Miryala, S: [217] [218] IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]
Mishchenko, A: [193] [194] Mapping into LUT Structures [p. 1579]
Mishra, P: [557] [558] Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols [p. 3]
Misra, S K: [237] [238] A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Mitea, O: [459] [460] Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Mitra, S: [95] [96] Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]; [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Mitra, T: [269] [270] Online Scheduling for Multi-Core Shared Reconfigurable Fabric [p. 582]
Mittag, M: [489] [490] Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Mittermaier, N: [89] [90] EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Mohalik, S: [559] [560] Verifying Timing Synchronization Constraints in Distributed Embedded Architectures [p. 200]
Mohammadi, A: [373] [374] SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Mohanram, K: [367] [368] High Performance Reliable Variable Latency Carry Select Addition [p. 1257]
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Monga, I: [35] [36] Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers [p. 175]
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Moses, J: [27] [28] PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Moshovos, A: [1] [2] Toward Virtualizing Branch Direction Prediction [p. 455]
Mueller, W: [131] [132] MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Mueller-Gritschneder, D: [545] [546] Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level [p. 135]; [565] [566] Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]
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N

Nagel,: [401] [402] Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) [p. 1161]
Nahir, A: [151] [152] Approximating Checkers for Simulation Acceleration [p. 153]
Nair, I: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Namyst, R: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Narayanan, R: [317] [318] Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Narayanan, V: [523] [524] Hazard Driven Test Generation for SMT Processors [p. 256]; [479] [480] An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Nassar, M: [323] [324] RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Nassery, A: [567] [568] An Analytical Technique for Characterization of Transceiver IQ Imbalances in the Loop-Back Mode [p. 1084]
Nazhandali, L: [419] [420] ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Nazin, S A: [561] [562] Yield Optimization for Radio Frequency Receiver at System Level [p. 848]
Nelis, V: [549] [550] Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]
Neogy, A: [569] [570] Analysis and Design of Sub-Harmonically Injection Locked Oscillators [p. 1209]
Newby, T: [119] [120] SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Newell, D: [27] [28] PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Nicolaidis, M: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Nicolau, A: [107] [108] VaMV: Variability-aware Memory Virtualization [p. 284]
Nikolov, H: [93] [94] A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Nirmaier, T: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Novo, D: [205] [206] Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]

O

O'Flynn, B: [133] [134] Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Oertel, M: [379] [380] Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Olivo, P: [155] [156] A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Osello, A: [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Osewold, C: [359] [360] Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]
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Ozev, S: [567] [568] An Analytical Technique for Characterization of Transceiver IQ Imbalances in the Loop-Back Mode [p. 1084]

P

Palermo, G: [153] [154] Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Panagopoulos, G: [81] [82] A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach [p. 1443]
Pang, G K H: [537] [538] An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]
Papaefstathiou, I: [207] [208] An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Parameswaran, S: [531] [532] Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors [p. 875]
Park, M S: [479] [480] An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Park, S: [17] [18] Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; [291] [292] State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Park, S P: [445] [446] Layout-Aware Optimization of STT MRAMs [p. 1455]
Parsa, R: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Partlo III, W E: [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Patel, H D: [571] [572] An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture [p. 659]
Patil, S: [229] [230] Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]; [221] [222] Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Patti, E: [3] [4] Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Pautet, L: [181] [182] Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Pavlidis, V F: [339] [340] Voltage Propagation Method for 3-D Power Grid Analysis [p. 844]
Pecheux, F: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Pedram, M: [243] [244] Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; [21] [22] An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]; [355] [356] Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric [p. 840]; [245] [246] State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Pelissier, M: [553] [554] UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications - Invited Paper [p. 1160]
Pellegrini, A: [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Pelz, G: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Peng, Z: [377] [378] Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]
Peraldi-Frati, M-A: [169] [170] Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Peranandam, P: [413] [414] An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Pereira, E: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Perin, G: [147] [148] Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
Perlo, P: [171] [172] Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Petracca, M: [225] [226] Compositional System-Level Design Exploration with Planning of High-Level Synthesis [p. 641]
Petters, S M: [549] [550] Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]
Pham, H-M: [177] [178] UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Pidan, D: [151] [152] Approximating Checkers for Simulation Acceleration [p. 153]
Piguet, C: [563] [564] Fixed Origin Corner Square Inspection Layout Regularity Metric [p. 1397]
Pillement, S: [177] [178] UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Pimentel, A D: [573] [574] Design Space Pruning through Hybrid Analysis in System-level Design Space Exploration [p. 781]
Pineda de Gyvez, J: [399] [400] Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems [p. 1048]
Pino, R E: [163] [164] Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Pino, Y: [497] [498] Logic Encryption: A Fault Analysis Perspective [p. 953]
Piscitelli, R: [573] [574] Design Space Pruning through Hybrid Analysis in System-level Design Space Exploration [p. 781]
Pllana, S: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Plosila, J: [319] [320] CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Plyaskin, R: [465] [466] Virtual Platforms: Breaking New Grounds [p. 685]
Polian, I: [121] [122] On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]
Pomata, S: [533] [534] Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Poncino, M: [217] [218] IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]; [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]; [243] [244] Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; [543] [544] Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Pons, M: [563] [564] Fixed Origin Corner Square Inspection Layout Regularity Metric [p. 1397]
Pontes, J: [215] [216] An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design [p. 224]
Pop, P: [417] [418] Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Poplavko, P: [411] [412] SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Popovici, E: [133] [134] Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Popp, R M: [25] [26] Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Potkonjak, M: [283] [284] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]; [427] [428] Optimization Intensive Energy Harvesting [p. 272]
Poulos, Z: [57] [58] Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Pourshaghaghi, H R: [399] [400] Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems [p. 1048]
Prakash, A: [571] [572] An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture [p. 659]
Pravadelli, G: [347] [348] Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]; [131] [132] MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Prenat, G: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Prinetto, P: [155] [156] A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Prochazka, W: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Provine, J: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Puaut, I: [549] [550] Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]

Q

Qian, Z: [575] [576] A Flit-level Speedup Scheme for Network-on-Chips Using Self-Reconfigurable Bi-directional Channels [p. 1295]
Qin, X: [557] [558] Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols [p. 3]
Qin, Z: [535] [536] A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Quaglia, D: [371] [372] Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]; [405] [406] Predictive Control of Networked Control Systems over Differentiated Services Lossy Networks [p. 1245]
Quan, G: [391] [392] Neighbor-Aware Dynamic Thermal Management for Multi-core Platform [p. 187]; [393] [394] Harmonic Semi-Partitioned Scheduling for Fixed-Priority Real-Time Tasks on Multi-Core Platform [p. 503]
Quinton, S: [387] [388] Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]; [157] [158] Challenges and New Trends in Probabilistic Timing Analysis [p. 810]

R

Raabe, A: [167] [168] Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]; [513] [514] Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
Rafaila, M: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Raffo, L: [533] [534] Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Ragel, R: [531] [532] Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors [p. 875]
Rahimi, A: [141] [142] Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]
Rahman, M: [577] [578] Post-Synthesis Leakage Power Minimization [p. 99]
Rajeev, A C: [559] [560] Verifying Timing Synchronization Constraints in Distributed Embedded Architectures [p. 200]
Rajendran, J: [497] [498] Logic Encryption: A Fault Analysis Perspective [p. 953]
Rambo, E A: [353] [354] On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Ramesh, S: [559] [560] Verifying Timing Synchronization Constraints in Distributed Embedded Architectures [p. 200]; [413] [414] An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Ranganathan, N: [579] [580] Runtime Power Gating in Caches of GPUs for Leakage Energy Savings [p. 300]; [517] [518] Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder [p. 721]
Ranjan, A: [329] [330] PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations [p. 550]
Raviram, S: [413] [414] An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Ray, S: [195] [196] Scalable Progress Verification in Credit-Based Flow-Control Systems [p. 905]; [193] [194] Mapping into LUT Structures [p. 1579]
Raychowdhury, A: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Rehman, S: [463] [464] Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Reinhardt, A: [561] [562] Yield Optimization for Radio Frequency Receiver at System Level [p. 848]
Reinig, H: [565] [566] Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]
Reinman, G: [283] [284] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Richards, A: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Richter, M: [231] [232] Test Pin Count Reduction for NoC-based Test Delivery in Multicore SOCs [p. 787]
Rimon, M: [501] [502] Generating Instruction Streams Using Abstract CSP [p. 15]
Rinaudo, S: [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Rivers, J: [89] [90] EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Rivers, J A: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Rochange, C: [425] [426] Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Rofouei, M: [427] [428] Optimization Intensive Energy Harvesting [p. 272]
Rohfleisch, B: [455] [456] Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Roncella, R: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Roop, P S: [105] [106] Correct-by-Construction Multi-Component SoC Design [p. 647]
Rosenstiel, W: [25] [26] Beyond CMOS - Benchmarking for Future Technologies [p. 129]; [199] [200] Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]; [203] [204] Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies [p. 862]; [489] [490] Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Rosiére, M: [345] [346] An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Rosing, T S: [35] [36] Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers [p. 175]; [85] [86] TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs [p. 593]; [487] [488] MAPG: Memory Access Power Gating [p. 1054]
Rottmann, A: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Rousseau, F: [547] [548] Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow [p. 1130]
Rox, J: [383] [384] Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]
Roy, K: [81] [82] A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach [p. 1443]; [445] [446] Layout-Aware Optimization of STT MRAMs [p. 1455]
Roy, S: [579] [580] Runtime Power Gating in Caches of GPUs for Leakage Energy Savings [p. 300]; [161] [162] An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Roychowdhury, J: [569] [570] Analysis and Design of Sub-Harmonically Injection Locked Oscillators [p. 1209]
Rozic, V: [581] [582] Low-Cost Implementations of On-the-Fly Tests for Random Number Generators [p. 959]
Rudolf, R: [583] [584] Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Ruehrmair, U: [273] [274] Characterization of the Bistable Ring PUF [p. 1459]
Ruggiero, M: [75] [76] Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Rupnow, K: [257] [258] Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]

S

Sabarad, J: [479] [480] An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Sabena, D: [585] [586] A New SBST Algorithm for Testing the Register File of VLIW Processors [p. 412]
Sabry, M M: [73] [74] Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation [p. 599]; [77] [78] A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Sadeghi, A-R: [327] [328] PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Sadooghi-Alvandi, M: [1] [2] Toward Virtualizing Branch Direction Prediction [p. 455]
Sadri, M: [99] [100] Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]
Safari, S: [21] [22] An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Sahlbach, H: [385] [386] A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]
Sai, B: [289] [290] A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Sainrat, P: [425] [426] Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Salajka, V: [587] [588] Towards New Applications of Multi-Function Logic: Image Multi-Filtering [p. 824]
Salcic, Z: [105] [106] Correct-by-Construction Multi-Component SoC Design [p. 647]
Saletti, R: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
San Segundo Bello, D: [431] [432] Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]
Sanchez, D: [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]
Sanders, B: [395] [396] Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Saponara, S: [397] [398] Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]; [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Saranovac, L: [205] [206] Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Sasao, T: [589] [590] Row-Shift Decompositions for Index Generation Functions [p. 1585]
Sassone, A: [87] [88] Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Satpathy, M: [413] [414] An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Sauer, M: [121] [122] On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]
Sawicki, J: [211] [212] Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Scarpelli, A: [171] [172] Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Schaumont, P: [419] [420] ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Schindler, W: [467] [468] Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models [p. 1179]
Schirner, G: [591] [592] Application-Specific Power-Efficient Approach for Reducing Register File Vulnerability [p. 574]
Schirrmeister, F: [465] [466] Virtual Platforms: Breaking New Grounds [p. 685]
Schlichtmann, U: [545] [546] Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level [p. 135]; [485] [486] Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]; [565] [566] Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]; [273] [274] Characterization of the Bistable Ring PUF [p. 1459]
Schmutzler, C: [127] [128] On Demand Dependent Deactivation of Automotive ECUs [p. 69]
Schneider, R: [235] [236] Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Schoenmaker, W: [117] [118] Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Schrijen, G-J: [593] [594] Comparative Analysis of SRAM Memories Used as PUF Primitives [p. 1319]
Schuchardt, M: [295] [296] Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Sciuto, D: [173] [174] An Adaptive Approach for Online Fault Management in Many-Core Architectures [p. 1429]
Scotti, S: [13] [14] Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Sebastian, M: [83] [84] Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Sebeke, C: [211] [212] Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Sechen, C: [577] [578] Post-Synthesis Leakage Power Minimization [p. 99]
Sekanina, L: [595] [596] A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits [p. 715]; [587] [588] Towards New Applications of Multi-Function Logic: Image Multi-Filtering [p. 824]
Sen, A: [343] [344] Verification Coverage of Embedded Multicore Applications [p. 252]
Senepa, L: [111] [112] SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Sengupta, R: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Sengupta, S: [237] [238] A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Shafiee, A: [29] [30] AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Shafique, M: [463] [464] Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Shah, H: [513] [514] Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
Shahid, M A: [597] [598] Cross Entropy Minimization for Efficient Estimation of SRAM Failure Rate [p. 230]
Shao, Z: [109] [110] 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]; [535] [536] A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Sharifi, S: [85] [86] TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs [p. 593]
Sharma, V: [71] [72] Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
She, D: [303] [304] Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Shen, C-C: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Shin, D: [245] [246] State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Shin, J: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Shoaib, M: [423] [424] A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]; [491] [492] Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals [p. 437]
Silvano, C: [153] [154] Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Sima, V-M: [153] [154] Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Simons, M: [127] [128] On Demand Dependent Deactivation of Automotive ECUs [p. 69]
Sinanoglu, O: [497] [498] Logic Encryption: A Fault Analysis Perspective [p. 953]
Singh, M: [451] [452] Multi-Token Resource Sharing for Pipelined Asynchronous Systems [p. 1191]
Singh, P: [523] [524] Hazard Driven Test Generation for SMT Processors [p. 256]
Sinha, R: [105] [106] Correct-by-Construction Multi-Component SoC Design [p. 647]
Sinkar, A A: [511] [512] Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors [p. 1134]
Smolinski, R: [19] [20] CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Soeken, M: [361] [362] Debugging of Inconsistent UML/OCL Models [p. 1078]; [363] [364] Eliminating Invariants in UML/OCL Models [p. 1142]
Song, W: [91] [92] Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Sonza Reorda, M: [585] [586] A New SBST Algorithm for Testing the Register File of VLIW Processors [p. 412]
Sotomayor Torres, C M: [25] [26] Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Soudris, D: [55] [56] A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Souissi, Y: [323] [324] RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Sridhar, A: [73] [74] Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation [p. 599]
Srivastav, M: [419] [420] ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Stattelmann, S: [199] [200] Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Stefan, R: [53] [54] A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Stefanni, F: [371] [372] Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Stefanov, T: [93] [94] A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Steger, C: [365] [366] Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Steinbach, D: [599] [600] Guidelines for Model Based Systems Engineering [p. 159]
Steininger, A: [435] [436] Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Steinmann, J: [201] [202] Optimal Energy Management and Recovery for FEV [p. 683]
Sterpone, L: [585] [586] A New SBST Algorithm for Testing the Register File of VLIW Processors [p. 412]
Stipic, S: [311] [312] TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Stoettinger, M: [475] [476] Side Channel Analysis of the SHA-3 Finalists [p. 1012]; [467] [468] Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models [p. 1179]
Stojilovic, M: [205] [206] Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Stratigopoulos, H: [337] [338] Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Stratigopoulos, H-G: [5] [6] Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Straube, S: [9] [10] Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Stripf, T: [125] [126] A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]
Strong, R: [487] [488] MAPG: Memory Access Power Gating [p. 1054]
Stuijk, S: [101] [102] Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]; [103] [104] Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Suaya, R: [325] [326] An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems [p. 1203]
Sun, F: [601] [602] Automatic Generation of Functional Models for Embedded Processor Extensions [p. 304]
Sun, G: [277] [278] 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]; [603] [604] Modeling and Design Exploration of FBDRAM as On-chip Memory [p. 1507]
Suri, B: [183] [184] A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Swick, R: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]

T

Taatizadeh, P: [583] [584] Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Tabkhi, H: [591] [592] Application-Specific Power-Efficient Approach for Reducing Register File Vulnerability [p. 574]
Tahar, S: [67] [68] Towards Improving Simulation of Analog Circuits Using Model Order Reduction [p. 1337]; [317] [318] Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Tahoori, M B: [407] [408] NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]; [159] [160] Layout-Driven Robustness Analysis for Misaligned Carbon Nanotubes in CNTFET-based Standard Cells [p. 1609]
Tamiya, Y: [477] [478] Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Tan, M: [285] [286] Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Tan, S X-D: [443] [444] Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]; [539] [540] Parallel Statistical Analysis of Analog Circuits by GPU-accelerated Graph-based Approach [p. 852]; [541] [542] A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation [p. 1349]
Tang, K-F: [293] [294] Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Tang, Q: [149] [150] Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Tang, W-C: [521] [522] Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]
Tasic, B: [337] [338] Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Teh, Y F: [575] [576] A Flit-level Speedup Scheme for Network-on-Chips Using Self-Reconfigurable Bi-directional Channels [p. 1295]
Tehranipoor, M: [331] [332] A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection [p. 1331]
Teich, J: [435] [436] Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]; [455] [456] Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Tenhunen, H: [319] [320] CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]; [267] [268] A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Tetzlaff, R: [209] [210] Memristor Technology in Future Electronic System Design [p. 592]
Thach, D: [477] [478] Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Thaler, A: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Thapliyal, H: [517] [518] Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder [p. 721]
Theelen, B: [499] [500] Model Checking of Scenario-Aware Dataflow with CADP [p. 653]
Theocharides, T: [605] [606] Towards Accurate Hardware Stereo Correspondence: A Real-Time FPGA Implementation of a Segmentation-Based Adaptive Support Weight Algorithm [p. 703]
Thibault, S: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Thiele, D: [389] [390] Optimizing Performance Analysis for Synchronous Dataflow Graphs with Shared Resources [p. 635]
Thomas, O: [51] [52] Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Tischendorf, C: [117] [118] Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Todorov, V: [565] [566] Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]
Todri, A: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Tokunaga, C: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Tomic, S: [311] [312] TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Tong, D: [285] [286] Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]; [321] [322] S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Topcuoglu, H R: [495] [496] Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Topham, N: [179] [180] Predicting Best Design Trade-offs: A Case Study in Processor Customization [p. 1030]
Torres, L: [147] [148] Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
Tosun, O: [495] [496] Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Traff, J L: [145] [146] Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Tretmans, J: [189] [190] State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Tristl, M: [453] [454] Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Trummer, R: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
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Tschanz, J: [59] [60] Design for Test and Reliability in Ultimate CMOS [p. 677]
Tsui, C-Y: [575] [576] A Flit-level Speedup Scheme for Network-on-Chips Using Self-Reconfigurable Bi-directional Channels [p. 1295]
Ttofis, C: [605] [606] Towards Accurate Hardware Stereo Correspondence: A Real-Time FPGA Implementation of a Segmentation-Based Adaptive Support Weight Algorithm [p. 703]
Tung, S-Y: [251] [252] Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Turturici, M: [397] [398] Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]
Tuveri, G: [533] [534] Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]

U

Ungerer, T: [425] [426] Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Unsal, O: [311] [312] TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]

V

Vahid, F: [433] [434] MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups [p. 1417]
Valero, M: [311] [312] TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
van Berkel, C H: [529] [530] A Complexity Adaptive Channel Estimator for Low Power [p. 1531]
van der Leest, V: [593] [594] Comparative Analysis of SRAM Memories Used as PUF Primitives [p. 1319]
van der Meijs, N: [149] [150] Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Vandling, G: [89] [90] EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Varman, P: [367] [368] High Performance Reliable Variable Latency Carry Select Addition [p. 1257]
Vasicek, Z: [595] [596] A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits [p. 715]
Vatajelu, E I: [403] [404] Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation [p. 1343]
Vaupel, M: [465] [466] Virtual Platforms: Breaking New Grounds [p. 685]
Vega, A: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Veljkovic, F: [581] [582] Low-Cost Implementations of On-the-Fly Tests for Random Number Generators [p. 959]
Veneris, A: [57] [58] Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]; [503] [504] Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Verbauwhede, I: [327] [328] PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]; [581] [582] Low-Cost Implementations of On-the-Fly Tests for Random Number Generators [p. 959]
Verma, N: [491] [492] Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals [p. 437]
Vincent, P: [553] [554] UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications - Invited Paper [p. 1160]
Vinco, S: [131] [132] MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Violante, M: [219] [220] An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation [p. 1433]
Virazel, A: [49] [50] Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Vivet, P: [215] [216] An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design [p. 224]
Vizzini, D: [261] [262] Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Vladimerescu, A: [51] [52] Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Voyiatzis, I: [607] [608] Input Vector Monitoring on Line Concurrent BIST Based on Multilevel Decoding Logic [p. 1251]
Vyagrheswarudu, N: [329] [330] PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations [p. 550]

W

Wajsbürt, F: [345] [346] An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Walravens, C: [341] [342] Design of a Low-Energy Data Processing Architecture for WSN Nodes [p. 570]
Wan, J: [505] [506] Monitoring Active Filters under Automotive Aging Scenarios with Embedded Instrument [p. 1096]
Wang, C: [609] [610] Extending the Lifetime of NAND Flash Memory by Salvaging Bad Blocks [p. 260]
Wang, C-Y: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Wang, H: [443] [444] Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]; [539] [540] Parallel Statistical Analysis of Analog Circuits by GPU-accelerated Graph-based Approach [p. 852]; [511] [512] Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors [p. 1134]; [541] [542] A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation [p. 1349]
Wang, J: [421] [422] A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Wang, K: [321] [322] S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Wang, L: [45] [46] Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Wang, S: [369] [370] Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Wang, S-C: [525] [526] Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Wang, T: [535] [536] A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Wang, X: [321] [322] S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]; [279] [280] Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Wang, Y: [243] [244] Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; [579] [580] Runtime Power Gating in Caches of GPUs for Leakage Energy Savings [p. 300]; [245] [246] State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]; [109] [110] 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]; [535] [536] A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]; [537] [538] An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]; [289] [290] A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Wang, Z: [461] [462] Accurate Source-Level Simulation of Embedded Software with Respect to Compiler Optimizations [p. 382]
Wassal, A G: [7] [8] Double-Patterning Friendly Grid-Based Detailed Routing with Online Conflict Resolution [p. 1475]
Watanabe, Y: [515] [516] Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Watt, J: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Weger, A J: [185] [186] Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Wehn, N: [31] [32] DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]; [143] [144] An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Weis, C: [31] [32] DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]; [143] [144] An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Weiss, R: [365] [366] Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Wenger, M: [97] [98] Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Wenninger, J: [45] [46] Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Werner, S: [129] [130] Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Whitty, S: [385] [386] A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]
Wilcock, R: [583] [584] Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Wille, R: [359] [360] Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]; [361] [362] Debugging of Inconsistent UML/OCL Models [p. 1078]; [363] [364] Eliminating Invariants in UML/OCL Models [p. 1142]
Williams, R S: [209] [210] Memristor Technology in Future Electronic System Design [p. 592]
Wilson, P: [583] [584] Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Wong, H-S P: [255] [256] Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Wong, N: [271] [272] Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]; [537] [538] An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]
Wong, W-F: [609] [610] Extending the Lifetime of NAND Flash Memory by Salvaging Bad Blocks [p. 260]
Wu, H: [499] [500] Model Checking of Scenario-Aware Dataflow with CADP [p. 653]
Wu, K-C: [525] [526] Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Wu, W: [471] [472] Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Wu, Y-L: [521] [522] Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]

X

Xhakoni, A: [431] [432] Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]
Xie, L: [333] [334] Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations [p. 1591]
Xie, Q: [243] [244] Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; [245] [246] State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Xie, Y: [277] [278] 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]; [603] [604] Modeling and Design Exploration of FBDRAM as On-chip Memory [p. 1507]
Xie, Z: [285] [286] Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Xing, X: [309] [310] Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Xu, C: [603] [604] Modeling and Design Exploration of FBDRAM as On-chip Memory [p. 1507]
Xu, Q: [375] [376] On Effective TSV Repair for 3D-Stacked ICs [p. 793]; [611] [612] Clock Skew Scheduling for Timing Speculation [p. 929]
Xu, Y: [455] [456] Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]; [271] [272] Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]

Y

Yakoushkin, S: [69] [70] Hybrid Simulation for Extensible Processor Cores [p. 288]
Yang, G: [267] [268] A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Yang, H: [289] [290] A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Yang, J: [281] [282] Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Yang, S: [187] [188] Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Yang, X: [521] [522] Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]
Yang, Y: [101] [102] Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]
Yang, Y-C: [247] [248] A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Yang, Y-S: [57] [58] Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Ye, R: [611] [612] Clock Skew Scheduling for Timing Speculation [p. 929]
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Z

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Zhao, S: [257] [258] Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
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Zheng, Y: [187] [188] Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
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