9.4 EU projects: Novel Platforms - from Self-Aware MPSoCs to Server Ecosystems

Time	Label	Presentation Title Authors
08:30	9.4.1	DREDBOX: MATERIALIZING A FULL-STACK RACK-SCALE SYSTEM PROTOTYPE OF A NEXT-GENERATION DISAGGREGATED DATACENTER Speaker: Dimitris Syrivelis, IBM Research, Ireland, GR Authors: Maciel Bielski¹, Ilias Syrirgos², Kostas Katrinis³, Dimitris Syrivelis³, Andrea Reale³, Dimitris Theodoropoulos⁴, Nikolaos Alachiotis⁵, Dionisios Pnevmatikatos⁶, Evert Pap⁷, George Zervas⁸, Vaibhawa Mishra⁸, Arsalan Saljoghei⁸, Alvise Rigo⁹, Jose Fernando Zazo¹⁰, Sergio Lopez-Buedo¹⁰, Ferad Zyulkyarov¹¹, Michael Enrico¹² and Osar-Gonzalez de Dios¹³ ¹Virtual Open Systems, FR; ²University of Thessaly, GR; ³IBM Research, Ireland, IE; ⁴Foundation for Research and Technology Hellas (FORTH), GR; ⁵Foundation for Research and Technologoy Hellas (FORTH), GR; ⁶ECE Department, Technical Univrsity of Crete & FORTH-ICS, GR; ⁷SINTECS, Netherlands, NL; ⁸University College London, GB; ⁹Virtual Open Systems, France, FR; ¹⁰NAUDIT HPCN, Spain, ES; ¹¹Barcelona Supercomputing Center, Spain, ES; ¹²POLATIS, UK, GB; ¹³TELEFONICA, Spain, ES Abstract Current datacenters are based on server machines, whose mainboard and hardware components form the baseline, monolithic building block that the rest of the system software, middleware and application stack are built upon. This leads to the following limitations: (a) resource proportionality of a multitray system is bounded by the basic building block (mainboard), (b) resource allocation to processes or virtual machines (VMs) is bounded by the available resources within the boundary of the mainboard, leading to spare resource fragmentation and inefficiencies, and (c) upgrades must be applied to each and every server even when only a specific component needs to be upgraded. The dRedBox project (Disaggregated Recursive Datacentre-ina- Box) addresses the above limitations, and proposes the next generation, low-power, across form-factor datacenters, departing from the paradigm of the mainboard-as-a-unit and enabling the creation of function-block-as-a-unit. Hardware-level disaggregation and software-defined wiring of resources is supported by a full-fledged Type-1 hypervisor that can execute commodity virtual machines, which communicate over a low-latency and high-throughput software-defined optical network. To evaluate its novel approach, dRedBox will demonstrate application execution in the domains of network functions virtualization, infrastructure analytics, and real-time video surveillance. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	9.4.2	AN ENERGY-EFFICIENT AND ERROR-RESILIENT SERVER ECOSYSTEM EXCEEDING CONSERVATIVE SCALING LIMITS Speaker: Georgios Karakonstantis, Queen, GB Authors: Georgios Karakonstantis¹, Konstantinos Tovletoglou², Lev Mukhanov¹, Hans Vandierendonck¹, Dimitrios Nikolopoulos², Peter Lawthers³, Panos Koutsovasilis⁴, Manolis Maroudas⁵, Christos D. Antonopoulos⁴, Christos Kalogirou⁴, Nikolaos Bellas⁶, Spyros Lalis⁴, Srikumar Venugopal⁷, Arnau Prat-Perez⁸, Alejandro Lampropulos⁹, Marios Kleanthous¹⁰, Andreas Diavastos¹¹, Zacharias Hadjilambrou¹¹, Panagiota Nikolaou¹¹, Yanos Sazeides¹², Pedro Trancoso¹¹, George Papadimitriou¹³, Manolis Kaliorakis¹³, Athanasios Chatzidimitriou¹³, Dimitris Gizopoulos¹³ and Shidhartha Das¹⁴ ¹Queen's University Belfast, GB; ²Queen's University of Belfast, GB; ³A.M.C.C. Deutschland, DE; ⁴University of Thessaly, GR; ⁵University of Thessaly, GB; ⁶University of Thessaly & CERTH, GR; ⁷IBM Research - Ireland, IE; ⁸Sparsity, ES; ⁹Worldsensing, ES; ¹⁰Meritorious, CY; ¹¹University of Cyprus, CY; ¹²u cyprus, CY; ¹³University of Athens, GR; ¹⁴ARM Ltd., GB Abstract The explosive growth of Internet-connected devices will soon result in a flood of generated data, which will increase the demand for network bandwidth as well as compute power to process the generated data. Consequently, there is a need for more energy efficient servers to empower traditional centralized Cloud data-centers as well as emerging decentralized data-centers at the Edges of the Cloud. In this paper, we present our approach, which aims at developing a new class of micro-servers - the UniServer - that exceed the conservative energy and performance scaling boundaries by introducing novel mechanisms at all layers of the design stack. The main idea lies on the realization of the intrinsic hardware heterogeneity and the development of mechanisms that will automatically expose the unique varying capabilities of each hardware component within commercial micro-servers and allow their operation at new extended operating points. Low overhead schemes are employed to monitor and predict the hardware behavior and report it to the system software. The system software including a virtualization and resource management layer is responsible for optimizing the system operation in terms of energy or performance, while guaranteeing non-disruptive operation under the extended operating points. Our characterization results on a 64-bit ARMv8 micro-server in 28nm process reveal large voltage margins in terms of Vmin variation among the 8 cores of the CPU chip, among 3 different sigma chips, and among different benchmarks with the potential to obtain up-to 38.8% energy savings. Similarly, DRAM characterizations show that refresh rate and voltage can be relaxed by 43x and 5%, respectively, leading to 23.2% power savings on average. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	9.4.3	THE TRANSPRECISION COMPUTING PARADIGM: CONCEPT, DESIGN, AND APPLICATIONS Speaker: Dionysios Diamantopoulos, IBM Research - Zurich, CH Authors: Cristiano Malossi¹, Michael Schaffner², Anca Molnos³, Luca Gammaitoni⁴, Giuseppe Tagliavini⁵, Andrew Emerson⁶, Andrés Tomás⁷, Dimitrios S. Nikolopoulos⁸, Eric Flamand⁹ and Norbert Wehn¹⁰ ¹IBM Research - Zurich, CH; ²ETHZ, CH; ³CEA, FR; ⁴Università di Perugia, IT; ⁵Università di Bologna, IT; ⁶CINECA, IT; ⁷Universitat Jaume I, ES; ⁸Queen's University of Belfast, GB; ⁹GreenWaves Technologies, FR; ¹⁰University of Kaiserslautern, DE Abstract Guaranteed numerical precision of each elementary step in a complex computation has been the mainstay of traditional computing systems for many years. This era, fueled by Moore's law and the constant exponential improvement in computing efficiency, is at its twilight: from tiny nodes of the Internet-of-Things, to large HPC computing centers, sub-picoJoule/operation energy efficiency is essential for practical realizations. To overcome the power wall, a shift from traditional computing paradigms is now mandatory. In this paper we present the driving motivations, roadmap, and expected impact of the European project OPRECOMP. OPRECOMP aims to (i) develop the first complete transprecision computing framework, (ii) apply it to a wide range of hardware platforms, from the sub-milliWatt up to the MegaWatt range, and (iii) demonstrate impact in a wide range of computational domains, spanning IoT, Big Data Analytics, Deep Learning, and HPC simulations. By combining together into a seamless design transprecision advances in devices, circuits, software tools, and algorithms, we expect to achieve major energy efficiency improvements, even when there is no freedom to relax end-to-end application quality of results. Indeed, OPRECOMP aims at demolishing the ultra-conservative ``precise'' computing abstraction, replacing it with a more flexible and efficient one, namely transprecision computing. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session Coffee Break in Exhibition Area Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 21, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 22, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00 Keynote Lecture in "Saal 2" 13:20 - 13:50 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

08:30

9.4.1

DREDBOX: MATERIALIZING A FULL-STACK RACK-SCALE SYSTEM PROTOTYPE OF A NEXT-GENERATION DISAGGREGATED DATACENTER
Speaker:
Dimitris Syrivelis, IBM Research, Ireland, GR
Authors:
Maciel Bielski¹, Ilias Syrirgos², Kostas Katrinis³, Dimitris Syrivelis³, Andrea Reale³, Dimitris Theodoropoulos⁴, Nikolaos Alachiotis⁵, Dionisios Pnevmatikatos⁶, Evert Pap⁷, George Zervas⁸, Vaibhawa Mishra⁸, Arsalan Saljoghei⁸, Alvise Rigo⁹, Jose Fernando Zazo¹⁰, Sergio Lopez-Buedo¹⁰, Ferad Zyulkyarov¹¹, Michael Enrico¹² and Osar-Gonzalez de Dios¹³
¹Virtual Open Systems, FR; ²University of Thessaly, GR; ³IBM Research, Ireland, IE; ⁴Foundation for Research and Technology Hellas (FORTH), GR; ⁵Foundation for Research and Technologoy Hellas (FORTH), GR; ⁶ECE Department, Technical Univrsity of Crete & FORTH-ICS, GR; ⁷SINTECS, Netherlands, NL; ⁸University College London, GB; ⁹Virtual Open Systems, France, FR; ¹⁰NAUDIT HPCN, Spain, ES; ¹¹Barcelona Supercomputing Center, Spain, ES; ¹²POLATIS, UK, GB; ¹³TELEFONICA, Spain, ES
Abstract
Current datacenters are based on server machines, whose mainboard and hardware components form the baseline, monolithic building block that the rest of the system software, middleware and application stack are built upon. This leads to the following limitations: (a) resource proportionality of a multitray system is bounded by the basic building block (mainboard), (b) resource allocation to processes or virtual machines (VMs) is bounded by the available resources within the boundary of the mainboard, leading to spare resource fragmentation and inefficiencies, and (c) upgrades must be applied to each and every server even when only a specific component needs to be upgraded. The dRedBox project (Disaggregated Recursive Datacentre-ina- Box) addresses the above limitations, and proposes the next generation, low-power, across form-factor datacenters, departing from the paradigm of the mainboard-as-a-unit and enabling the creation of function-block-as-a-unit. Hardware-level disaggregation and software-defined wiring of resources is supported by a full-fledged Type-1 hypervisor that can execute commodity virtual machines, which communicate over a low-latency and high-throughput software-defined optical network. To evaluate its novel approach, dRedBox will demonstrate application execution in the domains of network functions virtualization, infrastructure analytics, and real-time video surveillance.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:00

9.4.2

AN ENERGY-EFFICIENT AND ERROR-RESILIENT SERVER ECOSYSTEM EXCEEDING CONSERVATIVE SCALING LIMITS
Speaker:
Georgios Karakonstantis, Queen, GB
Authors:
Georgios Karakonstantis¹, Konstantinos Tovletoglou², Lev Mukhanov¹, Hans Vandierendonck¹, Dimitrios Nikolopoulos², Peter Lawthers³, Panos Koutsovasilis⁴, Manolis Maroudas⁵, Christos D. Antonopoulos⁴, Christos Kalogirou⁴, Nikolaos Bellas⁶, Spyros Lalis⁴, Srikumar Venugopal⁷, Arnau Prat-Perez⁸, Alejandro Lampropulos⁹, Marios Kleanthous¹⁰, Andreas Diavastos¹¹, Zacharias Hadjilambrou¹¹, Panagiota Nikolaou¹¹, Yanos Sazeides¹², Pedro Trancoso¹¹, George Papadimitriou¹³, Manolis Kaliorakis¹³, Athanasios Chatzidimitriou¹³, Dimitris Gizopoulos¹³ and Shidhartha Das¹⁴
¹Queen's University Belfast, GB; ²Queen's University of Belfast, GB; ³A.M.C.C. Deutschland, DE; ⁴University of Thessaly, GR; ⁵University of Thessaly, GB; ⁶University of Thessaly & CERTH, GR; ⁷IBM Research - Ireland, IE; ⁸Sparsity, ES; ⁹Worldsensing, ES; ¹⁰Meritorious, CY; ¹¹University of Cyprus, CY; ¹²u cyprus, CY; ¹³University of Athens, GR; ¹⁴ARM Ltd., GB
Abstract
The explosive growth of Internet-connected devices will soon result in a flood of generated data, which will increase the demand for network bandwidth as well as compute power to process the generated data. Consequently, there is a need for more energy efficient servers to empower traditional centralized Cloud data-centers as well as emerging decentralized data-centers at the Edges of the Cloud. In this paper, we present our approach, which aims at developing a new class of micro-servers - the UniServer - that exceed the conservative energy and performance scaling boundaries by introducing novel mechanisms at all layers of the design stack. The main idea lies on the realization of the intrinsic hardware heterogeneity and the development of mechanisms that will automatically expose the unique varying capabilities of each hardware component within commercial micro-servers and allow their operation at new extended operating points. Low overhead schemes are employed to monitor and predict the hardware behavior and report it to the system software. The system software including a virtualization and resource management layer is responsible for optimizing the system operation in terms of energy or performance, while guaranteeing non-disruptive operation under the extended operating points. Our characterization results on a 64-bit ARMv8 micro-server in 28nm process reveal large voltage margins in terms of Vmin variation among the 8 cores of the CPU chip, among 3 different sigma chips, and among different benchmarks with the potential to obtain up-to 38.8% energy savings. Similarly, DRAM characterizations show that refresh rate and voltage can be relaxed by 43x and 5%, respectively, leading to 23.2% power savings on average.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:30

9.4.3

THE TRANSPRECISION COMPUTING PARADIGM: CONCEPT, DESIGN, AND APPLICATIONS
Speaker:
Dionysios Diamantopoulos, IBM Research - Zurich, CH
Authors:
Cristiano Malossi¹, Michael Schaffner², Anca Molnos³, Luca Gammaitoni⁴, Giuseppe Tagliavini⁵, Andrew Emerson⁶, Andrés Tomás⁷, Dimitrios S. Nikolopoulos⁸, Eric Flamand⁹ and Norbert Wehn¹⁰
¹IBM Research - Zurich, CH; ²ETHZ, CH; ³CEA, FR; ⁴Università di Perugia, IT; ⁵Università di Bologna, IT; ⁶CINECA, IT; ⁷Universitat Jaume I, ES; ⁸Queen's University of Belfast, GB; ⁹GreenWaves Technologies, FR; ¹⁰University of Kaiserslautern, DE
Abstract
Guaranteed numerical precision of each elementary step in a complex computation has been the mainstay of traditional computing systems for many years. This era, fueled by Moore's law and the constant exponential improvement in computing efficiency, is at its twilight: from tiny nodes of the Internet-of-Things, to large HPC computing centers, sub-picoJoule/operation energy efficiency is essential for practical realizations. To overcome the power wall, a shift from traditional computing paradigms is now mandatory. In this paper we present the driving motivations, roadmap, and expected impact of the European project OPRECOMP. OPRECOMP aims to (i) develop the first complete transprecision computing framework, (ii) apply it to a wide range of hardware platforms, from the sub-milliWatt up to the MegaWatt range, and (iii) demonstrate impact in a wide range of computational domains, spanning IoT, Big Data Analytics, Deep Learning, and HPC simulations. By combining together into a seamless design transprecision advances in devices, circuits, software tools, and algorithms, we expect to achieve major energy efficiency improvements, even when there is no freedom to relax end-to-end application quality of results. Indeed, OPRECOMP aims at demolishing the ultra-conservative ``precise'' computing abstraction, replacing it with a more flexible and efficient one, namely transprecision computing.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

End of session
Coffee Break in Exhibition Area

Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD).

Lunch Breaks (Großer Saal + Saal 1)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 20, 2018