Date: Thursday 22 March 2018
Time: 08:30 - 10:00
Location / Room: Konf. 2
Chair:
Martin Schoeberl, Technical University of Denmark, DK
Co-Chair:
Flavius Gruian, Lund University, SE
This session presents three EU projects. The EU projects are: dReDBox—developing the next generation, low-power, across form-factor datacenters, enabling the creation of A338:AN521-as-a-unit, UniServer—developing a universal system architecture and software ecosystem for servers targeting cloud data-centers as well as upcoming edge-computing markets and OPRECOMP—developing concepts, methods, hardware and software building blocks for practical transprecision computing systems.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.4.1 | DREDBOX: MATERIALIZING A FULL-STACK RACK-SCALE SYSTEM PROTOTYPE OF A NEXT-GENERATION DISAGGREGATED DATACENTER Speaker: Dimitris Syrivelis, IBM Research, Ireland, GR Authors: Maciel Bielski1, Ilias Syrirgos2, Kostas Katrinis3, Dimitris Syrivelis3, Andrea Reale3, Dimitris Theodoropoulos4, Nikolaos Alachiotis5, Dionisios Pnevmatikatos6, Evert Pap7, George Zervas8, Vaibhawa Mishra8, Arsalan Saljoghei8, Alvise Rigo9, Jose Fernando Zazo10, Sergio Lopez-Buedo10, Ferad Zyulkyarov11, Michael Enrico12 and Osar-Gonzalez de Dios13 1Virtual Open Systems, FR; 2University of Thessaly, GR; 3IBM Research, Ireland, IE; 4Foundation for Research and Technology Hellas (FORTH), GR; 5Foundation for Research and Technologoy Hellas (FORTH), GR; 6ECE Department, Technical Univrsity of Crete & FORTH-ICS, GR; 7SINTECS, Netherlands, NL; 8University College London, GB; 9Virtual Open Systems, France, FR; 10NAUDIT HPCN, Spain, ES; 11Barcelona Supercomputing Center, Spain, ES; 12POLATIS, UK, GB; 13TELEFONICA, Spain, ES Abstract Current datacenters are based on server machines, whose mainboard and hardware components form the baseline, monolithic building block that the rest of the system software, middleware and application stack are built upon. This leads to the following limitations: (a) resource proportionality of a multitray system is bounded by the basic building block (mainboard), (b) resource allocation to processes or virtual machines (VMs) is bounded by the available resources within the boundary of the mainboard, leading to spare resource fragmentation and inefficiencies, and (c) upgrades must be applied to each and every server even when only a specific component needs to be upgraded. The dRedBox project (Disaggregated Recursive Datacentre-ina- Box) addresses the above limitations, and proposes the next generation, low-power, across form-factor datacenters, departing from the paradigm of the mainboard-as-a-unit and enabling the creation of function-block-as-a-unit. Hardware-level disaggregation and software-defined wiring of resources is supported by a full-fledged Type-1 hypervisor that can execute commodity virtual machines, which communicate over a low-latency and high-throughput software-defined optical network. To evaluate its novel approach, dRedBox will demonstrate application execution in the domains of network functions virtualization, infrastructure analytics, and real-time video surveillance. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.4.2 | AN ENERGY-EFFICIENT AND ERROR-RESILIENT SERVER ECOSYSTEM EXCEEDING CONSERVATIVE SCALING LIMITS Speaker: Georgios Karakonstantis, Queen, GB Authors: Georgios Karakonstantis1, Konstantinos Tovletoglou2, Lev Mukhanov1, Hans Vandierendonck1, Dimitrios Nikolopoulos2, Peter Lawthers3, Panos Koutsovasilis4, Manolis Maroudas5, Christos D. Antonopoulos4, Christos Kalogirou4, Nikolaos Bellas6, Spyros Lalis4, Srikumar Venugopal7, Arnau Prat-Perez8, Alejandro Lampropulos9, Marios Kleanthous10, Andreas Diavastos11, Zacharias Hadjilambrou11, Panagiota Nikolaou11, Yanos Sazeides12, Pedro Trancoso11, George Papadimitriou13, Manolis Kaliorakis13, Athanasios Chatzidimitriou13, Dimitris Gizopoulos13 and Shidhartha Das14 1Queen's University Belfast, GB; 2Queen's University of Belfast, GB; 3A.M.C.C. Deutschland, DE; 4University of Thessaly, GR; 5University of Thessaly, GB; 6University of Thessaly & CERTH, GR; 7IBM Research - Ireland, IE; 8Sparsity, ES; 9Worldsensing, ES; 10Meritorious, CY; 11University of Cyprus, CY; 12u cyprus, CY; 13University of Athens, GR; 14ARM Ltd., GB Abstract The explosive growth of Internet-connected devices will soon result in a flood of generated data, which will increase the demand for network bandwidth as well as compute power to process the generated data. Consequently, there is a need for more energy efficient servers to empower traditional centralized Cloud data-centers as well as emerging decentralized data-centers at the Edges of the Cloud. In this paper, we present our approach, which aims at developing a new class of micro-servers - the UniServer - that exceed the conservative energy and performance scaling boundaries by introducing novel mechanisms at all layers of the design stack. The main idea lies on the realization of the intrinsic hardware heterogeneity and the development of mechanisms that will automatically expose the unique varying capabilities of each hardware component within commercial micro-servers and allow their operation at new extended operating points. Low overhead schemes are employed to monitor and predict the hardware behavior and report it to the system software. The system software including a virtualization and resource management layer is responsible for optimizing the system operation in terms of energy or performance, while guaranteeing non-disruptive operation under the extended operating points. Our characterization results on a 64-bit ARMv8 micro-server in 28nm process reveal large voltage margins in terms of Vmin variation among the 8 cores of the CPU chip, among 3 different sigma chips, and among different benchmarks with the potential to obtain up-to 38.8% energy savings. Similarly, DRAM characterizations show that refresh rate and voltage can be relaxed by 43x and 5%, respectively, leading to 23.2% power savings on average. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.4.3 | THE TRANSPRECISION COMPUTING PARADIGM: CONCEPT, DESIGN, AND APPLICATIONS Speaker: Dionysios Diamantopoulos, IBM Research - Zurich, CH Authors: Cristiano Malossi1, Michael Schaffner2, Anca Molnos3, Luca Gammaitoni4, Giuseppe Tagliavini5, Andrew Emerson6, Andrés Tomás7, Dimitrios S. Nikolopoulos8, Eric Flamand9 and Norbert Wehn10 1IBM Research - Zurich, CH; 2ETHZ, CH; 3CEA, FR; 4Università di Perugia, IT; 5Università di Bologna, IT; 6CINECA, IT; 7Universitat Jaume I, ES; 8Queen's University of Belfast, GB; 9GreenWaves Technologies, FR; 10University of Kaiserslautern, DE Abstract Guaranteed numerical precision of each elementary step in a complex computation has been the mainstay of traditional computing systems for many years. This era, fueled by Moore's law and the constant exponential improvement in computing efficiency, is at its twilight: from tiny nodes of the Internet-of-Things, to large HPC computing centers, sub-picoJoule/operation energy efficiency is essential for practical realizations. To overcome the power wall, a shift from traditional computing paradigms is now mandatory. In this paper we present the driving motivations, roadmap, and expected impact of the European project OPRECOMP. OPRECOMP aims to (i) develop the first complete transprecision computing framework, (ii) apply it to a wide range of hardware platforms, from the sub-milliWatt up to the MegaWatt range, and (iii) demonstrate impact in a wide range of computational domains, spanning IoT, Big Data Analytics, Deep Learning, and HPC simulations. By combining together into a seamless design transprecision advances in devices, circuits, software tools, and algorithms, we expect to achieve major energy efficiency improvements, even when there is no freedom to relax end-to-end application quality of results. Indeed, OPRECOMP aims at demolishing the ultra-conservative ``precise'' computing abstraction, replacing it with a more flexible and efficient one, namely transprecision computing. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018
Wednesday, March 21, 2018
Thursday, March 22, 2018
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