6.3 Advances in AMS/RF Design & Test Automation and Beyond

Time	Label	Presentation Title Authors
11:00	6.3.1	ENHANCED ANALOG AND RF IC SIZING METHODOLOGY USING PCA AND NSGA-II OPTIMIZATION KERNEL Speaker: Nuno Lourenco, Instituto de Telecomunicações, PT Authors: Tiago Pessoa, Nuno Lourenco, Ricardo Martins, Ricardo Povoa and Nuno Horta, Instituto de Telecomunicações /Instituto Superior Técnico – Universidade de Lisboa, PT Abstract State-of-the-art design of analog and radio frequency integrated circuits is often accomplished using sizing optimization. In this paper, an innovative combination of principal component analysis (PCA) and evolutionary computation is used to increase the optimizer's efficiency. The adopted NSGA-II optimization kernel is improved by applying the genetic operators of mutation and crossover on a transformed design-space, obtained from the latest set of solutions (the parents) using PCA. By applying crossover and mutation on variables that are projections of the principal components, the optimization moves more effectively, finding solutions with better performances, in the same amount of time, than the standard NSGA-II optimization kernel. The proposed method was validated in the optimization of two widely used analog circuits, an amplifier and a voltage controlled oscillator, reaching wider solutions sets, and in some cases, solutions sets that can be almost 3 times better in terms of hypervolume. Download Paper (PDF; Only available from the DATE venue WiFi)
11:30	6.3.2	A SYSTEMC-BASED SIMULATOR FOR DESIGN SPACE EXPLORATION OF SMART WIRELESS SYSTEMS Speaker: Gabriele Miorandi, University of Verona, IT Authors: Gabriele Miorandi¹, Francesco Stefanni², Federico Fraccaroli³ and Davide Quaglia¹ ¹University of Verona, IT; ²EDALab s.r.l., IT; ³Wagoo Italia s.r.l.s., IT Abstract Smart wireless techniques are at the core of many today's telecommunication and networked embedded systems where performance are enhanced by intertwining radio frequency (RF) and digital aspects. Therefore their design requires to focus on both domains. Traditional approaches for their simulation rely either on different domain-specific tools or on analog-mixed-signal modeling languages. In the former case, the simulation of the whole platform in the same session is not possible while in the latter case, simulation performance are limited by the computationally most intensive domain (usually RF). We present an extension of the SystemC Network Simulation Library that allows to simulate antenna details and node position together with digital hardware and software. The validation on a real wearable system shows that the proposed simulation approach achieves a good trade-off between accuracy and speed thus allowing fast exploration of various configurations in the early phase of the design flow without recurring to the expensive and time-consuming creation of physical prototypes. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	6.3.3	A CIRCUIT-DESIGN-DRIVEN TOOL WITH A HYBRID AUTOMATION APPROACH FOR SAR ADCS IN IOT Speaker: Ming Ding, IMEC/Holst Centre, NL Authors: Ming Ding¹, Guibin Chen², Pieter Harpe³, Benjamin Busze¹, Yao-Hong Liu¹, Christian Bachmann¹, Kathleen Philips¹ and Arthur van Roermund³ ¹imec-Holst Centre, NL; ²imec-Holst Centre, Eindhoven University of Technology, NL; ³Eindhoven University of Technology, NL Abstract A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187uW and 16.7uW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
12:15	IP2-17, 902	AMS VERIFICATION METHODOLOGY REGARDING SUPPLY MODULATION IN RF SOCS INDUCED BY DIGITAL STANDARD CELLS Speaker: Fabian Speicher, RWTH Aachen University, DE Authors: Fabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich and Stefan Heinen, RWTH Aachen University, DE Abstract Nanoscale CMOS enables and forces the use of digital-centric RF architectures, where timing resolution is traded for analog resolution. Simultaneously, digital circuits act as aggressors endangering the performance of the time continuous digital and analog parts. The switching activities of logic cells result in power supply variations which lead to jitter in the digital signal paths and causes interferers coupling to the analog paths, appearing as e.g. phase noise, crosstalk, unwanted frequency conversion, etc. Since todays commonly used AMS simulation methods are limited to register-transfer level (RTL) models for the digital domain, the electrical behavior caused by digital switching is not considered. Here, a method for modeling logic cells with regard to power supply noise is presented using the available characterization data of a standard cell library. It covers the influence of switching on the supply voltage as well as influences of supply variations on the digital path delay and their feedthrough to blocks of the RF domain. A fast event-driven simulation of an entire AMS system regarding the mentioned aspects is enabled. The method is demonstrated on a digital-centric transmitter to detect the effects on system level. Download Paper (PDF; Only available from the DATE venue WiFi)
12:16	IP3-1, 611	TESTBENCH QUALIFICATION FOR SYSTEMC-AMS TIMED DATA FLOW MODELS Speaker: Muhammad Hassan, DFKI GmbH, DE Authors: Muhammad Hassan¹, Daniel Grosse², Hoang M. Le³, Thilo Voertler⁴, Karsten Einwich⁴ and Rolf Drechsler² ¹Cyber Physical Systems, DFKI, DE; ²University of Bremen/DFKI GmbH, DE; ³University of Bremen, DE; ⁴COSEDA Technologies GmbH, DE Abstract Analog-Mixed Signal (AMS) circuits have become increasingly important for today's SoCs. The Timed Data Flow (TDF) model of computation available in SystemC-AMS offers here a good tradeoff between accuracy and simulation-speed at the system-level. One of the main challenges in system-level verification is the quality of the testbench. In this paper, we present a testbench qualification approach for SystemC-AMS TDF models. Our contribution is twofold: First, we propose specific mutation models for the class of filters implemented as TDF models. This requires to analyze the Laplace transfer function of the filter design. Second, we present the mutation based qualification approach based on the proposed specific mutations as well as standard behavioral mutations. This allows to find serious quality issues in the testbench. Our experimental results for a real-world AMS system demonstrate the applicability and efficacy of our approach. Download Paper (PDF; Only available from the DATE venue WiFi)
12:17	IP3-2, 143	AN ALGEBRA FOR MODELING CONTINUOUS TIME SYSTEMS Speaker: José Medeiros, University of Brasilia, BR Authors: José E. G. de Medeiros¹, George Ungureanu² and Ingo Sander² ¹University of Brasília, BR; ²KTH Royal Institute of Technology, SE Abstract Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break in Großer Saal and Saal 1 Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 21, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 22, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00 Keynote Lecture in "Saal 2" 13:20 - 13:50 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

11:00

6.3.1

ENHANCED ANALOG AND RF IC SIZING METHODOLOGY USING PCA AND NSGA-II OPTIMIZATION KERNEL
Speaker:
Nuno Lourenco, Instituto de Telecomunicações, PT
Authors:
Tiago Pessoa, Nuno Lourenco, Ricardo Martins, Ricardo Povoa and Nuno Horta, Instituto de Telecomunicações /Instituto Superior Técnico – Universidade de Lisboa, PT
Abstract
State-of-the-art design of analog and radio frequency integrated circuits is often accomplished using sizing optimization. In this paper, an innovative combination of principal component analysis (PCA) and evolutionary computation is used to increase the optimizer's efficiency. The adopted NSGA-II optimization kernel is improved by applying the genetic operators of mutation and crossover on a transformed design-space, obtained from the latest set of solutions (the parents) using PCA. By applying crossover and mutation on variables that are projections of the principal components, the optimization moves more effectively, finding solutions with better performances, in the same amount of time, than the standard NSGA-II optimization kernel. The proposed method was validated in the optimization of two widely used analog circuits, an amplifier and a voltage controlled oscillator, reaching wider solutions sets, and in some cases, solutions sets that can be almost 3 times better in terms of hypervolume.
Download Paper (PDF; Only available from the DATE venue WiFi)

11:30

6.3.2

A SYSTEMC-BASED SIMULATOR FOR DESIGN SPACE EXPLORATION OF SMART WIRELESS SYSTEMS
Speaker:
Gabriele Miorandi, University of Verona, IT
Authors:
Gabriele Miorandi¹, Francesco Stefanni², Federico Fraccaroli³ and Davide Quaglia¹
¹University of Verona, IT; ²EDALab s.r.l., IT; ³Wagoo Italia s.r.l.s., IT
Abstract
Smart wireless techniques are at the core of many today's telecommunication and networked embedded systems where performance are enhanced by intertwining radio frequency (RF) and digital aspects. Therefore their design requires to focus on both domains. Traditional approaches for their simulation rely either on different domain-specific tools or on analog-mixed-signal modeling languages. In the former case, the simulation of the whole platform in the same session is not possible while in the latter case, simulation performance are limited by the computationally most intensive domain (usually RF). We present an extension of the SystemC Network Simulation Library that allows to simulate antenna details and node position together with digital hardware and software. The validation on a real wearable system shows that the proposed simulation approach achieves a good trade-off between accuracy and speed thus allowing fast exploration of various configurations in the early phase of the design flow without recurring to the expensive and time-consuming creation of physical prototypes.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:00

6.3.3

A CIRCUIT-DESIGN-DRIVEN TOOL WITH A HYBRID AUTOMATION APPROACH FOR SAR ADCS IN IOT
Speaker:
Ming Ding, IMEC/Holst Centre, NL
Authors:
Ming Ding¹, Guibin Chen², Pieter Harpe³, Benjamin Busze¹, Yao-Hong Liu¹, Christian Bachmann¹, Kathleen Philips¹ and Arthur van Roermund³
¹imec-Holst Centre, NL; ²imec-Holst Centre, Eindhoven University of Technology, NL; ³Eindhoven University of Technology, NL
Abstract
A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187uW and 16.7uW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:15

IP2-17, 902

AMS VERIFICATION METHODOLOGY REGARDING SUPPLY MODULATION IN RF SOCS INDUCED BY DIGITAL STANDARD CELLS
Speaker:
Fabian Speicher, RWTH Aachen University, DE
Authors:
Fabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich and Stefan Heinen, RWTH Aachen University, DE
Abstract
Nanoscale CMOS enables and forces the use of digital-centric RF architectures, where timing resolution is traded for analog resolution. Simultaneously, digital circuits act as aggressors endangering the performance of the time continuous digital and analog parts. The switching activities of logic cells result in power supply variations which lead to jitter in the digital signal paths and causes interferers coupling to the analog paths, appearing as e.g. phase noise, crosstalk, unwanted frequency conversion, etc. Since todays commonly used AMS simulation methods are limited to register-transfer level (RTL) models for the digital domain, the electrical behavior caused by digital switching is not considered. Here, a method for modeling logic cells with regard to power supply noise is presented using the available characterization data of a standard cell library. It covers the influence of switching on the supply voltage as well as influences of supply variations on the digital path delay and their feedthrough to blocks of the RF domain. A fast event-driven simulation of an entire AMS system regarding the mentioned aspects is enabled. The method is demonstrated on a digital-centric transmitter to detect the effects on system level.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:16

IP3-1, 611

TESTBENCH QUALIFICATION FOR SYSTEMC-AMS TIMED DATA FLOW MODELS
Speaker:
Muhammad Hassan, DFKI GmbH, DE
Authors:
Muhammad Hassan¹, Daniel Grosse², Hoang M. Le³, Thilo Voertler⁴, Karsten Einwich⁴ and Rolf Drechsler²
¹Cyber Physical Systems, DFKI, DE; ²University of Bremen/DFKI GmbH, DE; ³University of Bremen, DE; ⁴COSEDA Technologies GmbH, DE
Abstract
Analog-Mixed Signal (AMS) circuits have become increasingly important for today's SoCs. The Timed Data Flow (TDF) model of computation available in SystemC-AMS offers here a good tradeoff between accuracy and simulation-speed at the system-level. One of the main challenges in system-level verification is the quality of the testbench. In this paper, we present a testbench qualification approach for SystemC-AMS TDF models. Our contribution is twofold: First, we propose specific mutation models for the class of filters implemented as TDF models. This requires to analyze the Laplace transfer function of the filter design. Second, we present the mutation based qualification approach based on the proposed specific mutations as well as standard behavioral mutations. This allows to find serious quality issues in the testbench. Our experimental results for a real-world AMS system demonstrate the applicability and efficacy of our approach.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:17

IP3-2, 143

AN ALGEBRA FOR MODELING CONTINUOUS TIME SYSTEMS
Speaker:
José Medeiros, University of Brasilia, BR
Authors:
José E. G. de Medeiros¹, George Ungureanu² and Ingo Sander²
¹University of Brasília, BR; ²KTH Royal Institute of Technology, SE
Abstract
Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

End of session
Lunch Break in Großer Saal and Saal 1

Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD).

Lunch Breaks (Großer Saal + Saal 1)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 20, 2018