Date: Wednesday 21 March 2018
Time: 14:30 - 16:00
Location / Room: Saal 2

Chair:
Naveh Yehuda, IBM Research, IL

Quantum computing is emerging at a meteoric pace from a pure academic field to a fully industrial framework. Rapid advances are happening both in the physical realizations of quantum chips, and in their potential software applications. In contrast, we are not seeing that rapid growth in the design and verification methodologies for scaled-up quantum machines. In this session we describe the field of verification of quantum computers. We discuss the underlying concepts of this field, its theoretical and practical challenges, and state-of-the-art approaches to addressing those challenges. The goal of this session is to help facilitate early efforts to adapt and create verification methodologies for quantum computers and systems. Without such early efforts, a debilitating gap may form between the state-of-the-art of low level physical technologies for quantum computers, and our ability to build medium, large, and very large scale integrated quantum circuits (M/L/VLSIQ).

Time	Label	Presentation Title Authors
14:30	7.1.1	VERIFICATION OF QUANTUM COMPUTING Speaker: Petros Wallden, School of Informatics, University of Edinburgh, GB Author: Elham Kashefi, School of Informatics, University of Edinburgh, UK & CNRS LIP6, GB Abstract Quantum computers promise to efficiently solve not only problems believed to be intractable for classical computers, but also problems for which verifying the solution is also considered intractable. This raises the question of how one can check whether quantum computers are indeed producing correct results. This task, known as quantum verification, has been highlighted as a significant challenge on the road to scalable quantum computing technology. We review the most significant approaches to quantum verification and compare them in terms of structure, complexity and required resources. We also comment on the use of cryptographic techniques which, for many of the presented protocols, has proven extremely useful in performing verification. Finally, we discuss issues related to fault tolerance, experimental implementations and the outlook for future protocols.
14:50	7.1.2	GAINING INSIGHT INTO NEAR-TERM QUANTUM DEVICES WITH TAILOR-MADE APPLICATIONS Author: James R. Wootton, University of Basel, CH Abstract Many interesting algorithms have been designed for large scale fault-tolerant quantum computers. However, most will not be suitable for the smaller and noisier devices of the next decade. To understand how these devices function, we must therefore use applications specifically designed for their capabilities. In this talk we briefly introduce two possibilities. One is quantum error correction, which allows us to directly analyze imperfections in a device, as well as determine how well we can control them. The other is games, which can provide general insights into the capabilities of a device in a widely relatable manner.
15:15	7.1.3	THE ENGINEERING CHALLENGES IN QUANTUM COMPUTING Author: Koen Bertels, Delft University of Technology, NL Abstract In this presentation we will present the ongoing work that focuses on defining and building a micro-architecture for a quantum computer. We will present the essence of quantum computing, the challenges as well as our current long term (>5 years) and short term (<5 years) in this respect and we will discuss the system vision as well as the Transmon and Spinqubit processor prototypes that we have developed with the colleagues L. DiCarmo and L. Vandersypen at QuTech.
15:40	7.1.4	QUANTUM VERIFICATION: WHAT CAN WE ADOPT AND LEARN FROM CLASSICAL VERIFICATION Author: Yehuda Naveh, IBM Research - Haifa, IL Abstract I will provide a view of the challenges of verifying quantum computers through the lenses of classical verification methodologies. I will argue that while the fields are inherently different (e.g., quantum verification is a challenge already at the 50-qubit chip levels, while classical verification challenges stem mostly from complex micro-architectural structures present only at multi-million transistor chips), many methods of classical verification may still be adapted to the quantum regime. These include abstracted simulation and modeling languages, directed constraint-based random benchmarking, coverage measures, and more. My hope is that learning from the long history of classical verification will make the process of reaching robust, efficient, and stable verification methodologies for quantum computers much faster and less painful than has been for the classical case.
16:00		End of session Coffee Break in Exhibition Area Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 21, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 22, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00 Keynote Lecture in "Saal 2" 13:20 - 13:50 Coffee Break 15:30 - 16:00