Date: Wednesday 21 March 2018
Time: 11:00 - 12:30
Location / Room: Exhibition Theatre
Organiser:
Hans-Jürgen Brand, IDT/ZMDI, DE
The workshop on Innovative Products for Autonomous Driving includes 2 sessions (part 1:session 3.8). This session will highlight how to do ultra-low-voltage design, how to accelerate physical signoff and a 22 nm FDSOI System-on-Chip development for Advanced Driver Assistance System.
Time | Label | Presentation Title Authors |
---|---|---|
11:00 | 6.8.1 | 22FDX ULTRA-LOW-VOLTAGE DESIGN BASED ON ADAPTIVE BODY BIAS Speaker: Holger Eisenreich, Racyics GmbH, DE Abstract 22FDX body bias allows to compensate process, temperature and slow voltage variations. Applied in Adaptive Body Bias (ABB) scheme, this technology feature enables Ultra-Low-Voltage implementations down to 0.4V for IoT-like designs with unparalleled energy efficiency. Racyics will present its 22FDX ABB IP platform and the related ABB-aware implementation and sign-off methodology. |
11:30 | 6.8.2 | A NEW ADAS CHIP DESIGN IN 22 NM FDSOI TECHNOLOGY FOR AUTOMOTIVE COMPUTER VISION APPLICATIONS Speaker: Jens Benndorf, Dream Chip Technologies, DE Abstract The presentation explores the European collaboration on a 22 nm FDSOI System-on-Chip development for Advanced Driver Assistance System. |
12:00 | 6.8.3 | ACCELERATING PHYSICAL SIGNOFF FOR LEADING EDGE CHIP DESIGNS Speaker: David DeMarcos, Synopsys, DE Abstract Physical Verification with IC Validator in the Synopsys Design Platform provides technology-leading, production-proven signoff solutions for design rule checking (DRC), connectivity verification layout-vs.-schematic (LVS), metal fill insertion, and design-for-manufacturability (DFM) enhancements. IC Validator is supported by all major foundries as a signoff solution for established-node designs, as well as advanced emerging-node designs at 20nm and below. It includes productivity links to leading design tools such as IC Compiler™/IC Compiler II physical implementation, StarRC™ parasitic extraction, and Custom Compiler™ mixed-signal design. IC Validator's In-Design physical verification speeds up design closure with timing-aware metal fill and DRC fixing within the IC Compiler and IC Compiler II environments. |
12:30 | End of session Lunch Break in Großer Saal and Saal 1
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018
Wednesday, March 21, 2018
Thursday, March 22, 2018
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