6.8 Innovative Products for Autonomous Driving (part 2)

22FDX body bias allows to compensate process, temperature and slow voltage variations. Applied in Adaptive Body Bias (ABB) scheme, this technology feature enables Ultra-Low-Voltage implementations down to 0.4V for IoT-like designs with unparalleled energy efficiency. Racyics will present its 22FDX ABB IP platform and the related ABB-aware implementation and sign-off methodology.

The presentation explores the European collaboration on a 22 nm FDSOI System-on-Chip development for Advanced Driver Assistance System.
It will highlight partner co-operation and key trade-offs necessary to deliver the target performance. The scope includes:
• Short company introduction
• Project setup and target applications
• Chip architecture and performance requirements
• Hardware Demonstration System
• Outlook
• Summary

Physical Verification with IC Validator in the Synopsys Design Platform provides technology-leading, production-proven signoff solutions for design rule checking (DRC), connectivity verification layout-vs.-schematic (LVS), metal fill insertion, and design-for-manufacturability (DFM) enhancements. IC Validator is supported by all major foundries as a signoff solution for established-node designs, as well as advanced emerging-node designs at 20nm and below. It includes productivity links to leading design tools such as IC Compiler™/IC Compiler II physical implementation, StarRC™  parasitic extraction, and Custom Compiler™  mixed-signal design. IC Validator's In-Design physical verification speeds up design closure with timing-aware metal fill and DRC fixing within the IC Compiler and IC Compiler II environments.