5.5 Emerging Technologies for Future Computing

Time	Label	Presentation Title Authors
08:30	5.5.1	(Best Paper Award Candidate) COMPACT MODELING OF CARBON NANOTUBE THIN FILM TRANSISTORS FOR FLEXIBLE CIRCUIT DESIGN Speaker: Leilai Shao, University of California, Santa Barbara, US Authors: Leilai Shao¹, Tsung-Ching Huang², Ting Lei³, Zhenan Bao³, Raymond Beausoleil⁴ and Tim Cheng⁵ ¹University of California Santa Barbara, US; ²Hewlett Packard Labs, US; ³Stanford University, US; ⁴HPE Labs, US; ⁵HKUST, HK Abstract Carbon nanotube thin film transistor (CNT-TFT) is a promising candidate for flexible electronics, because of its high carrier mobility and great mechanical flexibility. An accurate and trustworthy device model for CNT-TFTs, however, is still missing. In this paper, we present a SPICE-compatible compact model for CNT-TFT circuit simulation and validate the proposed model based on fabricated CNT-TFTs and Pseudo-CMOS circuits. The proposed CNT-TFT model enables circuit designers to explore design space by adjusting device parameters, supply voltages and transistor sizes to optimize the noise margin (NM) and power-delay product (PDP), which are the key merits for larger scale CNT-TFT circuits. We further propose a design framework to effectively optimize the NM and PDP to facilitate greater automation of flexible circuit design based on CNT-TFTs. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	5.5.2	A HIGH-SPEED DESIGN METHODOLOGY FOR INDUCTIVE COUPLING LINKS IN 3D-ICS Speaker: Benjamin Fletcher, University of Southampton, GB Authors: Benjamin Fletcher¹, Shidhartha Das² and Terrence Mak¹ ¹University of Southampton, GB; ²ARM Ltd., GB Abstract Inductive coupling links (ICLs) are gaining traction as an alternative to through silicon vias (TSVs) for 3D integration, promising high-bandwidth connectivity without the inflated fabrication costs associated with TSV-enabled processes. For power-efficient ICL design, optimisation of the utilized physical inductor geometries is essential, however typically necessitates the use of finite element analysis (FEA) in addition to manual parameter fitting, a process that can take several hours even for a single geometry. As a result, the generation of optimised inductor designs poses a significant challenge. In this paper, we address this challenge, presenting a CAD-tool for Optimisation of Inductive coupling Links for 3D-ICs (COIL-3D). COIL-3D uses a rapid solver based upon semi-empirical expressions to quickly and accurately characterise a given link, in conjunction with a high-speed refined optimisation flow to find optimal inductor geometries for use in ICL-based 3D-ICs. The proposed solver achieves an average accuracy within 9.1% of commercial FEA software tools, and the proposed optimisation flow reduces the search time by 26 orders of magnitude. This work unlocks new potential for power-efficient 3D integration using inductive coupling links. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	5.5.3	AN EXACT METHOD FOR DESIGN EXPLORATION OF QUANTUM-DOT CELLULAR AUTOMATA Speaker: Marcel Walter, University of Bremen, DE Authors: Marcel Walter¹, Robert Wille², Daniel Grosse³, Frank Sill Torres⁴ and Rolf Drechsler³ ¹University of Bremen, DE; ²Johannes Kepler University Linz, AT; ³University of Bremen/DFKI GmbH, DE; ⁴Federal University of Minas Gerais, BR Abstract Quantum-dot Cellular Automata (QCA) are an emerging computation technology in which basic states are represented by nanosize particles and logic operations are conducted through corresponding effects such as Coulomb interaction. This allows to overcome physical boundaries of conventional solutions such as CMOS and, hence, constitutes a promising direction for future computing devices. Despite these promises, however, the development of (automatic) design methods for QCAs is still in its infancy. In fact, QCA circuits are mainly designed manually thus far and only few heuristics are available. This frequently leads to unsatisfactory results and generally makes it hard to evaluate the quality of respective QCA designs. In this work, we propose an exact solution for the design of QCA circuits that can be configured e. g. to generate circuits that satisfy certain design objectives and/or physical constraints. For the first time, this allows for design exploration of QCA circuits. Experimental evaluations and case studies demonstrate the benefit of the proposed solution. Download Paper (PDF; Only available from the DATE venue WiFi)
09:45	5.5.4	ACCURATE MARGIN CALCULATION FOR SINGLE FLUX QUANTUM LOGIC CELLS Speaker: Massoud Pedram, University of Southern California, US Authors: Soheil Nazar Shahsavani, Bo Zhang and Massoud Pedram, University of Southern California, US Abstract This paper presents a novel method for accurate margin calculation of single flux quantum (SFQ) logic cells in a superconducting electronic circuit. The proposed method can be utilized as a figure of merit to estimate the robustness of a logic cell without the need for expensive Monte-Carlo simulations. This is achieved through efficient state-space exploration of all parameters in the cell structure. Using proposed approach, distinct parameter dispersion (DPD) based yield of SFQ cells increases by 55% on average, compared with state-of-the-art techniques. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00	IP2-8, 858	IMPROVED SYNTHESIS OF CLIFFORD+T QUANTUM FUNCTIONALITY Speaker: Philipp Niemann, German Research Center for Articial Intelligence (DFKI GmbH), DE Authors: Philipp Niemann¹, Robert Wille² and Rolf Drechsler³ ¹Cyber-Physical Systems, DFKI GmbH, DE; ²Johannes Kepler University Linz, AT; ³University of Bremen/DFKI GmbH, DE Abstract The Clifford+T library provides robust and fault-tolerant realizations for quantum computations. Consequently, (logic) synthesis of Clifford+T quantum circuits became an important research problem. However, previously proposed solutions are either only applicable to very small quantum systems or lead to circuits that are far from being optimal—mainly caused by a local, i.e. column-wise, consideration of the underlying transformation matrix to be synthesized. In this paper, we suggest an improved approach that considers the matrix globally and, by this, overcomes many of these drawbacks. Preliminary evaluations show the promises of this direction. Download Paper (PDF; Only available from the DATE venue WiFi)
10:01	IP2-9, 462	ENERGY-EFFICIENT CHANNEL ALIGNMENT OF DWDM SILICON PHOTONIC TRANSCEIVERS Speaker: Yuyang Wang, University of California, Santa Barbara, US Authors: Yuyang Wang¹, M. Ashkan Seyedi², Rui Wu¹, Jared Hulme², Marco Fiorentino², Raymond G. Beausoleil² and Kwang-Ting Cheng³ ¹University of California, Santa Barbara, US; ²Hewlett Packard Labs, US; ³Hong Kong University of Science and Technology, HK Abstract The comb laser-driven microring-based dense wavelength division multiplexing silicon photonics is a promising candidate for next-generation optical interconnects. However, existing solutions for exploring the power-performance trade-off of such systems have been restricted to a limited design space, resulting from the unnecessary constraints of using an identical spacing for laser comb lines and microring channels, and of utilizing consecutive laser comb lines for data transmission. We propose an energy-efficient channel alignment scheme that aligns the microring channels to a subset of laser comb lines that are non-uniformly distributed in the free spectrum range of the microrings. Based on a well-established process variation model, our simulations show that the proposed scheme significantly reduces the microring tuning power in the presence of denser comb lines. The power saved from microring tuning can improve the overall system energy efficiency despite some power wasted in unused laser comb lines. We further conducted a case study for design space exploration using the proposed channel alignment scheme, seeking the most energy-efficient configuration in order to achieve a target aggregated data rate. Download Paper (PDF; Only available from the DATE venue WiFi)
10:02	IP2-10, 267	A PHYSICAL SYNTHESIS FLOW FOR EARLY TECHNOLOGY EVALUATION OF SILICON NANOWIRE BASED RECONFIGURABLE FETS Speaker: Shubham Rai, Chair For Processor Design, CFAED, Technische Universität Dresden, Dresden, DE Authors: Shubham Rai¹, Ansh Rupani², Dennis Walter¹, Michael Raitza¹, André Heinzig³, Christian Mayr¹, Walter Weber⁴ and Akash Kumar¹ ¹Technische Universität Dresden, DE; ²Birla Institute of Technology and Science Pilani, Hyderabad Campus, IN; ³NaMLab GmbH, DE; ⁴NaMLab gGmbH and CfAED, DE Abstract Silicon Nanowire based reconfigurable transistors (RFETs) provide an additional gate terminal called the program gate which gives the freedom of programming p-type or n-type functionality for the same device at runtime. This enables the circuit designers to pack more functionality per computational unit. This saves processing costs as only one device type is required. No doping and associated lithography steps are needed for this technology. In this paper, we present a complete design flow including both logic and physical synthesis for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (library extension format) files for the physical synthesis flow and make these available under an open source license to enable further research in the domain of these novel, functionally enhanced transistors. We develop a table model based on a transistor cell with relaxed dimensions following an SOI-based 22 nm technology having a gate pitch of 110 nm and modeled our logic gates on dual gate RFETs. For the sake of comparison, we use the same tool flow for CMOS. We show that in the first of its kind comparison, for these fully symmetrical reconfigurable transistors, the area after placement and routing for SiNW based circuits is 17% more than that of CMOS for MCNC benchmark. Further, we discuss areas of improvement for obtaining better area results from the silicon nanowire based RFETs from a fabrication and technology point of view. The future use of self-aligned techniques to structure two independent gates within a smaller pitch holds the promise of substantial area reduction. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session Coffee Break in Exhibition Area Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 21, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 22, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00 Keynote Lecture in "Saal 2" 13:20 - 13:50 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

08:30

5.5.1

(Best Paper Award Candidate)
COMPACT MODELING OF CARBON NANOTUBE THIN FILM TRANSISTORS FOR FLEXIBLE CIRCUIT DESIGN
Speaker:
Leilai Shao, University of California, Santa Barbara, US
Authors:
Leilai Shao¹, Tsung-Ching Huang², Ting Lei³, Zhenan Bao³, Raymond Beausoleil⁴ and Tim Cheng⁵
¹University of California Santa Barbara, US; ²Hewlett Packard Labs, US; ³Stanford University, US; ⁴HPE Labs, US; ⁵HKUST, HK
Abstract
Carbon nanotube thin film transistor (CNT-TFT) is a promising candidate for flexible electronics, because of its high carrier mobility and great mechanical flexibility. An accurate and trustworthy device model for CNT-TFTs, however, is still missing. In this paper, we present a SPICE-compatible compact model for CNT-TFT circuit simulation and validate the proposed model based on fabricated CNT-TFTs and Pseudo-CMOS circuits. The proposed CNT-TFT model enables circuit designers to explore design space by adjusting device parameters, supply voltages and transistor sizes to optimize the noise margin (NM) and power-delay product (PDP), which are the key merits for larger scale CNT-TFT circuits. We further propose a design framework to effectively optimize the NM and PDP to facilitate greater automation of flexible circuit design based on CNT-TFTs.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:00

5.5.2

A HIGH-SPEED DESIGN METHODOLOGY FOR INDUCTIVE COUPLING LINKS IN 3D-ICS
Speaker:
Benjamin Fletcher, University of Southampton, GB
Authors:
Benjamin Fletcher¹, Shidhartha Das² and Terrence Mak¹
¹University of Southampton, GB; ²ARM Ltd., GB
Abstract
Inductive coupling links (ICLs) are gaining traction as an alternative to through silicon vias (TSVs) for 3D integration, promising high-bandwidth connectivity without the inflated fabrication costs associated with TSV-enabled processes. For power-efficient ICL design, optimisation of the utilized physical inductor geometries is essential, however typically necessitates the use of finite element analysis (FEA) in addition to manual parameter fitting, a process that can take several hours even for a single geometry. As a result, the generation of optimised inductor designs poses a significant challenge. In this paper, we address this challenge, presenting a CAD-tool for Optimisation of Inductive coupling Links for 3D-ICs (COIL-3D). COIL-3D uses a rapid solver based upon semi-empirical expressions to quickly and accurately characterise a given link, in conjunction with a high-speed refined optimisation flow to find optimal inductor geometries for use in ICL-based 3D-ICs. The proposed solver achieves an average accuracy within 9.1% of commercial FEA software tools, and the proposed optimisation flow reduces the search time by 26 orders of magnitude. This work unlocks new potential for power-efficient 3D integration using inductive coupling links.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:30

5.5.3

AN EXACT METHOD FOR DESIGN EXPLORATION OF QUANTUM-DOT CELLULAR AUTOMATA
Speaker:
Marcel Walter, University of Bremen, DE
Authors:
Marcel Walter¹, Robert Wille², Daniel Grosse³, Frank Sill Torres⁴ and Rolf Drechsler³
¹University of Bremen, DE; ²Johannes Kepler University Linz, AT; ³University of Bremen/DFKI GmbH, DE; ⁴Federal University of Minas Gerais, BR
Abstract
Quantum-dot Cellular Automata (QCA) are an emerging computation technology in which basic states are represented by nanosize particles and logic operations are conducted through corresponding effects such as Coulomb interaction. This allows to overcome physical boundaries of conventional solutions such as CMOS and, hence, constitutes a promising direction for future computing devices. Despite these promises, however, the development of (automatic) design methods for QCAs is still in its infancy. In fact, QCA circuits are mainly designed manually thus far and only few heuristics are available. This frequently leads to unsatisfactory results and generally makes it hard to evaluate the quality of respective QCA designs. In this work, we propose an exact solution for the design of QCA circuits that can be configured e. g. to generate circuits that satisfy certain design objectives and/or physical constraints. For the first time, this allows for design exploration of QCA circuits. Experimental evaluations and case studies demonstrate the benefit of the proposed solution.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:45

5.5.4

ACCURATE MARGIN CALCULATION FOR SINGLE FLUX QUANTUM LOGIC CELLS
Speaker:
Massoud Pedram, University of Southern California, US
Authors:
Soheil Nazar Shahsavani, Bo Zhang and Massoud Pedram, University of Southern California, US
Abstract
This paper presents a novel method for accurate margin calculation of single flux quantum (SFQ) logic cells in a superconducting electronic circuit. The proposed method can be utilized as a figure of merit to estimate the robustness of a logic cell without the need for expensive Monte-Carlo simulations. This is achieved through efficient state-space exploration of all parameters in the cell structure. Using proposed approach, distinct parameter dispersion (DPD) based yield of SFQ cells increases by 55% on average, compared with state-of-the-art techniques.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

IP2-8, 858

IMPROVED SYNTHESIS OF CLIFFORD+T QUANTUM FUNCTIONALITY
Speaker:
Philipp Niemann, German Research Center for Articial Intelligence (DFKI GmbH), DE
Authors:
Philipp Niemann¹, Robert Wille² and Rolf Drechsler³
¹Cyber-Physical Systems, DFKI GmbH, DE; ²Johannes Kepler University Linz, AT; ³University of Bremen/DFKI GmbH, DE
Abstract
The Clifford+T library provides robust and fault-tolerant realizations for quantum computations. Consequently, (logic) synthesis of Clifford+T quantum circuits became an important research problem. However, previously proposed solutions are either only applicable to very small quantum systems or lead to circuits that are far from being optimal—mainly caused by a local, i.e. column-wise, consideration of the underlying transformation matrix to be synthesized. In this paper, we suggest an improved approach that considers the matrix globally and, by this, overcomes many of these drawbacks. Preliminary evaluations show the promises of this direction.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:01

IP2-9, 462

ENERGY-EFFICIENT CHANNEL ALIGNMENT OF DWDM SILICON PHOTONIC TRANSCEIVERS
Speaker:
Yuyang Wang, University of California, Santa Barbara, US
Authors:
Yuyang Wang¹, M. Ashkan Seyedi², Rui Wu¹, Jared Hulme², Marco Fiorentino², Raymond G. Beausoleil² and Kwang-Ting Cheng³
¹University of California, Santa Barbara, US; ²Hewlett Packard Labs, US; ³Hong Kong University of Science and Technology, HK
Abstract
The comb laser-driven microring-based dense wavelength division multiplexing silicon photonics is a promising candidate for next-generation optical interconnects. However, existing solutions for exploring the power-performance trade-off of such systems have been restricted to a limited design space, resulting from the unnecessary constraints of using an identical spacing for laser comb lines and microring channels, and of utilizing consecutive laser comb lines for data transmission. We propose an energy-efficient channel alignment scheme that aligns the microring channels to a subset of laser comb lines that are non-uniformly distributed in the free spectrum range of the microrings. Based on a well-established process variation model, our simulations show that the proposed scheme significantly reduces the microring tuning power in the presence of denser comb lines. The power saved from microring tuning can improve the overall system energy efficiency despite some power wasted in unused laser comb lines. We further conducted a case study for design space exploration using the proposed channel alignment scheme, seeking the most energy-efficient configuration in order to achieve a target aggregated data rate.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:02

IP2-10, 267

A PHYSICAL SYNTHESIS FLOW FOR EARLY TECHNOLOGY EVALUATION OF SILICON NANOWIRE BASED RECONFIGURABLE FETS
Speaker:
Shubham Rai, Chair For Processor Design, CFAED, Technische Universität Dresden, Dresden, DE
Authors:
Shubham Rai¹, Ansh Rupani², Dennis Walter¹, Michael Raitza¹, André Heinzig³, Christian Mayr¹, Walter Weber⁴ and Akash Kumar¹
¹Technische Universität Dresden, DE; ²Birla Institute of Technology and Science Pilani, Hyderabad Campus, IN; ³NaMLab GmbH, DE; ⁴NaMLab gGmbH and CfAED, DE
Abstract
Silicon Nanowire based reconfigurable transistors (RFETs) provide an additional gate terminal called the program gate which gives the freedom of programming p-type or n-type functionality for the same device at runtime. This enables the circuit designers to pack more functionality per computational unit. This saves processing costs as only one device type is required. No doping and associated lithography steps are needed for this technology. In this paper, we present a complete design flow including both logic and physical synthesis for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (library extension format) files for the physical synthesis flow and make these available under an open source license to enable further research in the domain of these novel, functionally enhanced transistors. We develop a table model based on a transistor cell with relaxed dimensions following an SOI-based 22 nm technology having a gate pitch of 110 nm and modeled our logic gates on dual gate RFETs. For the sake of comparison, we use the same tool flow for CMOS. We show that in the first of its kind comparison, for these fully symmetrical reconfigurable transistors, the area after placement and routing for SiNW based circuits is 17% more than that of CMOS for MCNC benchmark. Further, we discuss areas of improvement for obtaining better area results from the silicon nanowire based RFETs from a fabrication and technology point of view. The future use of self-aligned techniques to structure two independent gates within a smaller pitch holds the promise of substantial area reduction.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

End of session
Coffee Break in Exhibition Area

Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD).

Lunch Breaks (Großer Saal + Saal 1)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 20, 2018