W05 Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2018)
Agenda
| Time | Label | Session |
|---|---|---|
| 08:30 | W05.1 | Session 1: Physical attacks |
| 08:30 | W05.1.1 | Keynote 1 |
| 09:30 | W05.1.2 | Automatic Application of Side Channel Countermeasures: History and Perspectives Francesco Regazzoni, AlaRI, CH |
| 10:00 | W05.2 | Poster Session 1 + Coffee Break |
| 10:00 | W05.2.1 | Dummy rounds side-channel attack protection of round-based encryption algorithms Stanislav Jerabek, Jan Schmidt and Martin Novotny, CTU, CZ |
| 10:00 | W05.2.2 | A New Metric for the Side-Channel Vulnerability Evaluation? Jan Bělohoubek, Petr Fiser and Jan Schmidt, CTU, CZ |
| 10:00 | W05.2.3 | Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of AES implemented in FPGA Vojtěch Miškovský, Hana Kubatova and Martin Novotny, CTU, CZ |
| 10:30 | W05.3 | Session 2: Active attacks and systems integrity |
| 10:30 | W05.3.1 | A Hybrid Approach for Ensuring the Security of Hardware Control Systems Naceur Maha, Ulrich Kuehne and Jean-Luc Danger, Télécom ParisTech, FR |
| 11:00 | W05.3.2 | On Security Metrics for Evaluating Fault-injection Countermeasures Maël Gay1, Batya Karp2, Osnat Keren2 and Ilia Polian3 1University of Passau, DE; 2Bar Ilan University, IL; 3University of Stuttgart, DE |
| 11:30 | W05.3.3 | SCA & Glitch Rogue: An Accurate Side Channel Analysis and Glitch Attack Evaluation Platform for Embedded Systems Athanasios Papadimitriou and David Hely, Univ. Grenoble Alpes, FR |
| 11:45 | W05.3.4 | Nonlinear Codes for Control Flow Checking Giorgio Di Natale1 and Osnat Keren2 1LIRMM, FR; 2Bar Ilan University, IL |
| 12:00 | W05.4 | Lunch Break |
| 13:00 | W05.5 | Session 3: Design and test of secure hardware |
| 13:00 | W05.5.1 | Keynote 2 |
| 14:00 | W05.5.2 | Does stream cipher-based scan chains encryption really prevent scan attacks? Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale and Bruno Rouzeyre, LIRMM, FR |
| 14:30 | W05.6 | Poster Session 2 + Coffee Break |
| 14:30 | W05.6.1 | Dynamic reconfiguration used for side channel attacks protection of various encryption algorithms Jan Brejnik, Stanislav Jerabek and Martin Novotny, CTU, CZ |
| 14:30 | W05.6.2 | Xilinx 7-Series FPGA Based Evaluation Platform for Physically Unclonable Function Matej Bartik, CTU, CZ |
| 14:30 | W05.6.3 | Design and Implementation of a Security Processor for Satellite Communication Systems Stavroula Zouzoula1, Nicolas Sklavos2 and Apostolos Fournaris1 1University of Patras, GR; 2University of Patra, GR |
| 15:00 | W05.7 | Session 4: Hardware circuit security |
| 15:00 | W05.7.1 | Using Convolutional Codes for Key Extraction in SRAM Physical Unclonable Functions Sven Mueelich, Sven Puchinger and Martin Bossert, Ulm University, DE |
| 15:30 | W05.7.2 | Towards Inter-Vendor Compatibility of TRNGs for FPGAs Milos Grujic1, Bohan Yang1, Vladimir Rožić1 and Ingrid Verbauwhede2 1KU Leuven, BE; 2KU Leuven and UCLA, BE |
| 16:00 | W05.7.3 | Two Methods of the Clock Jitter Measurement Aimed at Embedded TRNG testing Oto Petura1, Marek Laban2, Elie Noumon Allini3 and Viktor Fischer4 1Hubert Curien Laboratory, Jean Monnet University, FR; 2Technical University of Kosice, SK; 3Jean Monnet University Saint-Etienne, FR; 4Laboratoire Hubert Curien, FR |
| 16:15 | W05.7.4 | Random Bit Generation Based on The Association of Serial CBRAM Devices Daniel Arumi, Salvador Manich and Rosa Rodriguez, UPC, ES |
| 16:30 | W05.7.5 | Hardware Trojan Detection and Obfuscation based on Approximate Circuits Honorio Martin1, Giorgio Di Natale2, Sophie Dupuis2 and Luis Entrena1 1University Carlos III de Madrid, ES; 2LIRMM, FR |
| 16:45 | W05.7.6 | Using different LUT paths to increase area efficiency of RO-PUFs on Altera FPGAs Linus Feiten, Karsten Scheibler, Bernd Becker and Matthias Sauer, University of Freiburg, DE |
DATE Smartphone App
available at
Visit us at DATE 2018
