W02 Emerging Memory Solutions & Applications - Technology, Manufacturing, Architectures, Design, Automation and Test
Agenda
| Time | Label | Session |
|---|---|---|
| 08:40 | W02.1 | Opening Chair: |
| 08:40 | W02.1.1 | Welcome Address Christian Weis, University of Kaiserslautern, DE |
| 08:45 | W02.2 | Keynote Chair: |
| 08:45 | W02.2.1 | "Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation" Onur Mutlu, ETHZ, CH Abstract: Today's systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scalability and energy bottlenecks. Conventional memory technology is facing many scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of slightly higher cost. The emergence of 3D-stacked memory plus logic as well as the adoption of error correcting codes inside the latest DRAM chips are an evidence of this trend. In this talk, I will discuss some recent research that aims to practically enable computation close to data. After motivating trends in applications as well as technology, we will discuss at least two promising directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of DRAM, with low-cost changes, 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications. In both approaches, we will discuss relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, and programming models. Our focus will be the development of in-memory processing designs that can be adopted in real computing platforms at low cost. |
| 09:30 | W02.3 | Invited Talk about Emerging Neuromorphic Applications Chair: |
| 09:30 | W02.3.1 | SpiNNaker2: Energy Efficient Neuromorphic Computing in 22nm FDSOI CMOS Sebastian Höppner, Technische Universität Dresden, DE |
| 10:00 | W02.4 | Coffee Break and Poster Session Chair: |
| 10:30 | W02.5 | Industry Talk Chair: |
| 10:30 | W02.5.1 | Applications of phase-change memory in non-von Neumann computing Manuel Le Gallo, IBM, CH |
| 11:00 | W02.6 | Panel about "Deep Learning: what is the best Memory to choose?" Moderator: Panelists: The bridge between technology and applications is challenging. But that is exactly what this topic is about.
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| Panelists: | ||
| 12:00 | W02.7 | Lunch Break |
| 13:00 | W02.8 | Keynote Chair: |
| 13:00 | W02.8.1 | "Memory-Centric Architectures for Artificial Intelligence" Paul Franzon, NC State University, US Abstract: There is much current interest in building custom accelerators for machine learning and machine intelligence algorithms. However, at their root, many of these algorithms are very memory intensive in both capacity and bandwidth needs. Thus there is a need for memory-processor codesign to obtain the most of these algorithms. This talk presents multiple options to achieve high performance. A 3DIC logic on memory stack has been designed to support the compute needs for multiple parallel inference engines running deep networks simultaneously, for example as would be needed for autonomous vehicles. The DRAM is adopted from the Tezzaron DiRAM4 but supports over 130 Tbps of memory bandwidth with potential for 64 GB of capacity. A Processor In Memory architecture with Application Specific Instruction features has been designed to support Sparse Hierarchical Temporal algorithms that permit in-situ learning. These achieve an improvement in performance over a GPU implementation of over 20x and a power efficiency improvement of over 500x. Currently we are designing 2.5D versions of these accelerators as well as accelerators for quantized deep learning and Long Short Term Memory (LSTM) algorithms. Preliminary results from this activity will be presented. |
| 13:30 | W02.9 | Special Session I on "In-Memory Computing" Chair: |
| 13:30 | W02.9.1 | Memristive Memory Processing Unit (mMPU) for Real Processing in Memory Nishil Talati, TECHNION, IL |
| 13:50 | W02.9.2 | The Processing In Memory Revolution Fabrice Devaux, UPMEM SAS, FR |
| 14:10 | W02.9.3 | Conceptual design of a RISC-V compatible processor core using ternary arithmetic unit with memristive MLC storage Dietmar Fey, FAU, DE |
| 14:30 | W02.10 | Coffee Break and Poster Session Chair: |
| 15:00 | W02.11 | Special Session II on "Emerging RRAMs and Alternatives" Chair: |
| 15:00 | W02.11.1 | Challenges for Memristive Circuit Design Anne Siemon, RWTH, DE |
| 15:20 | W02.11.2 | Reliability Modeling Framework for Emerging STT-MRAM Rajendra Bishnoi, Karlsruhe Institiute of Technology, DE |
| 15:40 | W02.11.3 | Compact modeling of resistive switching memories Marc Bocquet, IM2NP, FR |
| 16:00 | W02.12 | Open Call Paper Session Chair: |
| 16:00 | W02.12.1 | Quantifying the Performance Overhead of NVML William Wang, ARM, GB |
| 16:15 | W02.12.2 | RRAM-based Automata Processor Jintao Yu, Delft University of Technology, NL |
| 16:27 | W02.12.3 | Energy Efficient DRAM Cache with Unconventional Row Buffer Size Nyunyi M. Tshibangu, NCSU, US |
| 16:39 | W02.12.4 | A 3-D Priority Address Encoder for 3-D Content Addressable Memories Jin-Fu Li, NCU, TW |
| 16:51 | W02.12.5 | Asynchronous Ultra Wide Voltage Range Two-Port SRAM Circuit for Fast Wake-up IoT Platform Réda Boumchedda, STMicroelectronics, FR |
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