Speaker:
Montserrat Nafria, Universitat Autonoma de Barcelona, ES

Abstract:
Time Dependent Variability (TDV) in scaled CMOS technologies provokes uncertainty in the electrical characteristics of transistors, which will be transferred to the circuit performance. In the Design-for-Reliability context, understanding the phenomenology behind TDV is fundamental to explore new techniques for the design of reliable circuits. Several mechanisms are the main responsible of TDV in current and future CMOS technologies. In this tutorial, the physical origin and the characterization challenges of the main mechanisms (Random Telegraph Noise, Bias Temperature Instabilities and Channel Hot Carriers Injection) will be presented. The latest advances in the device TDV physics-based compact modeling will be also addressed.

Speaker:
Hussam Amrouch, Karlsruhe Institute of Technology, DE

Abstract:
Due to aging, circuit reliability has become extraordinary challenging. Reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this presentation, first we will demonstrate how we can bring aging awareness to existing EDA tool flows based on so-called degradation-aware cell libraries. These libraries include detailed delay information of gates/cells under the impact that aging has on the key parameters of MOSFET transistors. We will also demonstrate that degradation-aware libraries and tool flows are indispensable for not only accurately estimating guardbands, but also efficiently containing them. Then, we will explain how to our degradation-aware cell libraries can be employed within the standard tool flows to quantify the impact of aging at the system level in the context of image processing. This goes far beyond investigating aging with respect to circuits' path delays solely as often done in state of the art. Afterwards, we will demonstrate how nondeterministic aging-induced timing errors can be converted into deterministic and controlled approximations instead. This enables designers for the first time to narrow or even remove guardbands through exploring application of approximate computing principles in the context of aging. Finally, we will demonstrate how the existing view of aging in the state of the art needs to updated. In fact, aging has been, traditionally, assumed to be a long-term reliability degradation in which its effects are observed in the order of months and years. However, in the deep nano technology, aging has shifted from a sole long-term to a short- and long-term reliability challenge. We will explain why circuits designers need to take that into account when employing guardbands (i.e. safety margins) at the design time. Otherwise, reliability cannot be sustained at runtime. At the end of our presentation, we will distribute to the attendees USB drives, which

Speaker:
Norbert Wehn, University of Kaiserslautern, DE

Abstract:
All today's computing systems rely on an ever increasing amount of (external) memory. Dynamic Random Access Memories (DRAMs) play a central role in this memory hierarchy. DRAMs exhibit a large variation in their parameters and in the future memories such as DRAMs will become even more undependable due to further scaling. This has to be counterbalanced error detection and error correction codes and with higher refresh rates, which leads to a higher DRAM power consumption. Recent research activities resulted in the concept of "approximate DRAM" to save power and improve performance by lowering the refresh rate or disabling refresh completely. In this talk we will give an overview on the aforementioned DRAM challenges, present techniques to mitigate these problems and present a holistic simulation environment for investigations on approximate DRAM and the impact on error resilient applications.