Date: Wednesday 21 March 2018
Time: 17:00 - 18:30
Location / Room: Konf. 6

Chair:
Paul Pop, Technical University of Denmark, DK

Co-Chair:
Petru Eles, Linköping University, SE

This session presents the following EU projects: ARGO—developing a Worst-Case Execution Time (WCET)-aware parallelizing compilation toolchain, GREAT—aiming at using multifunctional standardized stack as a universal spintronic technology for IoT, CONNECT—highlighting the recent advancements of carbon nanotubes as interconnect material and T-CREST—which developed a a real-time multicore processor to be time-predictable and an easy target for static worst-case execution time analysis.

Time	Label	Presentation Title Authors
17:00	8.2.1	USING POLYHEDRAL TECHNIQUES TO TIGHTEN WCET ESTIMATES OF OPTIMIZED CODE: A CASE STUDY WITH ARRAY CONTRACTION Speaker: Steven Derrien, Université de Rennes 1 / IRISA, FR Authors: Thomas Lefeuvre1, Imen Fassi1, Christoph Cullmann2, Gernot Gebhard2, Emin Koray Kasnakli3, Isabelle Puaut1 and Steven Derrien1 1University of Rennes 1/IRISA, FR; 2Absint GmbH, DE; 3Fraunhofer IIS, DE Abstract The ARGO H2020 European project aims at developing a Worst-Case Execution Time (WCET)-aware parallelizing compilation toolchain. This toolchain operates on Scilab and XCoS inputs, and targets ScratchPad memory (SPM)-based multi-cores. Data-layout and loop transformations play a key role in this flow as they improve SPM efficiency and reduce the number of accesses to shared main memory. In this paper, we study how these transformations impact WCET estimates. We demonstrate that they can bring significant improvements of WCET estimates (up to 2.7x) provided that the WCET analysis process is guided with automatically generated flow annotations obtained using polyhedral counting techniques. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	8.2.2	USING MULTIFUNCTIONAL STANDARDIZED STACK AS UNIVERSAL SPINTRONIC TECHNOLOGY FOR IOT Speaker: Mehdi Tahoori, Karlsruhe Institute of Technology, DE Authors: Mehdi Tahoori1, Sarath Mohanachandran Nair1, Rajendra Bishnoi1, Sophiane SENNI2, Jad Mohdad2, Frederick Mailly2, Lionel Torres2, Pascal Benoit2, Abdoulaye Gamatie2, Pascal Nouet2, Kotb Jabeur3, Pierre Vanhauwaert3, Alexandru Atitoaie4, Iona Firastrau4, Gregory Di Pendina3 and Guillaume Prenat3 1Karlsruhe Institute of Technology, DE; 2LIRMM, FR; 3CEA, Univ. Grenoble Alpes, Grenoble, FR; 4Transilvania University of Brasov, RO Abstract For monolithic heterogeneous integration, fast yet low-power processing and storage, and high integration density, the objective of the EU GREAT project is to co-integrate multiple digital and analog functions together within CMOS by adapting the Magnetic Tunneling Junctions (MTJs) into a single baseline technology enabling logic, memory, and analog functions, particularly for Internet of Things (IoT) platforms. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the progress in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	8.2.3	PROGRESS ON CARBON NANOTUBE BEOL INTERCONNECTS Speaker: Benjamin Uhlig, Fraunhofer IPMS, Dresden, DE Authors: Benjamin Uhlig1, Jie Liang2, Jaehyun Lee3, Raphael Ramos4, Abitha Dhavamani1, Nicole Nagy1, Jean Dijon4, Hanako Okuno5, Dipankar Kalita5, Vihar Georgiev3, Asen Asenov3, Salvatore Amoroso6, Liping Wang6, Campbell Millar6, Fabian Koenemann7, Bernd Gotsmann7, Goncalo Goncalves8, Bingan Chen8, Reetu Raj Pandey2, Rongmei Chen2 and Aida Todri-Sanial2 1Fraunhofer IPMS, DE; 2CNRS-LIRMM/University of Montpellier, FR; 3School of Engineering, University of Glasgow, GB; 4CEA-LITEN/University Grenoble Alpes, FR; 5CEA-INAC/University Grenoble Alpes, FR; 6Synopsys Inc., GB; 7IBM Research Zurich, CH; 8Aixtron Ltd., GB Abstract This article is a review of the current progress and results obtained in the European H2020 CONNECT project. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, 2) modeling and simulation from atomistic to circuit-level benchmarking and performance prediction, and 3) characterization and electrical measurements. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a review and informative cornerstone on carbon nanotube interconnects. Download Paper (PDF; Only available from the DATE venue WiFi)
18:15	8.2.4	A WCET-AWARE PARALLEL PROGRAMMING MODEL FOR PREDICTABILITY ENHANCED MULTI-CORE ARCHITECTURES Speaker: Simon Reder, Karlsruhe Institute of Technology (KIT), DE Authors: Simon Reder1, Leonard Masing1, Harald Bucher1, Timon ter Braak2, Timo Stripf3 and Jürgen Becker1 1Karlsruhe Institute of Technology, DE; 2Recore Systems B.V., NL; 3emmtrix Technologies GmbH, DE Abstract Increasing performance requirements for cyber-physical systems in real-time applications raise the necessity to migrate to multi-core processor systems. However, commercial of the shelf multi-core systems are often inappropriate for the real-time domain and real-time capable multi-core programming models are rare. In this paper, we present a solution developed within the EU research project ARGO. By means of a predictability-enhanced NoC-based multi-/many-core architecture, we investigate hardware properties that can help to improve the predictability of the platform and the programming model. Both platform and programming model are complemented by a WCET-aware Architecture Description Language (ADL). This enables a certain degree of hardware abstraction while preserving the relevant details for accurate multi-core WCET analysis algorithms. Target platform and programming model are designed to be statically analyzable by multi-core WCET computation tools, that are part of the automated WCET-aware software parallelization tool flow developed in the ARGO project. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30	IP3-14, 1007	DESIGN OF A TIME-PREDICTABLE MULTICORE PROCESSOR: THE T-CREST PROJECT Speaker and Author: Martin Schoeberl, Technical University of Denmark, DK Abstract Real-time systems need to deliver results in time and often this timely production of a result needs to be guaranteed. Static timing analysis can be used to bound the worst-case execution time of tasks. However, this timing analysis is only possible if the processor architecture is analysis friendly. This paper presents the T-CREST processor, a real-time multicore processor developed to be time-predictable and an easy target for static worst-case execution time analysis. We present how to achieve time-predictability at all levels of the architecture, from the processor pipeline, via a network-on-chip, up to the memory controller. The main architectural feature to provide time predictability is to use static arbitration of shared resources in a time-division multiplexing way. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30		End of session