6.4 Modeling, Control and Scheduling for Cyber-Physical Systems

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Date: Wednesday 21 March 2018
Time: 11:00 - 12:30
Location / Room: Konf. 2

Chair:
Shiyan Hu, Michigan Tech., US

Co-Chair:
Franco Fummi, University of Verona, IT

The fast advancement of cyber-physical systems has been presenting significant design challenges. The papers in this session address these CPS design challenges across layers of control, communication, computation and embedded microarchitecture. They include methodologies for modeling and integrating heterogeneous models to build CPS virtual platforms, routing and scheduling messages with control stability consideration for networked CPS, designing feedback control of EtherCAT networks for reliability enhancement, and scheduling tasks with consideration of cache to maximize control performance.

TimeLabelPresentation Title
Authors
11:006.4.1AUTOMATIC INTEGRATION OF CYCLE-ACCURATE DESCRIPTIONS WITH CONTINUOUS-TIME MODELS FOR CYBER-PHYSICAL VIRTUAL PLATFORMS
Speaker:
Franco Fummi, University of Verona, IT
Authors:
Michele Lora1, Stefano Centomo1, Davide Quaglia1 and Franco Fummi2
1University of Verona, IT; 2Universita' di Verona, IT
Abstract
Development of cyber-physical systems' control algorithms usually relies on architecture-agnostic abstract models, often leading to ineffective implementations. This paper presents a technique to automatically integrate cycle-accurate models of digital HW components with continuous-time physical models. It proposes a solution to the semantic gap between the involved models of computation. Furthermore, model generation and integration for both Simulink-based proprietary environment and FMI-based portable standard are presented. The aim of such techniques is to produce cyber-physical virtual-platforms: a powerful tool to refine control algorithms up to their SW implementations on the actual HW platform.

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11:306.4.2STABILITY-AWARE INTEGRATED ROUTING AND SCHEDULING FOR CONTROL APPLICATIONS IN ETHERNET NETWORKS
Speaker:
Rouhollah Mahfouzi, Linköping University, SE
Authors:
Rouhollah Mahfouzi1, Amir Aminifar2, Soheil Samii3, Ahmed Rezine1, Petru Eles1 and Zebo Peng1
1Linköping University, SE; 2Swiss Federal Institute of Technology in Lausanne (EPFL), CH; 3General Motors Research & Development, US
Abstract
Real-time communication over Ethernet is becoming important in various application areas of cyber-physical systems such as industrial automation and control, avionics, and automotive networking. Since such applications are typically time critical, Ethernet technology has been enhanced to support time-driven communication through the IEEE 802.1 TSN standards. The performance and stability of control applications is strongly impacted by the timing of the network communication. Thus, in order to guarantee stability requirements, when synthesizing the communication schedule and routing, it is needed to consider the degree to which control applications can tolerate message delays and jitters. In this paper we jointly solve the message scheduling and routing problem for networked cyber-physical systems based on the time-triggered Ethernet TSN standards. Moreover, we consider this communication synthesis problem in the context of control applications and guarantee their worst-case stability, taking explicitly into consideration the impact of communication delay and jitter on control quality. Considering the inherent complexity of the network communication synthesis problem, we also propose new heuristics to improve synthesis efficiency without any major loss of quality. Experiments demonstrate the effectiveness of the proposed solutions.

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12:006.4.3FEEDBACK CONTROL OF REAL-TIME ETHERCAT NETWORKS FOR RELIABILITY ENHANCEMENT IN CPS
Speaker:
Tongquan Wei, East China Normal University, CN
Authors:
Liying Li1, Peijin Cong1, Kun Cao1, Junlong Zhou2, Tongquan Wei1, Mingsong Chen1 and Xiaobo Sharon Hu3
1East China Normal University, CN; 2Nanjing University of Science and Technology, CN; 3University of Notre Dame, US
Abstract
EtherCAT has become one of the leading real-time Ethernet solutions for networked industrial systems where a reliable communication infrastructure is needed due to highly error-prone environments. However, existing work on EtherCAT mainly focuses on clock synchronization and timeliness improvement. The reliability of EtherCAT-based networked systems has largely been ignored. In this paper, we present a PID-based feedback control scheme that aims at enhancing reliability of networked systems under timing and system resource constraints. Instead of automatic repeat request method (ARQ), a forward error control technique is introduced to achieve the required system reliability at a lower deadline miss rate of messages. The PID-based feedback control scheme can also improve the stability of a system in terms of deadline miss rate in the presence of bursty errors. Simulation results show that the proposed scheme can achieve reliability enhancement of up to 79% compared to benchmarking methods.

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12:156.4.4CACHE-AWARE TASK SCHEDULING FOR MAXIMIZING CONTROL PERFORMANCE
Speaker:
Wanli Chang, Singapore Institute of Technology, SG
Authors:
Wanli Chang1, Debayan Roy2, Xiaobo Sharon Hu3 and Samarjit Chakraborty2
1Singapore Institute of Technology, SG; 2Technical University of Munich, DE; 3University of Notre Dame, US
Abstract
Embedded control applications are widely implemented on small, low-cost and resource-constrained microcontrollers, e.g., in the automotive domain. Conventionally, control algorithms are designed using model-based approaches, without considering the details of the implementation platform. This leads to inefficient utilization of the resources. With the emergence of the cyber-physical system (CPS)-oriented thinking, there has lately been a strong interest in co-design of control algorithms and their implementation platforms. Some recent efforts have shown that a schedule on multiple applications with more on-chip cache reuse is able to improve the control performance. However, it has not been studied how the control performance can be maximized for a given schedule and how an optimal schedule can be computed. In this work, we propose a two-stage framework to compute the schedule maximizing the overall control performance of all the applications. First, a holistic controller design taking all the sampling periods and sensing-to-actuation delays in a schedule into account is presented, aiming to maximize the overall control performance. Second, a hybrid search algorithm for discrete decision space is reported to efficiently compute an optimal schedule. Experimental results on a case study with multiple automotive applications show that a significant improvement of 10-20% in control performance can be achieved by the proposed cache-aware scheduling approach.

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12:30IP3-3, 135TTW: A TIME-TRIGGERED WIRELESS DESIGN FOR CPS
Speaker:
Romain Jacob, ETH Zurich, CH
Authors:
Romain Jacob1, Licong Zhang2, Marco Zimmerling3, Jan Beutel1, Samarjit Chakraborty2 and Lothar Thiele1
1ETH Zurich, CH; 2Technical University of Munich, DE; 3Technische Universität Dresden, DE
Abstract
Wired fieldbuses have long been proven effective in supporting Cyber-Physical Systems (CPS). However, various domains are now striving for wireless solutions due to ease of deployment or novel functionality requiring the ability to support mobile devices. Low-power wireless protocols have been proposed in response to this need, but requirements of a large class of CPS applications can still not be satisfied. We thus propose Time-Triggered Wireless (TTW), a distributed low-power wireless system design that minimizes communication energy consumption and offers end-to-end timing predictability, runtime adaptability, reliability, and low latency. Evaluation shows a 2x reduction in communication latency and 33-40% lower radio-on time compared with DRP, the closest related work, validating the suitability of TTW for new exciting wireless CPS applications.

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12:31IP3-4, 429PHYLAX: SNAPSHOT-BASED PROFILING OF REAL-TIME EMBEDDED DEVICES VIA JTAG INTERFACE
Speaker:
Eduardo Chielle, New York University Abu Dhabi, BR
Authors:
Charalambos Konstantinou1, Eduardo Chielle2 and Michail Maniatakos2
1New York University, US; 2New York University Abu Dhabi, AE
Abstract
Real-time embedded systems play a significant role in the functionality of critical infrastructure. Legacy microprocessor-based embedded systems, however, have not been developed with security in mind. Applying traditional security mechanisms in such systems is challenging due to computing constraints and/or real-time requirements. Their typical 20-30 year lifespan further exacerbates the problem. In this work, we propose PHYLAX, a plug-and-play solution to detect intrusions in already installed embedded devices. PHYLAX is an external monitoring tool which does not require code instrumentation. Also, our tool adapts and prioritizes intrusion detection based on the requirements of the underlying infrastructure (power grid, chemical factory, etc.) as well as the computing capabilities of the target embedded system (CPU model, memory size, etc.). PHYLAX can be employed on any legacy device which incorporates a JTAG interface. As a case study, we present the inclusion of PHYLAX on a power grid recloser controller.

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12:32IP3-5, 463CHARACTERIZING DISPLAY QOS BASED ON FRAME DROPPING FOR POWER MANAGEMENT OF INTERACTIVE APPLICATIONS ON SMARTPHONES
Speaker:
Chung-Ta King, National Tsing Hua University, TW
Authors:
Kuan-Ting Ho1, Chung-Ta King1, Bhaskar Das1 and Yung-Ju Chang2
1National Tsing Hua University, TW; 2National Chiao Tung University, TW
Abstract
User-centric power management in smartphones aims to conserve power without affecting user's perceived quality of experience. Most existing works focus on periodically updated applications such as games and video players and use a fixed frame rate, measured in frame per second (FPS), as the metric to quantify the display quality of service (QoS). The idea is to adjust the CPU/GPU frequency just enough to maintain the frame rate at a user satisfactory level. However, when applied to aperiodically-updated interactive applications, e.g. Facebook or Instagram, that draw the frame buffer at a varying rate in response to user inputs, such a power management strategy becomes too conservative. Based on real user experiments, we observe that users can tolerate a certain percentage of frame drops when running aperiodically updated applications without affecting their perceived display quality. Hence, we introduce a new metric to characterize display quality of service, called the frame drawn ratio (FDR), and propose a new CPU/GPU frequency governor based on the FDR metric. The experiments by real users show that the proposed governor can conserve 17.2% power in average when compared to the default governor, while maintaining the same or even better QoE rating.

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12:30End of session
Lunch Break in Großer Saal and Saal 1



Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD).

Lunch Breaks (Großer Saal + Saal 1)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 20, 2018

  • Coffee Break 10:30 - 11:30
  • Lunch Break 13:00 - 14:30
  • Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20
  • Coffee Break 16:00 - 17:00

Wednesday, March 21, 2018

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:30
  • Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20
  • Coffee Break 16:00 - 17:00

Thursday, March 22, 2018

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:00
  • Keynote Lecture in "Saal 2" 13:20 - 13:50
  • Coffee Break 15:30 - 16:00