With Billions of IoT devices getting connected to the Internet, it is ever more important to make these devices are as secure and robust as possible.  These devices should be protected from running malicious software and it is critical that the sensitive user data that these device handle is kept secret.  These security requirements add significant responsibility to the system-on-chip solutions at their heart.  The SimpleLink Wi-Fi family of devices have been instrumental in enabling small, power-optimised IoT devices leveraging existing Wi-Fi infrastructure.  The first generation CC3100/CC3200 provides secure network socket connectivity to enable secure data connection to remote servers and services.  The next generation of this family, CC3120/CC3220, significantly extends these capabilities by not only offering the latest network security ciphers, but also an advanced security platform to protect system assets for the entire life-cycle of the product, offering customers further confidence and protection.  This presentation aims to detail the challenges of security in today's IoT products and how the architecture of this latest generation of embedded Wi-Fi platform has been designed to efficiently address the technical challenges presented and how these advanced and differentiated security capabilities can be exposed and enabled for all users via a 'simple' SimpleLink API.

Optimized digital standard cells which efficiently operate in the near-threshold voltage (NTV) region are one basic enabler for the next generation of smart sensor systems especially of IoT. While a significant reduction of both dynamic power and leakage power is necessary to meet the power requirements of such systems, a reasonable performance still needs to be supported, to enable on-chip pre-processing and analysis of the sensor data.

The presentation will provide an overview about the development of a near-threshold digital library implemented in X-FAB's 0.18 µm Silicon-on-Insulator technology carried out in the framework of the BMBF-funded project RoMulus [1]. A digital ultra-low-power logic library was developed based on the standard CMOS technique, which operates in NTV region with 700 ... 900mV operating voltage at -20 °C ... 85 °C. Additionally supporting cells like level shifters and an NTV I/O pad cell library with ESD protection have been developed. The cells have been implemented with a NTV test chip, using a power-aware digital implementation flow. The test chip has been manufactured and characterized. The test results prove the function of the NTV logic cells in the specified voltage and temperature range and demonstrate the feasibility and possibilities of the development of further NTV logic cells.

Microelectromechanical systems (MEMS) are widely used in IoT devices. Due to the lack of sophisticated component libraries for MEMS, highly optimized MEMS sensors are currently designed using a polygon-driven design flow. The advantage of this design flow is its accurate mechanical simulation, but it lacks of methods for analyzing the parasitic electrostatic effects arising from the electric coupling between (stationary) wiring and the mechanical structures. For a robust and secure MEMS design, it is necessary to analyze, to optimize and finally to include these parasitics into the MEMS-ASIC co-simulation.
The presentation will provide an overview about the development of new methods for the analysis of parasitic electrostatic effects by a 3D field-solver carried out in the framework of the BMBF-funded project RoMulus. The developed methods include a rule based structure recognition algorithm, which allows the identification of meaningful MEMS sensor parts out of the plain graphical polygon representation of the MEMS layout. The mapping of the extracted RC-values to the recognized elements of the MEMS sensor enables a detailed analysis and optimization of actual MEMS sensors. This method is upgraded by a feature that enables the parasitics arising from in-plane, sensor-structure motion to be extracted quasi-dynamically.

Power optimized digital standard cell libraries are a "must have" when it comes to the implementation of power efficient smart sensor systems for IoT applications. In the framework of the BMBF-funded project RoMulus, the Fritz Huettinger Chair of Microelectronics of the University of Freiburg and X-FAB jointly develop near- and sub-threshold digital standard cell libraries for both ultra low-voltage and ultra low-power applications.

 The presentation provides an overview of our research activities on a sub-threshold digital circuit design technique for ultra low-voltage and ultra low-power applications. At first, the fundamentals of the Schmitt-Trigger based design methodology are presented that allow reducing the supply voltage of digital circuits to a few tens of millivolts in a 130nm CMOS technology. Subsequently, the BMBF-funded project RoMulus is considered in which the Schmitt-Trigger based design methodology is applied to the design of a digital standard cell library in an X-FAB 180nm CMOS process. Measurement results as well as an outlook on the next steps in the project conclude the presentation.