10.8 An Industry Approach to FPGA and SOC System Development and Verification
Date: Thursday 22 March 2018
Time: 11:00 - 12:30
Location / Room: Exhibition Theatre
Organiser:
Alexander Schreiber, The MathWorks, DE
Speaker:
John Zhao, MathWorks, US
MATLAB and Simulink provide a rich environment for embedded-system development, with libraries of proven, specialized algorithms ready to use for specific applications. The environment enables a model-based design workflow for fast prototyping and implementation of the algorithms on heterogeneous embedded targets, such as MPSoC. A system-level design approach enables architectural exploration and partitioning, as well as coordination between SW and HW development workflows. Functional verification throughout the design process improves coverage and test-case generation while reducing the time and resources required.
In this exhibition theater session, you will learn
- Automatically generate synthesizable RTL code from you MATLAB and Simulink algorithms targeting FPGA, ASIC or Programmable SoC
- A HW/SW co-design workflow that combines system level design and simulation with automatic code generation
- Functional verification using MATLAB and Simulink in a SystemVerilog workflow illustrated by a detailed example
| Time | Label | Presentation Title Authors |
|---|---|---|
| 12:30 | End of session Lunch Break in Großer Saal and Saal 1
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018
Wednesday, March 21, 2018
Thursday, March 22, 2018
|
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