10.5 Mixed-Criticality and Fault-Tolerant Real-Time Embedded Systems

Time	Label	Presentation Title Authors
11:00	10.5.1	AVAILABILITY ENHANCEMENT AND ANALYSIS FOR MIXED-CRITICALITY SYSTEMS ON MULTI-CORE Speaker: Roberto Medina, Télécom ParisTech, FR Authors: Roberto Medina, Etienne Borde and Laurent Pautet, Télécom ParisTech, FR Abstract In the critical systems domain, Mixed Criticality Systems (MCS) improve considerably the usage of computation resources by running tasks with different levels of criticality on multi-core processors. To ensure the safety of MCS, services provided by low criticality tasks are degraded or stopped whenever high criticality tasks need more computation time than initially credited. The evaluation of this degradation is hardly considered in the literature although low criticality services are of prime importance for the quality of service (QoS) of critical systems. In this paper, we propose a method to evaluate the availability of low criticality services, i.e. how often these services are delivered in MCS. We also propose a task model that improves this availability, demonstrated thanks to our evaluation method on an illustrative example of MCS. Download Paper (PDF; Only available from the DATE venue WiFi)
11:30	10.5.2	MIXED-CRITICALITY SCHEDULING WITH MEMORY BANDWIDTH REGULATION Speaker: Muhammad Ali Awan, CISTER/INESC-TEC and ISEP/IPP, Porto, Portugal, PT Authors: Muhammad Ali Awan¹, Pedro Souto², Konstantinos Bletsas¹, Benny Akesson¹ and Eduardo Tovar¹ ¹CISTER/INESC-TEC, ISEP, PT; ²Faculty of Engineering of the University of Porto, PT Abstract Mixed-criticality (MC) multicore system design must reconcile safety guarantees and high performance. The interference among cores on shared resources in such systems leads to unpredictable temporal behaviour. Memory bandwidth regulation among different cores can be a useful tool to mitigate the interference when accessing main memory. However, for mixed-criticality systems conforming to the (well-established) Vestal model, the existing schedulability analyses are oblivious to memory stalling effects, including stalls from memory bandwidth regulation. This makes it unsafe. In this paper, we address this issue by formulating a schedulability analysis for mixed-criticality fixed-priority-scheduled multicore systems using per-core memory access regulation. We also propose multiple heuristics for memory bandwidth allocation and task-to-core assignment. We implement our analysis and heuristics in a tool and evaluate them, performance-wise, through extensive experiments. Our experiments show that stall-oblivious schedulability analysis may be optimistic due to contention on shared memory resources. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	10.5.3	DESIGN AND VALIDATION OF FAULT-TOLERANT EMBEDDED CONTROLLERS Speaker: Soumyajit Dey, IIT Kharagpur, IN Authors: Saurav Kumar Ghosh¹, Soumyajit Dey², Dip Goswami³, Daniel Mueller-Gritschneder⁴ and Samarjit Chakraborty⁴ ¹Dept. of CSE, IIT Kharagpur, IN; ²Indian Institute of Technology Kharagpur, IN; ³Eindhoven University of Technology, NL; ⁴Technical University of Munich, DE Abstract Embedded control systems are an important and often safety-critical class of applications that need to operate reliably even in the presence of faults. We show that intermittent fault scenarios caused by wear-out effects due to a higher density and a smaller geometry of the embedded electronic components may become a reliability concern for real-time embedded control applications. To mitigate the effects of such intermittent faults, we propose a novel fault-tolerant controller design method such that the resulting controllers ensure closed loop stability (i.e., guarantee safety) with only possibly degraded performance under such fault scenarios. In order to measure the amortized performance offered by the software implementations of such fault-tolerant controllers, we provide a program analysis methodology that statically estimates the quality of control guaranteed by the C code implementation of the fault-tolerant control law. This combination of fault-tolerant controller design followed by performance feedback computed using a formal analysis is illustrated with a case study from the automotive domain. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	IP4-16, 181	END-TO-END LATENCY ANALYSIS OF CAUSE-EFFECT CHAINS IN AN ENGINE MANAGEMENT SYSTEM Speaker: Junchul Choi, Seoul National University, KR Authors: Junchul Choi, Donghyun Kang and Soonhoi Ha, Seoul National University, KR Abstract An engine management system consists of periodic or sporadic real-time tasks. A task is a set of runnables that may be fully preemptive or partially at runnable boundaries. A cause-effect chain is defined as a chain of runnables that are connected by the read/write dependency. We propose a novel analytical technique to estimate the end-to-end latency of a cause-effect chain by considering conservatively estimated schedule time bounds of associated runnables. The proposed approach is verified with an industrial-strength automotive benchmark. Download Paper (PDF; Only available from the DATE venue WiFi)
12:31	IP5-12, 442	TOWARDS FULLY AUTOMATED TLM-TO-RTL PROPERTY REFINEMENT Speaker: Vladimir Herdt, University of Bremen, DE Authors: Vladimir Herdt¹, Hoang M. Le¹, Daniel Grosse² and Rolf Drechsler² ¹University of Bremen, DE; ²University of Bremen/DFKI GmbH, DE Abstract An ESL design flow starts with a TLM description, which is thoroughly verified and then refined to a RTL description in subsequent steps. The properties used for TLM verification are refined alongside the TLM description to serve as starting point for RTL property checking. However, a manual transformation of properties from TLM to RTL is error prone and time consuming. Therefore, in this paper we propose a fully automated TLM-to-RTL property refinement based on a symbolic analysis of transactors. We demonstrate the applicability of our property refinement approach using a case study. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break in Großer Saal and Saal 1 Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 21, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 22, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00 Keynote Lecture in "Saal 2" 13:20 - 13:50 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

11:00

10.5.1

AVAILABILITY ENHANCEMENT AND ANALYSIS FOR MIXED-CRITICALITY SYSTEMS ON MULTI-CORE
Speaker:
Roberto Medina, Télécom ParisTech, FR
Authors:
Roberto Medina, Etienne Borde and Laurent Pautet, Télécom ParisTech, FR
Abstract
In the critical systems domain, Mixed Criticality Systems (MCS) improve considerably the usage of computation resources by running tasks with different levels of criticality on multi-core processors. To ensure the safety of MCS, services provided by low criticality tasks are degraded or stopped whenever high criticality tasks need more computation time than initially credited. The evaluation of this degradation is hardly considered in the literature although low criticality services are of prime importance for the quality of service (QoS) of critical systems. In this paper, we propose a method to evaluate the availability of low criticality services, i.e. how often these services are delivered in MCS. We also propose a task model that improves this availability, demonstrated thanks to our evaluation method on an illustrative example of MCS.
Download Paper (PDF; Only available from the DATE venue WiFi)

11:30

10.5.2

MIXED-CRITICALITY SCHEDULING WITH MEMORY BANDWIDTH REGULATION
Speaker:
Muhammad Ali Awan, CISTER/INESC-TEC and ISEP/IPP, Porto, Portugal, PT
Authors:
Muhammad Ali Awan¹, Pedro Souto², Konstantinos Bletsas¹, Benny Akesson¹ and Eduardo Tovar¹
¹CISTER/INESC-TEC, ISEP, PT; ²Faculty of Engineering of the University of Porto, PT
Abstract
Mixed-criticality (MC) multicore system design must reconcile safety guarantees and high performance. The interference among cores on shared resources in such systems leads to unpredictable temporal behaviour. Memory bandwidth regulation among different cores can be a useful tool to mitigate the interference when accessing main memory. However, for mixed-criticality systems conforming to the (well-established) Vestal model, the existing schedulability analyses are oblivious to memory stalling effects, including stalls from memory bandwidth regulation. This makes it unsafe. In this paper, we address this issue by formulating a schedulability analysis for mixed-criticality fixed-priority-scheduled multicore systems using per-core memory access regulation. We also propose multiple heuristics for memory bandwidth allocation and task-to-core assignment. We implement our analysis and heuristics in a tool and evaluate them, performance-wise, through extensive experiments. Our experiments show that stall-oblivious schedulability analysis may be optimistic due to contention on shared memory resources.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:00

10.5.3

DESIGN AND VALIDATION OF FAULT-TOLERANT EMBEDDED CONTROLLERS
Speaker:
Soumyajit Dey, IIT Kharagpur, IN
Authors:
Saurav Kumar Ghosh¹, Soumyajit Dey², Dip Goswami³, Daniel Mueller-Gritschneder⁴ and Samarjit Chakraborty⁴
¹Dept. of CSE, IIT Kharagpur, IN; ²Indian Institute of Technology Kharagpur, IN; ³Eindhoven University of Technology, NL; ⁴Technical University of Munich, DE
Abstract
Embedded control systems are an important and often safety-critical class of applications that need to operate reliably even in the presence of faults. We show that intermittent fault scenarios caused by wear-out effects due to a higher density and a smaller geometry of the embedded electronic components may become a reliability concern for real-time embedded control applications. To mitigate the effects of such intermittent faults, we propose a novel fault-tolerant controller design method such that the resulting controllers ensure closed loop stability (i.e., guarantee safety) with only possibly degraded performance under such fault scenarios. In order to measure the amortized performance offered by the software implementations of such fault-tolerant controllers, we provide a program analysis methodology that statically estimates the quality of control guaranteed by the C code implementation of the fault-tolerant control law. This combination of fault-tolerant controller design followed by performance feedback computed using a formal analysis is illustrated with a case study from the automotive domain.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

IP4-16, 181

END-TO-END LATENCY ANALYSIS OF CAUSE-EFFECT CHAINS IN AN ENGINE MANAGEMENT SYSTEM
Speaker:
Junchul Choi, Seoul National University, KR
Authors:
Junchul Choi, Donghyun Kang and Soonhoi Ha, Seoul National University, KR
Abstract
An engine management system consists of periodic or sporadic real-time tasks. A task is a set of runnables that may be fully preemptive or partially at runnable boundaries. A cause-effect chain is defined as a chain of runnables that are connected by the read/write dependency. We propose a novel analytical technique to estimate the end-to-end latency of a cause-effect chain by considering conservatively estimated schedule time bounds of associated runnables. The proposed approach is verified with an industrial-strength automotive benchmark.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:31

IP5-12, 442

TOWARDS FULLY AUTOMATED TLM-TO-RTL PROPERTY REFINEMENT
Speaker:
Vladimir Herdt, University of Bremen, DE
Authors:
Vladimir Herdt¹, Hoang M. Le¹, Daniel Grosse² and Rolf Drechsler²
¹University of Bremen, DE; ²University of Bremen/DFKI GmbH, DE
Abstract
An ESL design flow starts with a TLM description, which is thoroughly verified and then refined to a RTL description in subsequent steps. The properties used for TLM verification are refined alongside the TLM description to serve as starting point for RTL property checking. However, a manual transformation of properties from TLM to RTL is error prone and time consuming. Therefore, in this paper we propose a fully automated TLM-to-RTL property refinement based on a symbolic analysis of transactors. We demonstrate the applicability of our property refinement approach using a case study.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

End of session
Lunch Break in Großer Saal and Saal 1

Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD).

Lunch Breaks (Großer Saal + Saal 1)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 20, 2018