Tutorial

Printer-friendly version PDF version
Monday Tutorials

M12 All You Need to Know About Hardware Trojans and Counterfeit Ics

Agenda

Agenda

TimeLabelSession
14:30M12.1Session 1
00:00M12.1.1Background and motivation for hardware Trojan and counterfeit prevention/detection

00:00M12.1.2Taxonomies related to both topics

16:30M12.2Session 2
00:00M12.2.1Existing solutions

00:00M12.2.2Open challenges

00:00M12.2.3New and unified solutions to address these challenges

M11 Post-Silicon Validation and Debug: Best Practices and Disruptive Innovation

Agenda

Agenda

TimeLabelSession
14:30M11.1Session 1
00:00M11.1.1Big Picture (Nagib Hakim, Subhasish Mitra, Amir Nahir)
Nagib Hakim1, Subhasish Mitra2 and Amir Nahir3
1Intel Corporation Santa Clara, US; 2Stanford University, US; 3IBM Research Labs Haifa, IL

16:30M11.2Session 2
00:00M11.2.1Observability enhancement during post-silicon validation (Alan Hu, Subhasish Mitra)
Alan Hu1 and Subhasish Mitra2
1University of British Columbia, CA; 2Stanford University, US

M10 A Cyber-Physical Approach to Modeling, Simulation and Verification of Smart Systems

Agenda

Agenda

TimeLabelSession
14:30M10.1Session 1
00:00M10.1.1Introduction to smart systems and cyber-physical systems (Davide Quaglia)
Davide Quaglia, EDALab s.r.l, IT

00:00M10.1.2Multi-domain modeling languages and methodologies (Davide Quaglia)
Davide Quaglia, EDALab s.r.l, IT

00:00M10.1.3Multi-scale modeling: abstraction and refinement (Dimitris Drogoudis)
Dimitris Drogoudis, Agilent, BE

16:30M10.2Session 2
00:00M10.2.1Verification of Cyber-Physical Systems (Davide Bresolin)
Davide Bresolin, University of Bologna, IT

00:00M10.2.2Application of modeling concepts and tools to real case studies (Dimitris Drogoudis)
Dimitris Drogoudis, Agilent, BE

00:00M10.2.3Application of verification concepts and tools to real case studies (Davide Bresolin)
Davide Bresolin, University of Bologna, IT

M04 Dynamic Heterogeneous Architectures to Address The Efficiency Crisis!

Agenda

Agenda

TimeLabelSession
09:30M04.1Session 1
00:00M04.1.1Reviews of major challenges facing semiconductor industry, introduce the concept of dynamic heterogeneous architecture and concept of core pooling (Houman Homayoun)
Houman Homayoun, ,

00:00M04.1.2Pathfinding methodology for optimal design and integration of 2.5D/3D heterogeneous systems
Farhang Yazdani, ,

11:30M04.2Session 2
00:00M04.2.13D systems as platforms for "flexible heterogeneity", cache/memory pooling, power & temperature challenges
Ayse Coskun, ,

00:00M04.2.2Managing dynamically configurable systems: optimizing energy under performance constraints; Coordinating adaptation across the system stack
Hank Hoffman, ,

 

M03 Automatic fixed-point conversion: a gate way to high-level power optimization

Agenda

Agenda

TimeLabelSession
09:30M03.1Session 1
00:00M03.1.1Introduction

00:00M03.1.2Fixed-point arithmetic

00:00M03.1.3Range analysis

11:30M03.2Session 2
00:00M03.2.1Precision analysis

00:00M03.2.2Word-length optimization

00:00M03.2.3Opportunistic run-time precision adaptation

00:00M03.2.4Conclusion

 

M06 Testing of TSV-Based 2.5D- and 3D-Stacked ICs

Agenda

Agenda

TimeLabelSession
09:30M06.1Session 1
00:00M06.1.1Introduction

00:00M06.1.2Overview of 2.5D- and 3D-technology

00:00M06.1.33D test flows and test contents

00:00M06.1.43D test access: wafer probing (industry/research)

11:30M06.2Session 2
00:00M06.2.13D test access: DfT architecture (incl. IEEE P1838) and optimizations

00:00M06.2.23D cost flow modeling (with case studies)

00:00M06.2.3Conclusion

M02 Software Debug on ARM Processors in Emulation

Agenda

Agenda

TimeLabelSession
09:30M02.1Session 1
00:00M02.1.1Options for software debug and trace in the context of design running in emulation

00:00M02.1.2Understanding the trade-offs in terms of performance, functionality, and intrusiveness of different debug approaches

11:30M02.2Session 2
00:00M02.2.1Concurrent debug of multiple cores in emulation

00:00M02.2.2Correlation of hardware and software debug views

00:00M02.2.3Efficient utilization of emulation resources during software debug

M05 Wireless NoC as Interconnection Backbone for Multicore Chips: Promises, Challenges, and Recent Developments

Agenda

Agenda

TimeLabelSession
09:30M05.1Session 1
00:00M05.1.1Foundations of On-chip Communication: Performance and Power Management in 2D and 3D Multicore Platforms
Radu Marculescu, ,

00:00M05.1.2WiNoC: Network Architecture and Communication Resource Management
Partha Pratim Pande, ,

11:30M05.2Session 2
00:00M05.2.1Millimeter-Wave Wireless Link: The Physical Layer Design for WiNoCs
Deukhyoun Heo, ,

00:00M05.2.13D WiNoC Architectures
Hiroki Matsutani, ,

M09 Energy-Efficient System Design Through Error-Resilient Computing

Agenda

Agenda

TimeLabelSession
14:30M09.1Session 1
00:00M09.1.1Error-resilient Computing - Motivation and Example Applications
Saibal Mukhopaddhyay, University of Georgia Tech, US

00:00M09.1.2Error-resilience for general-purpose computing - Razor
Shidhartha Das, ARM Ltd, GB

16:30M09.2Session 2
00:00M09.2.1Approximate Computing - A circuits and architecture perspective
Anand Raghunathan, Purdue University, US

00:00M09.2.2Approximate Computing - A software and applications perspective
Srimat Chakradhar, NEC Labs, US

M08 Microfluidic Biochips: A Vision for More than Moore and Biochemistry-on-Chip

Agenda

Agenda

TimeLabelSession
14:30M08.1Session 1
00:00M08.1.1Technology and application drivers

00:00M08.1.2Synthesis techniques

16:30M08.2Session 2
00:00M08.2.1Testing and design-for-testability

00:00M08.2.2Cyberphysical integration and dynamic adaptation

M01 Development of mixed-criticality systems based on system partitioning

Agenda

Agenda

TimeLabelSession
09:30M01.1Session 1
00:00M01.1.1Challenges in the development of high-integrity embedded systems
Jon Pérez, IK4-IKERLAN, ES

00:00M01.1.2Mixed criticality systems based on system partitioning
Alfons Crespo, Universidad Politécnica de Valencia, ES

00:00M01.1.3The XtratuM hypervisor
Alfons Crespo, Universidad Politécnica de Valencia, ES

11:30M01.2Session 2
00:00M01.2.1Framework for the development of mixed criticality systems
Alejandro Alonso, Universidad Politécnica de Madrid, ES

00:00M01.2.2Use case: development of a mixed-criticality embedded system; Aerospace (Alejandro) and Wind-power (Jon)
Alejandro Alonso1 and Jon Pérez2
1Universidad Politécnica de Madrid, ES; 2IK4-IKERLAN, ES

00:00M01.2.3Conclusion and future directions

M07 L4/Fiasco.OC - A Microkernel OS Designed for Security, Real-Time And Reliability

Agenda

Agenda

TimeLabelSession
14:30M07.1Session 1
00:00M07.1.1Why we need microkernels
Hermann Härtig, Technische Universität Dresden, DE

00:00M07.1.2Isolation for Security, Portability, and Real-Time
Adam Lackorzynski, Kernkonzept GmbH, DE

00:00M07.1.3Building a Secure System on top of Fiasco.OC
Carsten Weinhold, Technische Universität Dresden, DE

00:00M07.1.4Fiasco.OC for Reliability and Fault Tolerance
Björn Döbel, Technische Universität Dresden, DE

16:30M07.2Session 2
00:00M07.2.1Hands On Session (Please bring your laptop)

00:00M07.2.2Practical Introduction to running L4/Fiasco.OC

00:00M07.2.3System Setup and Application Development

Syndicate content