Technical Programme Committee 2014

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Track D: Design, Methods and Tools (click to open)

Design Methods and Tools, addressing design automation and design tools for electronic and embedded systems. Emphasis is on methods and tools related to the use of computers in designing products. This includes designer feedback on existing design methods and tools as well as to initiate discussions on requirements of future system architectures, design flows and environments.

Track Chair: Luca Fanucci, University of Pisa, IT, Contact


D1 System Specifications, Models, and Methodologies (click to open)

Chair: Christian Haubelt, University of Rostock, DE, Contact

Co-Chair: Andy Pimentel, University of Amsterdam, NL, Contact

Topic Members (click to open)

  • Andreas Gerstlauer, University of Texas at Austin, US, Contact
  • Jan Haase, Technical University Vienna, AT, Contact
  • Jorn W. Janneck, Lund University, SE, Contact
  • Wolfgang Mueller, Universität Paderborn, DE, Contact
  • Frank Oppenheimer, OFFIS e. V., DE, Contact
  • Francois Pecheux, UPMC/LIP6, FR, Contact
  • Laurence Pierre, TIMA, FR, Contact
  • Ingo Sander, Royal Institute of Technology, SE, Contact
  • Leandro Indrusiak, University of York, GB, Contact
  • Sander Stuijk, Eindhoven University of Technology, NL, Contact
  • Eugenio Villar, University of Cantabria, ES, Contact

Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

D2 System Design, Synthesis and Optimization (click to open)

Chair: Luciano Lavagno, Politecnico di Torino, IT, Contact

Co-Chair: , Contact

Topic Members (click to open)

  • Rainer Doemer, University of California, Irvine, US, Contact
  • Soonhoi Ha, Seoul National University, KR, Contact
  • Andreas Herkersdorf, TU München, DE, Contact
  • Jan Madsen, Technical University of Denmark, DK, Contact
  • Sudeep Pasricha, Colorado State University, US, Contact
  • Donatella Sciuto, Politecnico di Milano, It, Contact
  • Todor Stefanov, Leiden University, NL, Contact
  • Jürgen Teich, University of Erlangen-Nuremberg, DE, Contact
  • Yosinori Watanabe, Cadence Design Systems, US, Contact
  • Jason Xue Chun, City University of Hong Kong, HK, Contact

Synthesis of complete systems, application- and domain-specific synthesis techniques; system-level models for design, optimization and synthesis; hardware/software co-design and partitioning issues; hardware/software interface and communication synthesis; interface-based and correct-by construction designs; system-level scheduling techniques; protocol synthesis and optimization; system optimization for all cost functions (timing, electrical, non-functional); multi-objective optimization techniques for system level design; large-scale and industrial case studies involving full system optimization and synthesis.

D3 Simulation and Validation (click to open)

Chair: Mark Zwolinski, University of Southampton, GB, Contact

Co-Chair: Prabhat Mishra, University of Florida, US, Contact

Topic Members (click to open)

  • Andrea Acquaviva, Politecnico di Torino, IT, Contact
  • Valeria Bertacco, University of Michigan, US, Contact
  • Mingsong Chen, East China Normal University, CN, Contact
  • Pallab Dasgupta, Indian Institute of Technology Kharagpur, IN, Contact
  • Adrian Evans, Iroc, FR, Contact
  • Franco Fummi, Universita' di Verona, IT, Contact
  • Rand Gray, Intel Corporation, US, Contact
  • Daniel Grosse, Solvertec GmbH, DE, Contact
  • Michael Hsiao, Virginia Tech, US, Contact
  • Elena Vatajelu, Politecnico de Torino, IT, Contact
  • Florian Letombe, Springsoft, FR, Contact
  • Ronny Morad, IBM Research - Haifa, IL, Contact
  • Edouard Ngoya, XLIM-CNRS, University of Limoges, FR, Contact
  • Jaan Raik, Tallinn University of Technology, Department of Computer Engineering, EE, Contact
  • Sandip Ray, Intel, US, Contact
  • Pablo Sanchez, University of Cantabria, ES, Contact
  • Alper Sen, Bogazici University, TR, Contact

Simulation-based verification; post-silicon validation; hardware/software co-simulation and validation; test generation for validation; transaction-level validation; validation using semi-formal methods; testbench generation; design error debug and diagnosis; advanced simulation and emulation techniques from system to circuit level; simulation accelerators; multi-domain simulation techniques for mixed systems; validation of cyber-physical systems, multicore SoCs, and emerging architectures.

D4 Design for power, variability and aging (click to open)

Chair: Domenik Helms, OFFIS, DE, Contact

Co-Chair: Marisa Lopez-Vallejo, UPM, ES, Contact

Topic Members (click to open)

  • Antonio J. Acosta-Jimenez, University of Seville/IMSE, ES, Contact
  • Antonio Rubio, Universitat Politècnica de Catalunya (UPC), ES, Contact
  • Naehyuck Chang, Seoul National University, KR, Contact
  • Edith Beigne, CEA-LETI Minatec, FR, Contact
  • Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
  • Alberto Macii, Politecnico di Torino, IT, Contact
  • Tudor Murgan, Intel, DE, Contact
  • Alberto Nannarelli, DTU, DK, Contact
  • Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
  • , Contact
  • Grasser Tibor, TU Vienna, AT, Contact

Design methods, techniques and case studies for power, variability or aging aware design, for analog and digital circuits, RT and IP components, memories, FPGAs, HW and SW systems. Main topics are dynamic power, leakage currents, process, temperature and voltage variations, degradation mechanisms, power management, run-time adaption techniques, redundancy and recomputation, 3D stacking, energy harvesting, battery

D5 Power Estimation and Optimization (click to open)

Chair: Jian-Jia Chen, KIT, DE, Contact

Co-Chair: William Fornaciari, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Yiran Chen, Seagate Technology, US, Contact
  • Josef Haid, Infineon, AT, Contact
  • Joerg Henkel, Karlsruhe Institute of Technology, DE, Contact
  • Francesc Moll, Universitat Politècnica de Catalunya, ES, Contact
  • Wolfgang Nebel, Oldenburg University and OFFIS, DE, Contact
  • Mauro Olivieri, Sapienza University of Rome, IT, Contact
  • Massimo Poncino, Politecnico di Torino, IT, Contact
  • Anand Raghunathan, Purdue University, US, Contact
  • Olivier Sentieys, CAIRN,IRISA, FR, Contact
  • Xiaorui Wang, University of Ohio, US, Contact
  • Chia-Lin Yang, National Taiwan University, TW, Contact

Algorithms, techniques and tools for power and temperature modeling, estimation and optimization of electronic systems applicable at all levels of the design hierarchy, from system-level specification to layout, including software and run-time management.

D6 Emerging Technologies, Systems and Applications (click to open)

Chair: Siddharth Garg, University of Waterloo, CA, Contact

Co-Chair: Michael Niemier, University Of Notre Dame, US, Contact

Topic Members (click to open)

  • Paul Bogdan, Carnegie Mellon University, US, Contact
  • Philip Brisk, University of California, Riverside, US, Contact
  • Smita Krishnaswamy, Columbia University, US, Contact
  • Dhireesha Kudithipudi, Rochester Institute of Technology, US, Contact
  • Helen Li, University of Pittsburgh, US, Contact
  • Dmitri Maslov, National Science Foundation, US, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Marco Ottavi, University of Roma, IT, Contact
  • Wenjing Rao, University of Illinois at Chicago, US, Contact
  • Aida Todri-Sanial, CNRS - LIRMM, FR, Contact
  • Guangyu Sun, Peking University, CN, Contact
  • Yvain Thonnart, CEA, LETI, MINATEC, FR, Contact
  • Chun-Yao Wang, National Tsing Hua University, TW, Contact
  • Yu Wang, Tsinghua University, CN, Contact

Modeling, circuit design and design automation flows for future technologies: 3D integration; MEMS; non-CMOS logic, memory, and interconnect (e.g., STT-RAM, PCRAM, optical, etc.); emerging FET devices (e.g., graphene-based FETs, TFETs, etc.). Biologically-based or biologically-inspired computing systems; Bio-MEMS, lab-on-a-chip. System design methods, models of computation, and case studies for emerging applications: quantum computing, reversible logic, wearable computing, e-textiles, etc.

D7 Formal Methods and Verification (click to open)

Chair: Jason Baumgartner, IBM Corporation, US, Contact

Co-Chair: Julien Schmaltz, Open University, NL, Contact

Topic Members (click to open)

  • Armin Biere, Universitaet Linz, AT, Contact
  • Per Bjesse, Synopsys, IE, Contact
  • Gianpiero Cabodi, Politecnico di Torino, IT, Contact
  • Alessandro Cimatti, FBK-irst (Fondazione Bruno Kessler - Center for Information technology), IT, Contact
  • Barbara Jobstmann, VERIMAG, FR, Contact
  • Fahim Rahim, Atrenta, FR, Contact
  • Christoph Scholl, University Freiburg, DE, Contact
  • Thomas Wahl, Northeastern University Boston, US, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem-proving, abstraction and decomposition techniques, and real-time verification); technologies supporting formal verification (including SMT, SAT, BDD, ATPG, and related work); semi-formal verification techniques; applications and case studies; formal verification of IPs, SoCs, cores, real-time and embedded systems; verification in practice, namely the integration of verification into the design flow; challenges of multi-cores, both as verification targets and as verification host platforms.

D8 Network on Chip (click to open)

Chair: Federico Angiolini, iNoCs, CH, Contact

Co-Chair: Fabien Clermidy, CEA-LETI, FR, Contact

Topic Members (click to open)

  • Paul Ampadu, University of Rochester, US, Contact
  • John Bainbridge, Sonics, US, Contact
  • Davide Bertozzi, University of Ferrara, IT, Contact
  • Luca Carloni, Columbia University, US, Contact
  • Koushik Chakraborty, Utah State University, US, Contact
  • Masoud Daneshtalab, UTU, FI, Contact
  • Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
  • Josè Flich, Universidad Politecnica de Valencia, ES, Contact
  • Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
  • Andreas Hansson, ARM Ltd, GB, Contact
  • Shaahin Hessabi, Sharif University of Technology, IR, Contact
  • Jung Ho Ahn, Seoul National University, KR, Contact
  • , Contact
  • Hiroki Matsutani, Keio University, JP, Contact
  • Steven Nowick, Columbia University, US, Contact
  • Pascal VIVET, CEA-LETI, FR, Contact
  • Sungjoo Yoo, POSTECH, KR, Contact

Architecture, modeling and design techniques for Networks-on-Chips; design methods and architectures for the on-chip interconnection network: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security, power management and fault tolerance; techniques and methodologies for NoC testing; GALS synchronization architectures for NoCs; physical design techniques and methodologies; integration of external interfaces/memory controllers with NoCs; cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; programming models for NoC-based platforms; industrial applications of NoCs; design of NoCs based on alternative technologies such as photonics/optics, wireless, 3D stacking.

D9 Architectural and Microarchitectural Design (click to open)

Chair: Tulika Mitra, National University of Singapore, SG, Contact

Co-Chair: Todd Austin, University of Michigan, US, Contact

Topic Members (click to open)

  • Kypros Constantinides, Microsoft, US, Contact
  • Henk Corporaal, TU/e, NL, Contact
  • Stijn Eyerman, Ghent University, BE, Contact
  • Georgi Gaydadjiev, Chalmers University, SE, Contact
  • Nikos Hardavellas, Northwestern University, US, Contact
  • Ahmed Hemani, Royal Institute of Technology, SE, Contact
  • Soontae Kim, KAIST, KR, Contact
  • Benjamin C. Lee, Duke University, US, Contact
  • Hsien-Hsin Lee, Georgia Institute of Technology, US, Contact
  • Yun (eric) Liang, Peking University, CN, Contact
  • Andreas Moshovos, University of Toronto, CA, Contact
  • Chrysostomos Nicopoulos, University of Cyprus, CY, Contact
  • Sri Parameswaran, UNSW, AU, Contact
  • Dionisios Pnevmatikatos, Technical University of Crete, GR, Contact
  • Laura Pozzi, University of Lugano, CH, Contact
  • muhammad [dot] shafique at tuwien [dot] ac [dot] at, Contact
  • Zili Shao, Hong Kong Polytechnic University, HK, Contact
  • Cristina SILVANO, Politecnico di Milano, IT, Contact
  • Sami Yehia, Intel, US, Contact

Architectural and micro-architectural design techniques, memory systems, power and energy efficient architectures, multi/many-core architectures, multi-threading techniques and support for parallelism, modeling and performance analysis, application-specific processors and accelerators, architectural support for reliability, security, timing predictability, architectures for emerging technologies and applications.

D10 High Level Synthesis (click to open)

Topic Members (click to open)

    Algorithms for resource scheduling, allocation, and binding; high level design languages; application-specific processor generation; memory and communication interface synthesis; control and data flow analysis; architectural and micro architectural optimizations; best practices for high level design tools and optimizations.

    D11 Reconfigurable Computing (click to open)

    Chair: Fadi Kurdahi, University of California at Irvine, US, Contact

    Co-Chair: Marco Platzner, University of Paderborn, DE, Contact

    Topic Members (click to open)

    • koen bertels, Delft University of Technology, NL, Contact
    • Fabrizio Ferrandi, Politecnico di Milano, IT, Contact
    • Diana Goehringer, Ruhr-University Bochum, DE, Contact
    • Yajun Ha, National University of Singapore, SG, Contact
    • Enno Luebbers, Intel Open Lab Munich, DE, Contact
    • Patrick Lysaght, Xilinx, US, Contact
    • Walid Najjar, UC Riverside, US, Contact
    • Smail Niar, University of Valenciennes, FR, Contact
    • Mazen Saghir, Texas A&M University, QA, Contact

    Statically and dynamically reconfigurable and reprogrammable systems and components: platforms and architectures, FPGAs, reconfigurable processors, design methods and tools for reconfigurable computing and communication, applications.

    D12 Logic Synthesis and Timing Analysis (click to open)

    Chair: José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact

    Co-Chair: Valentina Ciriani, University of Milano, IT, Contact

    Topic Members (click to open)

    • Michel Berkelaar, Delft University of Technology, NL, Contact
    • Jordi Cortadella, Universitat Politecnica de Catalunya, ES, Contact
    • Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
    • John Hayes, University of Michigan, US, Contact
    • Sanjay Kumar, Synopsys, US, Contact
    • Davide Pandini, STMicroelectronics, IT, Contact
    • Tiziano Villa, University of Verona, IT, Contact
    • Vladimir Zolotov, IBM T.J. Watson Research Center, US, Contact

    Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design, statistical timing analysis, timing closure; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; PLD and FPGA synthesis; arithmetic circuits.

    D13 Physical Synthesis and Verification (click to open)

    Chair: Ralph Otten, TU Eindhoven, NL, Contact

    Co-Chair: Patrick Groeneveld, Synopsys, US, Contact

    Topic Members (click to open)

    • Azadeh Davoodi, University of Wisconsin - Madison, US, Contact
    • Jens Lienig, Technical University of Dresden, DE, Contact
    • Sven Peyer, IBM, DE, Contact
    • Jose Pineda de Gyvez, NXP Semiconductors, NL, Contact
    • Carl Sechen, UT Dallas, US, Contact

    Floorplanning; automatic place and route; module generation; design rule checking; layout characterization; verification; deep sub-micron, high-speed design; interconnect-driven and performance-driven layout: process technology developments; design for manufacturability

    D14 Analog and Mixed-Signal Systems and Circuits (click to open)

    Chair: Catherine Dehollain, EPFL, CH, Contact

    Co-Chair: Günhan Dündar, Boğaziçi University, TR, Contact

    Topic Members (click to open)

    • Francisco Fernandez, IMSE, CSIC and University of Sevilla, ES, Contact
    • Georges Gielen, Katholieke Universiteit Leuven, BE, Contact
    • Christoph Grimm, TU Vienna, AT, Contact
    • Joachim Haase, Fraunhofer EAS, DE, Contact
    • Lars Hedrich, University of Frankfurt, DE, Contact
    • Tom Kazmierski, University of Southampton, GB, Contact
    • marie-Minerve Louerat, UNiversity Pierre & Marie Curie, LIP6, FR, Contact
    • Dominique MORCHE, CEA-LETI, FR, Contact

    CAD for analogue and mixed-signal circuits and systems: Layout, Topology generation, Architecture and System Synthesis, Modeling of AMS circuits and systems, Modeling strategies, Modeling of complex analogue mixed-signal systems, Model generation, Formal and Symbolic Techniques; Languages for AMS circuits and systems: VHDL-AMS, Verilog-AMS, SystemC-AMS, Matlab/Simulink, Ptolomy; Innovative circuit topologies and architectures: Topologies/architectures that increase robustness, Topologies/architectures that increase re-usability.

    D15 Parasitic Extraction, Modeling and Optimization of Interconnect, TSV and Power Grids (click to open)

    Chair: Stefano Grivet-Talocia, Politecnico di Torino, IT, Contact

    Co-Chair: Luca Daniel, Massachusetts Institute of Technology, US, Contact

    Topic Members (click to open)

    • Dipanjan Gope, Indian Institute of Science, IN, Contact
    • L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact
    • Dries Vande Ginste, University of Ghent, BE, Contact

    Electrical and thermal characterization, modeling and optimization of on and off chip interconnects, Through Silicon Vias (TSV), 3D interconnects, interposer, and packaging; wireless interconnects via capacitive/inductive coupling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate; EMC issues in interconnects: electromagnetic emission, susceptibility and compatibility; chip-package co-design; high-speed channel and equalizer modeling, design, and measurement; macro-modeling, behavioral, and reduced order modeling.

    Track A: Application Design (click to open)

    Application Design, is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as innovative design methodologies and applications of specific design technologies. Contributions should illustrate state-of-the-art or record-breaking designs, which will provide viable solutions in tomorrow’s silicon and embedded systems. In topic A7, there is the opportunity to submit short, 2-page papers that relate to industrial research and practice.

    Track Chair: David Atienza, EPFL, CH, Contact


    A1 Green Computing Systems (click to open)

    Chair: Ayse Coskun, Boston University, US, Contact

    Co-Chair: Martino Ruggiero, University of Bologna, IT, Contact

    Topic Members (click to open)

    • Cees De Laat, Univ. of Amsterdam, NL, Contact
    • Michael Kauschke, Intel GmbH, DE, Contact
    • Qinru Qiu, Syracuse University, US, Contact

    Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, high performance computing clusters, data centers, cloud systems and cyber-physical systems. Topics of interest include, but are not limited to: software architectures for parallel systems and cloud computing, virtualization, energy-efficient memory, processor, or communication architectures, heterogeneous computing, resource management techniques including adaptive/learning-based methods, innovative data-center management strategies, big-data management, data centers powered by renewable energy sources, and data centers in the smart-grids.

    A2 Communication, Consumer and Multimedia Systems (click to open)

    Chair: Theocharis Theocharides, University of Cyprus, CY, Contact

    Co-Chair: Sergio Saponara, University of Pisa, IT, Contact

    Topic Members (click to open)

    • Amer Baghdadi, TELECOM Bretagne, FR, Contact
    • Christos Bouganis, Imperial College, GB, Contact
    • Marcello Coppola, STMicroelectronics, FR, Contact
    • David Gnaedig, TurboConcept (company), FR, Contact
    • Guido Masera, Politecnico di Torino, IT, Contact
    • Steffen Paul, Unversity Bremen, DE, Contact
    • Ioannis Sourdis, Chalmers Univeristy of Technology, SE, Contact

    Practical design experience for communication, multimedia and consumer systems like smartphones, smart-books/tablets; examples are digital integrated circuits design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software-defined/cognitive radio systems; embedded systems design in the field of audio, video and computer vision domains; Application Specific Processors (ASP), Digital Signal Processors (DSP), Multi-Processor System on Chip (MPSoC) and Network on Chip (NoC) designs for these domains.

    A3 Automotive Systems and Smart Energy Systems  (click to open)

    Chair: Davide Brunelli, University of Trento, IT, Contact

    Co-Chair: Bart Vermeulen, NXP Semiconductors, NL, Contact

    Topic Members (click to open)

    • David Boyle, Imperial College London, GB, Contact
    • Martin Lukasiewycz, TUM CREATE, SG, Contact
    • Michele Magno, University of Bologna, IT, Contact
    • Albrecht Mayer, Infineon Technologies AG, DE, Contact
    • Geoff Merrett, University of Southampton, GB, Contact

    This topic covers works that describe design experiences for automotive systems, smart energy systems, energy scavenging and harvesting for embedded systems, and related applications. This includes analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures, integrated sensors and transducers, RF architectures, in-vehicle networks, systems for electric vehicles, networks of systems (including car-to-car and car-to-infrastructure networks), and innovative concepts for power distribution, energy storage, and grid monitoring. Furthermore, this topic also includes design methods including models and tools, design of hardware and software components, architecture analysis and optimization, component-oriented design and system-level analysis and validation. Finally, topics of interest are also hardware and software solutions for run-time system management, including self-diagnostics and repair, energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems, and optimization of system energy efficiency.

    A4 Ambient Intelligence and Ultra-Low Power Systems for Healthcare and Wellness (click to open)

    Chair: Srinivasan Murali, SmartCardia, CH, Contact

    Co-Chair: Elisabetta Farella, Fondazione Bruno Kessler, IT, Contact

    Topic Members (click to open)

    • Ana M. Bernardos, UPM, ES, Contact
    • Ani Nahapetian, UCLA, US, Contact
    • Julien Penders, IMEC/Holst Centrum, Eindhoven, NL, Contact
    • Francisco Rincon, EPFL, CH, Contact

    Medical, healthcare, and life science applications require increasingly smarter and smaller devices enabling to easily interact among each other, with the environment and with the users in a smooth and smart way. Personal and personalized medicine and rehabilitation is leading to a significant increase in both complex lab solutions as well as a myriad of consumer-like disposable devices. This topic covers the use of ambient intelligence, wireless body sensor networks and wearable technologies for healthcare, rehabilitation and wellness. This includes but it is not limited to: technologies for ultra-low/zero power systems for personal vital signs monitoring (such as heart rate, fitness devices); mobile system for motor rehabilitation and assessment; (bio)feedback system for rehabilitation and fitness based on wearable and mobile technologies; innovative implantable miniaturized sensors and actuators, personal health devices; power management, on-board performance optimization and networking technologies for body area networks and ambient intelligence in wellness, healthcare and fitness.

    A5 Secure Systems (click to open)

    Chair: Guido Bertoni, STMicroelectronics, IT, Contact

    Co-Chair: Patrick Schaumont, Virginia Tech, US, Contact

    Topic Members (click to open)

    • Ray Cheung, City University of Hong Kong, HK, Contact
    • Viktor Fischer, Laboratoire Hubert Curien, FR, Contact
    • Wieland Fischer, Infineon, DE, Contact
    • Tim Güneysu, Ruhr University Bochum, DE, Contact
    • Michael Hutter, Graz University of Technology, AT, Contact
    • Roel Maes, Intrinsic-ID, NL, Contact
    • Paolo Maistri, TIMA Laboratory, FR, Contact
    • Debdeep Mukhopadhyay, Indian Institute of Technology, IN, Contact
    • Jim Plusquellic, Univ. Of New Mexico, US, Contact
    • Axel Poschmann, Nanyang Technological University, SG, Contact
    • Francesco Regazzoni, Université catholique de Louvain and ALaRI, CH, Contact
    • Sebastien Tiran, LIRMM, FR, Contact
    • Alessandro Trifiletti, Sapienza Università di Roma, IT, Contact
    • Ingrid Verbauwhede, KU Leuven and UCLA, BE, Contact

    Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

    A6 Reliable and Reconfigurable Systems (click to open)

    Chair: jayala at ucm [dot] es, Contact

    Co-Chair: Marco D. Santambrogio, Politecnico di Milano, IT, Contact

    Topic Members (click to open)

    • Giovanni Ansaloni, École Polytechnique Fédérale de Lausanne, CH, Contact
    • Andrea Calimera, Politecnico di Torino, IT, Contact
    • , Contact
    • Oliver Pell, Maxeler Technologies, GB, Contact
    • , Contact
    • Vincenzo Rana, Politecnico di Milano, IT, Contact
    • Marian Verhelst, KULeuven - ESAT - MICAS, BE, Contact

    This topic covers the area of reliable and adaptive systems for practical applications. The scope of this topic includes, but not limited to, the development, optimization and practical application mechanisms to compensate for aging and temperature, development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

    A7 Industrial Experiences Brief Papers (click to open)

    Chair: Emil Matus, Technische Universität Dresden, DE, Contact

    Co-Chair: Roberto Zafalon, STMicroelectronics, IT, Contact

    Topic Members (click to open)

    • Hendrik Ahlendorf, ATMEL Automotive GmbH, DE, Contact
    • Benjamin Carrion Schafer, Hong Kong Polytechnic University, HK, Contact
    • Reimund Klemm, RadioOpt, DE, Contact
    • Norbert Wehn, TU Kaiserslautern, DE, Contact

    Short or brief papers with a limit of two pages are solicited that relate to industrial research and practice: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanism. Product presentations and announcements are strongly discouraged and will not be considered for publication.

    Track T: Test and Reliability (click to open)

    Covering all test, design-for-test, reliability and design-for-reliability issues, at system-, chip-, circuit-, and device-level. Including also diagnosis, failure mode analysis, debug and post-silicon validation challenges.

    Track Chair: Cecilia Metra, University of Bologna, IT, Contact


    T1 Defects, Faults, Variability and Reliability Analysis and Modeling (click to open)

    Chair: Robert Aitken, ARM, US, Contact

    Co-Chair: Joan Figueras, Universitat Politècnica Catalunya, ES, Contact

    Topic Members (click to open)

    • Kanak Agarwal, IBM Corp, US, Contact
    • Bartomeu Alorda, Illes Balears University, ES, Contact
    • Sandeep Gupta, University of Southern California, US, Contact
    • Bram Kruseman, NXP Semiconductors, NL, Contact
    • Kuen-Jong Lee, National Cheng Kung University, TW, Contact
    • Irith Pomeranz, Purdue University, US, Contact
    • Rosa Rodriguez, UPC, ES, Contact
    • Markus Rudack, Intel Mobile Communications GmbH, DE, Contact
    • Medhi Tahoori, KIT, DE, Contact
    • Li Wang, UC Santa Barbara, US, Contact

    Identification, characterization and modeling of defects, faults and degradation mechanisms; defect-based fault analysis; reliability analysis and modeling, Failure mode and effect analysis (FMEA) and physics of failures; noise and uncertainty modeling; test and reliability issues in emerging technologies; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations; process yield modeling and enhancement.

    T2 Test Generation, Simulation, Diagnosis and System Test (click to open)

    Chair: Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact

    Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

    Topic Members (click to open)

    • Piet Engelke, Infineon, DE, Contact
    • Nicola Nicolici, McMaster University, CA, Contact
    • matteo sonza reorda, politecnico di torino - DAUIN, IT, Contact
    • Arnau Virazel, LIRMM / Univ. Montpellier, FR, Contact
    • Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact

    Test pattern generation (TPG); fault simulation; high-level TPG; delay TPG; low-power TPG; TPG for memories and FPGAs; system test; diagnosis; debug; post-silicon validation; testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, System-on-Package, Package on Package, board, system; testing 3D chips; Network-on-Chip test; hardware/software system test; processor based test; infrastructure IP.

    T3 Test for Mixed-Signal, Analog, RF, MEMS/bioMEMS/MOEMS (click to open)

    Chair: haralampos [dot] stratigopoulos at lip6 [dot] fr, Contact

    Co-Chair: Andre Ivanov, UBC, CA, Contact

    Topic Members (click to open)

    • Abhijit Chatterjee, Georgia Tech, US, Contact
    • Hans Kerkhoff, University of Twente, NL, Contact
    • Gildas Leger, IMSE-CNM-CSIC, ES, Contact

    Test generation; test instrumentation; built-in test; built-in self-test; design-for test; defect characterization; failure analysis; fault modeling; fault simulation; defect-oriented test; test coverage metrics and estimation; adaptive test; self-healing/self-calibration/self-adaptation; design-for-manufacturability and design-for-yield; diagnosis and self-repair; test economics.

    T4 Design-for-Test, Test Compression, Test Access (click to open)

    Chair: Rohit Kapur, Synopsys, US, Contact

    Co-Chair: Paolo PRINETTO, Politecnico di Torino, IT, Contact

    Topic Members (click to open)

    • Peter Harrod, ARM, GB, Contact
    • Sybille Hellebrand, University of Paderborn, DE, Contact
    • Erik Jan Marinissen, IMEC, BE, Contact
    • Jerzy Tyszer, Poznan University of Technology, PL, Contact
    • Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact

    Design-for-test, -debug, and -manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DfT techniques, DfT for secure systems, DfT economics; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies.

    T5 On-Line Test, Fault Tolerance and Reliable System Design (click to open)

    Chair: Lorena Anghel, TIMA, FR, Contact

    Co-Chair: Fabrizio Lombardi, Northeastern University, US, Contact

    Topic Members (click to open)

    • Jaume Abella, Barcelona Supercomputing Center, ES, Contact
    • Dan Alexandrescu, iRoC Technologies, FR, Contact
    • Cristiana Bolchini, Politecnico di Milano, IT, Contact
    • Jie Han, Member IEEE, CA, Contact
    • Yiorgos Makris, Dallas University, US, Contact
    • Diana Marculescu, CMU, US, Contact
    • Michael Nicolaidis, TIMA, FR, Contact
    • Antonis Paschalis, University of Athens, GR, Contact
    • salvatore Pontarelli, University of Rome "Tor Vergata", IT, Contact
    • Pedro Reviriego, Universidad Antonio de Nebrija, ES, Contact
    • Andreas Steininger, Vienna University of Technology, AT, Contact
    • Xavier Vera, Intel, ES, Contact

    Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependability evaluation, reliable system design; redundant systems design; hardware/software recovery; self-repair; fault tolerance; on-line testing and fault tolerance for industrial applications.

    Track E: Embedded Systems Software (click to open)

    Embedded Systems Software is devoted to modelling, analysis, design and deployment of Embedded Software. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, realtime systems, cyber-physical systems, networked and dependable systems.

    Track Chair: , Contact


    E1 Real-time, Networked, and Dependable Systems (click to open)

    Chair: Giuseppe Lipari, ENS-Cachan, FR, Contact

    Co-Chair: Stefan M. Petters, CISTER-ISEP, IPP, PT, Contact

    Topic Members (click to open)

    • Benny Akesson, CISTER-ISEP Research Centre, Polytechnic Institute of Porto, PT, Contact
    • Iain Bate, University of York, GB, Contact
    • Tommaso Cucinotta, Alcatel-Lucent Bell Labs, Dublin, IR, Contact
    • Liliana Cucu, INRIA, FR, Contact
    • Arvind Easwaran, Nanyang Technical University, SG, Contact
    • Sebastian Fischmeister, University of Waterloo, CA, Contact
    • Gregor Gössler, INRIA, FR, Contact
    • Joel Goossens, Universite Libre de Bruxelles, BE, Contact
    • Raimund Kirner, University of Hertfortshire, GB, Contact
    • Kai Lampka, Uppsala University, SE, Contact
    • Chang-Gun Lee, Seoul National University, KR, Contact
    • Binoy Ravindran, Virginia Tech, US, Contact
    • Sebastian Stiller, TU Berlin, DE, Contact
    • Patrick Meumeu Yomsi, ISEP, PT, Contact
    • Dakai Zhu, University of Texas at San Antonio, US, Contact

    Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; tools and design methods for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications

    E2 Compilers for Embedded Systems (click to open)

    Chair: Heiko Falk, Ulm University, DE, Contact

    Co-Chair: Florence Maraninchi, Grenoble INP / Ensimag & VERIMAG, FR, Contact

    Topic Members (click to open)

    • Alain Darte, ENS Lyon - INRIA, FR, Contact
    • Frank Hannig, University of Erlangen-Nuremberg, DE, Contact
    • Huynh Phung Huynh, A*STAR Institute of High Performance Computing, SG, Contact
    • Rodric Rabbah, IBM Research, US, Contact
    • Jingling Xue, University of New South Wales, AU, Contact

    Compilers for embedded multi-core, heterogeneous, GPU, reconfigurable, or FPGA platforms; compiler-related tools for design space exploration, for iterative compilation, to complement HLS tools; just-in-time compilation and libraries for embedded and mobile devices; compiler support for enhanced debugging, profiling, and traceability; code analysis, optimization, and generation for different metrics (e.g., power, memory lifetime, WCET, etc.); compilation of domain specific or streaming languages for embedded systems; compilation tools for embedded systems as cloud services; certified compilers.

    E3 Model-based Design and Verification for Embedded Systems (click to open)

    Chair: Wang Yi, Uppsala University, SE, Contact

    Co-Chair: Saddek Ben Salem, Verimag, FR, Contact

    Topic Members (click to open)

    • Petru Eles, Linköping University, SE, Contact
    • Alain Girault, INRIA, FR, Contact
    • Kim Guldstrand Larsen, Aalborg University, DK, Contact
    • Roychoudhury Abhik, National University of Singapore, SG, Contact
    • Linh Thi Xuan Phan, University of Pennsylvania, US, Contact

    Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Model-based design of software architectures, and system integration and deployment. Theories, languages and tools supporting model-based design flows covering hardware, software, control and physical components; Case studies and industrial applications of model-based methods and tools for embedded systems design.

    E4 Embedded Software Architectures (click to open)

    Chair: Oliver Bringmann, FZI / University of Tuebingen, DE, Contact

    Co-Chair: Marc Geilen, TU Eindhoven, NL, Contact

    Topic Members (click to open)

    • Gero Dittmann, IBM, DE, Contact
    • Akash Kumar, Electrical and Computer Engineering, National University of Singapore, SG, Contact
    • Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
    • Orlando Moreira, ST-Ericsson, NL, Contact
    • Alex Orailoglu, UC San Diego, US, Contact
    • Gunar Schirner, Norhteastern University, US, Contact
    • Frank Slomka, Ulm University, DE, Contact

    Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; Virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; Software support for reconfigurable components and accelerators; Software architectures for low power and temperature awareness

    E5 Cyber-Physical Systems (click to open)

    Chair: Anuradha Annaswamy, MIT, US, Contact

    Co-Chair: Rolf Ernst, TU Braunschweig, DE, Contact

    Topic Members (click to open)

    • Jean-Dominique Decotignie, EPFL, CH, Contact
    • Joao Hespanha, UC Santa Barbara, US, Contact
    • Karl Johansson, Royal Institute of Technology, SE, Contact
    • Jonathan Sprinkle, University of Arizona, US, Contact

    Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); Modeling techniques for large-scale cyber physical systems design and analysis; Verification and validation in CPS; Safety and cybersecurity in CPS systems; Internet of things and CPS: modeling, analysis, and design; Software-intensive CPS; Data-mining and CPS; Autonomous and semi-autonomous large-scale CPS and related issues; Socio-technical systems (ex. empowered consumer and organizational behavior in smart grids) and CPS; Cognitive control for CPS; Modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis; Case studies in CPS ranging from healthcare, automotive systems, and avionics, to smart buildings and smart grids