M06 Testing of TSV-Based 2.5D- and 3D-Stacked ICs
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:30 | M06.1 | Session 1 |
| 00:00 | M06.1.1 | Introduction |
| 00:00 | M06.1.2 | Overview of 2.5D- and 3D-technology |
| 00:00 | M06.1.3 | 3D test flows and test contents |
| 00:00 | M06.1.4 | 3D test access: wafer probing (industry/research) |
| 11:30 | M06.2 | Session 2 |
| 00:00 | M06.2.1 | 3D test access: DfT architecture (incl. IEEE P1838) and optimizations |
| 00:00 | M06.2.2 | 3D cost flow modeling (with case studies) |
| 00:00 | M06.2.3 | Conclusion |
Groups:
