Tutorial
H2 Beyond DFT: The Convergence of DFM, Variability, Yield, Diagnosis and Reliability
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 13:00 | H2 | Lunch Break Buffet meal |
| 14:30 | H2.1 | Session 1 |
| 14:30 | H2.1.1 | Introduction and Background Rob Aitken, ARM, US |
| 15:00 | H2.1.2 | Yield and Fab Metrology Rob Aitken, ARM, US |
| 15:30 | H2.1.3 | DFM/Y - Design for Manufacturability and Yield Rob Aitken, ARM, US |
| 15:30 | H2.1.4 | Variability and DFV Rob Aitken, ARM, US |
| 16:00 | H2 | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 16:30 | H2.2 | Session 2 |
| 16:30 | H2.2.1 | DFT / Test and the link to Manufacturability Rob Aitken, ARM, US |
| 16:55 | H2.2.2 | Diagnosis and the Feedback Loop Rob Aitken, ARM, US |
| 17:20 | H2.2.3 | Reliability Rob Aitken, ARM, US |
| 17:45 | H2.2.4 | Putting it all together |
H1 Mixed-signal DfT & BIST: Trends, Principles, and Solutions
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:30 | H1.1 | Session 1 |
| 09:30 | Trends, and Review of IEEE Standards Stephen Sunter, Mentor Graphics, US | |
| 11:00 | H1 | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 11:30 | H1.2 | Session 2 |
| 11:30 | BIST Principles, and Techniques for New DFT Stephen Sunter, Mentor Graphics, US | |
| 13:00 | H1 | Lunch Break Buffet meal |
G Design Methodologies for Adaptive Circuits and Systems
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:30 | G.1 | Session 1 |
| 09:00 | G.1.1 | Introduction and Motivation Saibal Mukhopadhyay, Georgia Institute of Technology, US |
| 10:15 | G.1.2 | Adaptive Logic Circuits Saibal Mukhopadhyay, Georgia Institute of Technology, US |
| 11:00 | G | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 11:30 | G.2 | Session 2 |
| 11:30 | Adaptive SRAM Circuits Arijit Raychowdhury, Georgia Institute of Technology, US | |
| 13:00 | G | Lunch Break Buffet meal |
| 14:30 | G.3 | Session 3 |
| 14:30 | Adaptive Architecture Sudhakar Yalamanchili, Georgia Institute of Technology, US | |
| 16:00 | G | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 16:30 | G.4 | Session 4 |
| 16:00 | G.7.1 | Adaptive Wireless Systems Abhijit Chatterjee, Georgia Institute of Technology, US |
| 17:15 | G.7.2 | Conclusion and Discussion Saibal Mukhopadhyay, Abhijit Chatterjee, Sudhakar Yalamanchili and Arijit Raychowdhury, Georgia Institute of Technology, US |
F Post-Silicon Validation: Old Challenges and New Solutions
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:30 | F.1 | Session 1 |
| 09:30 | Post-silicon bugs and industry tools Rand Gray1 and Wisam Kadry2 1Intel Corp, US; 2IBM, IL | |
| 11:00 | F | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 11:30 | F.2 | Session 2 |
| 11:30 | Post-silicon monitoring infrastructures Valeria Bertacco1 and Sharad Malik2 1University of Michigan, US; 2Princeton University, US | |
| 13:00 | FM1 | Challenges in Design and Qualification for Automotive Electronics Organisers: This is a focused meeting on design and qualification challenges for electronic circuits used in automotive systems. It will be conducted in free format, where practitioners and experts will share state-of-the-art practices and user experiences, and discuss new challenges in this area. Topics likely to be covered include adoption of automotive safe standards, compliance checks and certification processes, IC component vs overall system reliability, time zero screens vs life time failure estimation, firmware qualification and co-design requirements. |
| 13:00 | F | Lunch Break Buffet meal |
| 14:30 | F.3 | Session 3 |
| 14:30 | Bug localization. Microprocessor's solutions Valeria Bertacco1 and Sharad Malik2 1University of Michigan, US; 2Princeton University, US | |
| 16:00 | F | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 16:30 | F.4 | Session 4 |
| 16:30 | Post-silicon methodologies in the industry Rand Gray1 and Wisam Kadry2 1Intel Corp, US; 2IBM, IL | |
| 19:00 | FM2 | ACM SIGDA / EDAA PhD Forum PhD Forum Committee Chair: PhD Forum Committee Members: The ACM SIGDA / EDAA PhD forum is part of the DATE Conference and hosted by ACM SIGDA and the European Design Automation Association (EDAA). It offers the opportunity for PhD students to present their thesis work to a broad audience in the design, automation and test community from academia and industry. During the presentation at the DATE Conference, it helps students to establish contacts. Also, representatives from industry and academia get a glance of state-of-the-art research in design, automation and test. The review process resulted in the selection of the PhD students listed below. We thank ACM SIGDA, EDAA, and DATE for making this Forum possible. Peter Marwedel (Chair, ACM SIGDA / EDAA PhD Forum at DATE 2013) |
| 19:00 | PhD.1 | Energy Consumption Information in High-level Models Laurent Bousquet, Tima Laboratory, Grenoble, FR |
| 19:00 | PhD.2 | OpenMP extensions to Exploit HW Acceleration on Shared-Memory Many-Core Clusters Paolo Burgio, University of Bologna, IT |
| 19:00 | PhD.3 | Out-of-order Parallel Simulation for Electronic System-Level Design Weiwei Chen, UC Irvine, US |
| 19:00 | PhD.4 | On Efficient Management of Flash Memory for Long Lifetime and High Performance Wang Chundong, National University of Singapore, SG |
| 19:00 | PhD.6 | A Resilient Framework for Post-Silicon Delay Validation of High Performance Circuits Prasanjeet Das, University of Southern California, US |
| 19:00 | PhD.7 | Self-adaptivity of Applications on Network on Chip Multiprocessors: The Case of Fault-Tolerant Kahn Process Networks Onur Derin, University of Lugano, CH |
| 19:00 | PhD.8 | Modeling and Synthesis of the Network in Distributed Embedded Systems Emad Ebeid, University of Verona, IT |
| 19:00 | PhD.9 | Path-based Partitioning Methods for 3D NoCs with Minimal Adaptive Routing Masoumeh Ebrahimi, University of Turku, FI |
| 19:00 | PhD.10 | Architectural Exploration Methods and Tools for Heterogeneous 3D-IC Felipe F. Ferreira, Lyon Institute of Nanotechnology, FR |
| 19:00 | PhD.11 | Working With Adaptive NoC Routers John Jose, IIT Madras, IN |
| 19:00 | PhD.12 | Energy-Aware Multi-Threaded Software Systems: An Overview Steve Kerrison, University of Bristol, UK |
| 19:00 | PhD.13 | On Optimizing Dynamic Memory Allocators Ioannis Koutras, National Technical University of Athens, GR |
| 19:00 | PhD.14 | FPGA-based Hardware Accelerators for Embedded Object Detection Systems Christos Kyrkou, University of Cyprus, CY |
| 19:00 | PhD.15 | Built In Self Test of Pipeline Analog-to-Digital Converters Asma Laraba, Tima Laboratory,Grenoble, FR |
| 19:00 | PhD.16 | Automated Techniques for Verification-driven Design at the Electronic System Level Hoang Le, University of Bremen, DE |
| 19:00 | PhD.17 | High-Speed Interconnect Models with Stochastic Parameter Variability Paolo Manfredi, Politecnico di Torino, IT |
| 19:00 | PhD.18 | Microarchitectures for Hybrid High and Ultra-low Voltage Operation Bojan Maric, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES |
| 19:00 | PhD.19 | Design Entropy Benjamin Menhorn, Ulm University, DE |
| 19:00 | PhD.20 | Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits Srobona Mitra, IBM India Pvt Ltd, IN |
| 19:00 | PhD.21 | Assertions: From a Mixed-Signal Perspective Subhankar Mukherjee, IIT Kharagpur, IN |
| 19:00 | PhD.22 | Towards Optimized Flexible Multi-ASIP Architectures for LDPC/Turbo Decoding Purushotham Murugappa, Telecom Bretagne, FR |
| 19:00 | PhD.23 | Performance Analysis of Complex Real-Time Applications on Multi-Core Systems with Shared Resources Mircea Negrean, TU Braunschweig, DE |
| 19:00 | PhD.24 | Composable Execution of Mixed-Criticality Embedded Applications With Mixed-Models-of-Computation Ashkan Beyranvand Nejad, Delft University of Technology, NL |
| 19:00 | PhD.25 | Composable Application-level Power Management for Real-Time Embedded Systems Andrew Nelson, Delft University of Technology, NL |
| 19:00 | PhD.26 | RSSI-based Localisation of Mobile Robots With Online Channel Estimation Luis Olivera, University of Porto, PT |
| 19:00 | PhD.27 | Improving Performance of FPGAs Using Resistive Switching Memory (RRAM) Based Low Power Circuit Architectures Santhosh Onkaraiah, CEA-Leti, Minatec, FR |
| 19:00 | PhD.28 | Capacity Metric for Chip Heterogeneous Multiprocessors Mwaffaq Otoom, Yarmouk University, JO |
| 19:00 | PhD.29 | System-Level Approaches for Fixed-Point Refinement of Signal Processing Algorithms Karthik Parashar, INRIA Bretagne Atlantique, Rennes, FR |
| 19:00 | PhD.30 | Model Checking Memory-Related Properties of SystemC Transaction Level Designs Marcel Pockrandt, TU Berlin, DE |
| 19:00 | PhD.31 | Soft Error Mitigation in Asynchronous Networks on Chip Julian Pontes, Universidade Católica do Rio Grande do Sul, BR |
| 19:00 | PhD.32 | A Reconfigurable Low-Latency Architecture for Real-Time Image and Video Processing Paulo Possa, University of Mons, BE |
| 19:00 | PhD.33 | Thread Assignment of Network Applications in Multithreaded Processors: A Statistical Approach Petar Radojkovic, Barcelona Super Computer Center, ES |
| 19:00 | PhD.34 | Reliable Software for Unreliable Hardware Semeen Rehman, Karlsruhe Institute of Technology, DE |
| 19:00 | PhD.35 | Verification of Hybrid DEVS Models Hesham Saadawi, Carleton University, Ottawa, CA |
| 19:00 | PhD.36 | MiMAPT: Adaptive Multi-Resolution Thermal Analysis at RT and Gate Level Mohammadsadegh Sadri, University of Bologna, IT |
| 19:00 | PhD.38 | Variability, Regularity and DFM Metrics Kasyab Parmesh Subramaniyan, Chalmer University, SE |
| 19:00 | PhD.40 | Disparity Estimation Hardware Architectures and Design Techniques for Embedded Stereo Vision Applications Christos Ttofis, University of Cyprus, CY |
| 19:00 | PhD.42 | Low Power and High Performance Current Mode On-Chip Interconnect System Design and Optimization Xinsheng Wang, Harbin Institute of Technology, Harbi, CN |
| 13:00 | FM3 | IEEE European Test Technology Technical Council (ETTTC) Meeting Organiser: |
| 18:30 | FM4 | EDAA General Assembly Organiser: |
| 18:30 | FM5 | 27. European SystemC Users' Group Meeting Organiser: The European SystemC Users' Group (ESCUG) announces its 27th meeting at DATE Conference 2013 on Tuesday, March 19th, 2013, 18:30 h (closing 21:30 h). The 27th European SystemC Users' Group Meeting encompasses not only SystemC but the wider picture of Accellera standards and technologies, such as UVM, SystemVerilog, SVA, and IP-XACT. This meeting will be organized in town hall style, giving experts from Accellera a platform to introduce these design and verification technologies and providing the audience an opportunity to join interesting discussion. Please register here. We're looking forward to meeting you in Grenoble! |
| 18:30 | FM1.1 | Opening and Welcome Oliver Bringmann, University of Tuebingen, DE |
| 18:45 | FM1.2 | Accellera News Update Dennis Brophy, Accellera Systems Initiative, US |
| 19:15 | FM1.3 | Accellera Systems Initiative Presentstion Dennis Brophy1, Martin Barnasconi2 and Laurent Maillet-Contoz3 1Accellera Systems Initiative, US; 2Accellera Systems initiative, NL; 3Accellera Systems Initiative, FR |
| 20:15 | FM1.4 | Interactive Discussion |
| 21:15 | FM1.5 | Wrap-Up and Closing Oliver Bringmann, University of Tuebingen, DE |
E2 Design and Verification of Embedded Systems from Natural Language Descriptions
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 13:00 | E2 | Lunch Break Buffet meal |
| 14:30 | E2.1 | Session 1 |
| 14:30 | E2.1.1 | Introduction and Envisioned Design Flow Robert Wille, University of Bremen, DE |
| 14:45 | E2.1.2 | Natural Language Processing Ian G. Harris, University of California, Irvine, US |
| 15:30 | E2.1.3 | Deriving Formal Specifications Through NLP Rolf Drechsler, DFKI GmbH, DE |
| 16:00 | E2 | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 16:30 | E2.2 | Session 2 |
| 16:30 | E2.2.1 | Verification of Formal Specifications Robert Wille, University of Bremen, DE |
| 17:00 | E2.2.2 | Code Generation Wolfgang Ecker1 and Rainer Findenig2 1Infineon Technologies, DE; 2Intel Mobile Communications, AT |
| 17:45 | E2.2.3 | Conclusion and Open Research Questions Rolf Drechsler, DFKI GmbH, DE |
E1 Assertion Based Verification: a Common Verification Infrastructure for SoC and Embedded Software
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:30 | E1.1 | Session1 |
| 09:30 | E1.1.1 | Introduction to ABV and PSL Graziano Pravadelli, Università di Verona, IT |
| 10:00 | E1.1.2 | ABV for SoC Masahiro Fujita, University of Tokyo, JP |
| 11:00 | E1 | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 11:30 | E1.2 | Session 2 |
| 11:30 | E1.2.1 | Dynamic ABV for embedded SW Giuseppe Di Guglielmo, Columbia University, US |
| 12:30 | E1.2.2 | ABV and the IEC 60730 safety standard Cristina Marconcini, STM Product, IT |
| 13:00 | E1 | Lunch Break Buffet meal |
D2 Hardware Security and Trust
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 13:00 | D2 | Lunch Break Buffet meal |
| 14:30 | D2.1 | Session 1 |
| 15:00 | D2.1.2 | Malicious modifications (hardware trojans) to designs and counterfeit ICs Yiorgos Makris, University of Texas at Dallas, US |
| 14:30 | D2.1.1 | Introduction, motivation, hardware security primitives Ramesh Karri, Polytechnic Institute of New York University, US |
| 16:00 | D2 | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 16:30 | D2.2 | Session 2 |
| 16:30 | D2.2.1 | IC reverse engineering, overbuilding and IP piracy Ozgur Sinanoglu, New York University Abu Dhabi, AE |
| 17:30 | D2.2.2 | Design for Test vulnerabilities and countermeasures Ramesh Karri, Polytechnic Institute of New York University, US |
Speaker bios:
Ramesh Karri (Member, IEEE) received the BE in Electronics and Communications Engineering from Andhra University in 1985, MS in Computer Science from University of Hyderabad in 1988, MS in Computer Engineering and Ph.D. degree in computer science from the University of California San Diego, La Jolla in 1992 and 1993 respectively. He is a Professor in the Electrical and Computer Engineering Department, Polytechnic Institute of New York University. His research interests include trustworthy hardware design and the interaction between security and reliability. He has published over a hundred conference and journal articles in these areas. He has received the NSF CAREER Award and the Alexander Humboldt Fellowship. He is serving as the program chair of the 2012 IEEE Symposium on Hardware oriented Security and Trust (HOST 2012). He is an Associate Editor of the IEEE Transactions on Information Forensics and Security and the ACM Journal of Emerging Technologies in Computing Systems. He has served or is currently serving on several conference program committees.
Yiorgos Makris is an associate professor in the department of Electrical Engineering at UT Dallas. Prior to that he was at Yale University. He received a Ph.D. (2001) and an M.S. (1997) in Computer Engineering from the University of California, San Diego, and a Diploma of Engineering (1995) in Computer Engineering and Informatics from the University of Patras, Greece. His main research interests lie in the application of machine learning and statistical analysis towards developing reliable and trusted integrated circuits, with particular emphasis in the analog/RF domain. He is also investigating error detection and correction methods for modern microprocessors, as well as novel computational modalities using emerging technologies. His research activities have been supported by NSF, SRC, DARPA, Boeing, IBM, LSI, Intel, and TI. He is the program chair of the 2013 VLSI Test Symposium and has served as a guest editor for the IEEE Transactions on Computers and as a committee member for several IEEE and ACM conferences. He is a Senior Member of the IEEE and a recipient of the 2006 Sheffield Distinguished Teaching Award.
Ozgur Sinanoglu is a Faculty of Engineering at New York University in Abu Dhabi. Prof. Ozgur Sinanoglu obtained his Ph.D. in Computer Science and Engineering from University of California, San Diego, in 2004. During his PhD, he was given the IBM PhD Fellowship Award in two consecutive years in 2001 and 2002, and his PhD thesis won the CSE PhD Dissertation Award in UCSD in 2005. He worked for two years at Qualcomm in San Diego as a senior Design-for-Testability engineer, primarily responsible for developing cost-effective test solutions for low-power SOCs. After a 4-year academic experience at Kuwait University, where he was given two research awards, he has joined in Fall 2010 New York University in Abu Dhabi. Upon spending his integration year as a visiting Faculty in New York at the ECE Department of NYU Poly, he joined the Faculty in Abu Dhabi in Fall 2011. His primary field of research is the reliability and trust of integrated circuits, mostly focusing on design-for-testability. He has around 100 conference and journal papers in addition to 3 issued and several pending patents. He is the recipient of the Best Paper Award of VLSI Test Symposium 2011.
D1 Digital Microfluidic Biochips: Towards Hardware/Software Co-Design and Cyberphysical System Integration
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:30 | D1.1 | Session 1 |
| 09:30 | D1.1.1 | Technology overview Krishnendu Chakrabarty, Duke University, US |
| 10:15 | D1.1.2 | Fluidic synthesis methods Tsung-Yi Ho, National Cheng Kung Univ., TW |
| 11:00 | D1 | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 11:30 | D1.2 | Session 2 |
| 11:30 | D1.2.1 | Chip design Tsung-Yi Ho, National Cheng Kung Univ., TW |
| 12:00 | D1.2.2 | Cyberphysical integration Krishnendu Chakrabarty, Duke University, US |
| 12:30 | D1.2.3 | Dynamic reconfiguration Krishnendu Chakrabarty, Duke University, US |
| 13:00 | D1 | Lunch Break Buffet meal |
C E-Health: Systems, Components, Technologies
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:00 | C.1 | Session 1 |
| 09:00 | C.1.1 | Introduction, motivation and big picture Rudy Lauwereins, IMEC, BE |
| 11:00 | C | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 11:30 | C.2 | Session 2 |
| 11:30 | C.2.1 | Survey of biosensors for medical applications Sven Ingebrandt, University of Kaiserslautern, DE |
| 12:15 | C.2.2 | Biosensor integration Carlotta Guiducci, École Polytechnique Fédérale de Lausanne, CH |
| 13:00 | C | Lunch Break Buffet meal |
| 14:30 | C.3 | Session 3 |
| 14:30 | C.3.1 | MEMS for health applications Benedetto Vigna, STMicroelectronics, IT |
| 16:00 | C | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 16:30 | C.4 | Session 4 |
| 16:30 | C.4.1 | System design issues in e-health applications Wayne Burleson, University of Massachusetts Amherst, US |
| 17:15 | C.4.2 | Case studies and conclusions Giovanni De Micheli, École Polytechnique Fédérale de Lausanne, CH |
B Advanced Techniques for Power-Aware System-Level Prototyping
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 09:30 | B.1 | Session 1 |
| 09:30 | B.1.1 | Introduction and tutorial overview Frank Oppenheimer, OFFIS, DE |
| 10:00 | B.1.2 | An MDD Methodology for Specification and Performance Estimation of Embedded Systems Eugenio Villar, Universidad de Cantabria, ES |
| 11:00 | B | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 11:30 | B.2 | Session 2 |
| 11:30 | B.2.1 | Virtual Platform Generation, Integration and Extension of Extra-Functional Properties Emmanuel Vaumorin, Magillem, FR |
| 12:00 | B.2.2 | Industrial experience report for model-based design in space/aerospace applications (demo) Francisco Ferrero, GMV AD, ES |
| 13:00 | B | Lunch Break Buffet meal |
| 14:30 | B.3 | Session 3 |
| 14:30 | B.3.1 | From RTL IP to Functional System-Level Models with Extra-Functional Properties Davide Quaglia, EDALab, IT |
| 15:15 | B.3.2 | High-Level Synthesis-based Hardware Power and Timing Estimation Philipp A. Hartmann, OFFIS, DE |
| 16:00 | B | Coffee Break Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme. |
| 16:30 | B.4 | Session 4 |
| 16:30 | B.4.1 | Software Power and Timing Estimation Carlo Brandolese, Politecnico di Milano, IT |
| 17:00 | B.4.2 | Network-aware Design-Space Exploration of a Power-Efficient Embedded Application (demo) Sara Bocchio, STMicroelectronics, IT |
| 17:30 | B.4.3 | Summary and Closing remarks Frank Oppenheimer, OFFIS, DE |
A Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead A Tribute to Robert Brayton
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 08:15 | A.1 | Opening Session |
| 08:30 | A.2 | Simulation and Circuit Design |
| 08:30 | A.2.1 | EDA beyond Electronics: Anecdotal Evidence in Systems Biology, MRI Optimization, and Electric Vehicle Simulation Jacob White, MIT, US |
| 09:00 | A.2.2 | Phase Logic Using Self-Sustaining Nonlinear Oscillators Jaijeet Roychowdhury, University of California, Berkeley, US |
| 09:30 | A.3 | Logic Synthesis and Computer Architecture |
| 09:30 | A.3.1 | Towards the Unification of Synthesis and Verification in Logic and Architectural Design Masahiro Fujita, University of Tokyo, JP |
| 10:00 | A.3.2 | From 2-Level to Architectural Synthesis: a Long Trip for Design Automation Jordi Cortadella, Universitat Politècnica de Catalunya, ES |
| 10:30 | A.3.3 | Decomposition of Boolean Expressions 30 Years After the First Algebraic Factoring Algorithm Victor Kravets, IBM, US |
| 11:00 | A.4 | Physical Design and Timing Analysis |
| 11:00 | A.4.1 | Space (and Physical Design): the Final Frontier for VLSI Igor Markov, University of Michigan, US |
| 11:30 | A.4.2 | Technology-Based Logic Transforms Rajeev Murgai, Synopsys, IN |
| 12:00 | A | Lunch Break Buffet meal |
| 13:00 | A.5 | Formal Verification and Equivalence Checking |
| 13:00 | A.5.1 | Combining Algorithms to Solve Intractable Problems Ken McMillan, Microsoft, US |
| 13:30 | A.5.2 | Integrating Induction and Deduction for Verification and Synthesis Sanjit Seshia, University of California, Berkeley, US |
| 14:00 | A.6 | New Frontiers of EDA |
| 14:00 | A.6.1 | New Frontiers of Logic Design Tools Giovanni De Micheli, Ecole Polyt. de Lausanne, CH |
| 14:30 | A.6.2 | Bio-Design Automation: Designing Genetic Circuits with EDA Principles Douglas Densmore, Boston University, US |
| 15:00 | A.7 | Formal Models |
| 15:00 | A.7.1 | Error Localization using Maximal Satisfiability Rupak Majumdar, University of California, Los Angeles, US |
| 15:30 | A.7.2 | The Unknown Component Problem Alexandre Petrenko, CRIM, CA |
| 16:00 | A.8 | System Design |
| 16:00 | A.8.1 | From Latency-Insensitive to Communication-Based System- Level Design Luca Carloni, Columbia University, US |
| 16:30 | A.8.2 | EDA: the Last 40 Years and the next 20 Years Alberto Sangiovanni-Vincentelli, University of California, Berkeley, US |
| 17:00 | A.9 | Conclusions Moderators: |
Robert Brayton
Robert Brayton received the BSEE degree from Iowa State University in 1956 and the Ph.D. degree in mathematics from MIT in 1961. He was a member of the Mathematical Sciences Department of the IBM T. J. Watson Research Center until he joined the EECS Department at Berkeley in 1987. He held the Edgar L. and Harold H. Buttner Endowed Chair and retired as the Cadence Distinguished Professor of Electrical Engineering at Berkeley.
He is a member of the US National Academy of Engineering, an IEEE Fellow, and has received the following awards: IEEE Guilleman-Cauer (1971), ISCAS Darlington (1987), IEEE CAS Technical Achievement (1991), IEEE Emanuel R. Piore (2006), ACM Kanallakis (2006), European DAA Lifetime Achievement (2006), EDAC/CEDA Phil Kaufman (2007), D.O. Pederson best paper in Trans. CAD (2008), ACM/IEEE A. Richard Newton Technical Impact in EDA (2009), Iowa State University Distinguished Alumnus (2010), SRC Technical Excellence (2011) and ACM/SIGDA Pioneering Achievement (2011).
He has co-authored over 460 technical papers, and 11 books in the areas of the analysis of nonlinear networks, simulation and optimization of electrical circuits, logic synthesis, and formal design verification.
